From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::143; helo=mail-it1-x143.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x143.google.com (mail-it1-x143.google.com [IPv6:2607:f8b0:4864:20::143]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id D228F211B5071 for ; Tue, 22 Jan 2019 10:15:27 -0800 (PST) Received: by mail-it1-x143.google.com with SMTP id g76so23005623itg.2 for ; Tue, 22 Jan 2019 10:15:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=86G37D6/9CRfKO8pzQpnXFiU7xn4k+FxgalHYimT+bM=; b=CED0TUtnmeV5Jhf23MI/nIrJ8LXpQVGtNSrdH00qcmDeFqU9SHWOQwY7XQpuZxrFq0 RNNjQhqCQtroNmS1a3uM/pQVG/fzsWvdVvtHL35EGxlJgztJYnlD3trdqx5Jw9bdRt6Q MZveupkp5RVGNMH7nRsw46dYFH0+MmNqu11t5SS6ZtRLpTW+l6jsBOfGFmf54BMrLbPK yXeMoxw3JKoQ2hS4SWV6+MEjPaKnB6tomwNRgcQ+RjjAZo1CRdlz0DmIqK2rW3kFG8ya eb4RIDjsQC3851Zhts5Y7j9pGL96KJ8G2UEZhGE9PhOYveG/DN3XA6Kj2eR4XdyCX+LQ +g3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=86G37D6/9CRfKO8pzQpnXFiU7xn4k+FxgalHYimT+bM=; b=ItWj4SAYo0E9MVWoRhey4ldMCkgTeBAChGZA+2G1X+RSA6SGpmqublGk6YffqefV+w p7MhPBtG7ZGiGVj91TBYh8zGIBZOUhLnxcskDYM6n1DOwEe7AO6WpUFda5mIsDmSoYBM W1OUGdsAXWoV5+UcMPHHe9xWY6BAx+6Ze5AdGAhd8kcRtd707bkv8H3MfaDh4N+BZQbv x82z+eG6Dp/yrnWvbRBa1pf/yLfS+2Fcm36v7qL8jfuoSTkZuZBQcaJrO6YxBEdFd78x nYyXAaaZC+oWU6BPXthL7oJbc+ET5tSAU1E9qhdxju7E3gGL/8zRZ+3Gfc9kbFntnk9M jKeQ== X-Gm-Message-State: AJcUukfo3bio+wK5yH3JBy5LsgqKQwEdu1imqkXa+hJGt7hSi5sjpwK6 Sgt9Q2ITm8573rD9mJS+7P005iHoer4dpNAe/gDaZA== X-Google-Smtp-Source: ALg8bN5Iy1ti3LA9mB3fyFlzDytGZ1NUszehHCWvjFwVTxNGLlLJ6ZLXeOydyD6INe/jRuqiB85k3WH/flRQKvl94NY= X-Received: by 2002:a24:eb0b:: with SMTP id h11mr2786701itj.138.1548180926771; Tue, 22 Jan 2019 10:15:26 -0800 (PST) MIME-Version: 1.0 References: <1548120742-11928-1-git-send-email-mw@semihalf.com> <1548120742-11928-3-git-send-email-mw@semihalf.com> <20190122173559.7nuidsdtoxoiexag@bivouac.eciton.net> In-Reply-To: <20190122173559.7nuidsdtoxoiexag@bivouac.eciton.net> From: Marcin Wojtas Date: Tue, 22 Jan 2019 19:15:15 +0100 Message-ID: To: Leif Lindholm Cc: edk2-devel-01 , Ard Biesheuvel , nadavh@marvell.com, "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Subject: Re: [platforms: PATCH v2 2/4] Marvell/Library: Introduce common header for the SMC ID's X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Jan 2019 18:15:28 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, wt., 22 sty 2019 o 18:36 Leif Lindholm napisa=C5= =82(a): > > On Tue, Jan 22, 2019 at 02:32:20AM +0100, Marcin Wojtas wrote: > > Marvell firmware allows to use SiP services other than > > for ComPhy handling. In order to avoid spreading the SMC > > ID's definitions across many files, introduce common header > > for that purpose. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Include/Library/MvSmc.h | 23 ++++++++++++++++= ++++ > > Final nitpick: This isn't a library. > IndustryStandard is probably a better approximation. (You are > effectively extending ArmPkg/Include/IndustryStandard/ArmStdSmc.h with > vendor-specific bits.) > Ok, I will move MvSmc.h to such location. Thanks, Marcin > With that change: > Reviewed-by: Leif Lindholm > > / > Leif > > > Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h | 8 +++---- > > Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c | 14 ++++++------ > > 3 files changed, 33 insertions(+), 12 deletions(-) > > create mode 100644 Silicon/Marvell/Include/Library/MvSmc.h > > > > diff --git a/Silicon/Marvell/Include/Library/MvSmc.h b/Silicon/Marvell/= Include/Library/MvSmc.h > > new file mode 100644 > > index 0000000..2d1542a > > --- /dev/null > > +++ b/Silicon/Marvell/Include/Library/MvSmc.h > > @@ -0,0 +1,23 @@ > > +/** > > +* > > +* Copyright (C) 2019, Marvell International Ltd. and its affiliates. > > +* > > +* This program and the accompanying materials are licensed and made a= vailable > > +* under the terms and conditions of the BSD License which accompanies= this > > +* distribution. The full text of the license may be found at > > +* http://opensource.org/licenses/bsd-license.php > > +* > > +* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASI= S, > > +* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS O= R IMPLIED. > > +* > > +**/ > > + > > +#ifndef __MV_SMC_H__ > > +#define __MV_SMC_H__ > > + > > +/* Marvell SiP services SMC ID's */ > > +#define MV_SMC_ID_COMPHY_POWER_ON 0x82000001 > > +#define MV_SMC_ID_COMPHY_POWER_OFF 0x82000002 > > +#define MV_SMC_ID_COMPHY_PLL_LOCK 0x82000003 > > + > > +#endif //__MV_SMC_H__ > > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h b/Silicon= /Marvell/Library/ComPhyLib/ComPhySipSvc.h > > index d156af6..f6ac65b 100644 > > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h > > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhySipSvc.h > > @@ -35,16 +35,14 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUC= H DAMAGE. > > #ifndef __COMPHY_SIP_SVC_H__ > > #define __COMPHY_SIP_SVC_H__ > > > > +#include > > + > > /* > > * All values in this file are defined externally and used > > * for the SerDes configuration via SiP services. > > */ > > > > -/* Firmware related definitions used for SMC calls */ > > -#define MV_SIP_COMPHY_POWER_ON 0x82000001 > > -#define MV_SIP_COMPHY_POWER_OFF 0x82000002 > > -#define MV_SIP_COMPHY_PLL_LOCK 0x82000003 > > - > > +/* Helper macros for passing ComPhy parameters to the EL3 */ > > #define COMPHY_FW_MODE_FORMAT(mode) (mode << 12) > > #define COMPHY_FW_FORMAT(mode, idx, speeds) \ > > ((mode << 12) | (idx << 8) | (spee= ds << 2)) > > diff --git a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c b/Silicon/= Marvell/Library/ComPhyLib/ComPhyCp110.c > > index 2abb006..4f85676 100755 > > --- a/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c > > +++ b/Silicon/Marvell/Library/ComPhyLib/ComPhyCp110.c > > @@ -163,7 +163,7 @@ ComPhySataPowerUp ( > > > > ComPhySataMacPowerDown (Desc[ChipId].SoC->AhciBaseAddress); > > > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > ComPhyBase, > > Lane, > > COMPHY_FW_FORMAT (COMPHY_SATA_MODE, > > @@ -175,7 +175,7 @@ ComPhySataPowerUp ( > > > > ComPhySataPhyPowerUp (Desc[ChipId].SoC->AhciBaseAddress); > > > > - Status =3D ComPhySmc (MV_SIP_COMPHY_PLL_LOCK, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_PLL_LOCK, > > ComPhyBase, > > Lane, > > COMPHY_FW_FORMAT (COMPHY_SATA_MODE, > > @@ -234,7 +234,7 @@ ComPhyCp110Init ( > > case COMPHY_TYPE_PCIE1: > > case COMPHY_TYPE_PCIE2: > > case COMPHY_TYPE_PCIE3: > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > PtrChipCfg->ComPhyBaseAddr, > > Lane, > > COMPHY_FW_PCIE_FORMAT (PcieWidth, > > @@ -269,7 +269,7 @@ ComPhyCp110Init ( > > break; > > case COMPHY_TYPE_USB3_HOST0: > > case COMPHY_TYPE_USB3_HOST1: > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > PtrChipCfg->ComPhyBaseAddr, > > Lane, > > COMPHY_FW_MODE_FORMAT (COMPHY_USB3H_MODE)); > > @@ -278,7 +278,7 @@ ComPhyCp110Init ( > > case COMPHY_TYPE_SGMII1: > > case COMPHY_TYPE_SGMII2: > > case COMPHY_TYPE_SGMII3: > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > PtrChipCfg->ComPhyBaseAddr, > > Lane, > > COMPHY_FW_FORMAT (COMPHY_SGMII_MODE, > > @@ -286,7 +286,7 @@ ComPhyCp110Init ( > > PtrComPhyMap->Speed)); > > break; > > case COMPHY_TYPE_SFI: > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > PtrChipCfg->ComPhyBaseAddr, > > Lane, > > COMPHY_FW_FORMAT (COMPHY_SFI_MODE, > > @@ -295,7 +295,7 @@ ComPhyCp110Init ( > > break; > > case COMPHY_TYPE_RXAUI0: > > case COMPHY_TYPE_RXAUI1: > > - Status =3D ComPhySmc (MV_SIP_COMPHY_POWER_ON, > > + Status =3D ComPhySmc (MV_SMC_ID_COMPHY_POWER_ON, > > PtrChipCfg->ComPhyBaseAddr, > > Lane, > > COMPHY_FW_MODE_FORMAT (COMPHY_RXAUI_MODE)); > > -- > > 2.7.4 > >