From: Marcin Wojtas <mw@semihalf.com>
To: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: "edk2-devel@lists.01.org" <edk2-devel@lists.01.org>,
"Leif Lindholm" <leif.lindholm@linaro.org>,
"Nadav Haklai" <nadavh@marvell.com>,
"Neta Zur Hershkovits" <neta@marvell.com>,
"Kostya Porotchkin" <kostap@marvell.com>,
"Hua Jing" <jinghua@marvell.com>,
"Alexander Graf" <agraf@suse.de>, "Jan Dąbroś" <jsd@semihalf.com>
Subject: Re: [platforms: PATCH 2/7] Drivers/Net/Pp2Dxe: Add SFI support
Date: Fri, 1 Sep 2017 11:39:13 +0200 [thread overview]
Message-ID: <CAPv3WKdH=fETT0BZRTvrFJm3aqLFeJ7HEnf7tN8XuJMpMvKJVg@mail.gmail.com> (raw)
In-Reply-To: <CAKv+Gu91kKdxucZ7+bXKHnm5nSQcN4Dmi11xqn8hW6TJ6LCxgw@mail.gmail.com>
Hi Ard,
2017-09-01 11:26 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
>
> On 1 September 2017 at 03:37, Marcin Wojtas <mw@semihalf.com> wrote:
> > Since now SerDes can be properly configured to support 10G
> > link, add this feature to the Armada 7k/8k network driver
> > as well. This patch extends low-level configuration routines
> > with SFI additions, which required two new fields in
> > PP2DXE_PORT structure (XpcsBase and MpcsBase).
> >
> > Contributed-under: TianoCore Contribution Agreement 1.0
> > Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>
> If you need to resend this, please fix your indentation: either
>
> Status = Function(xxx, xxx,
> xxx, xxx, etc);
>
> (two spaces indentation relative to the function name)
>
> or
>
> Status = Function (xxx,
> xxx,
> xxx,
> etc);
>
> Other than that
>
In 5.2.2.4 of https://edk2-docs.gitbooks.io/edk-ii-c-coding-standards-specification/content/5_source_files/52_spacing.html#52-spacing
there's indeed 2 spaces of indentation relative to function name, but
shouldn't correct multiline call look following:
Status = Function (
aaa,
bbb
);
?
> Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>
> > ---
> > Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c | 183 +++++++++++++++++++++++
> > Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h | 31 ++++
> > Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h | 39 ++++-
> > Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c | 2 +
> > Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h | 4 +-
> > Platform/Marvell/Include/Protocol/MvPhy.h | 3 +-
> > 6 files changed, 259 insertions(+), 3 deletions(-)
> >
> > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
> > index cdd0979..5fb7a58 100644
> > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
> > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.c
> > @@ -4116,6 +4116,21 @@ MvGop110PortInit (
> > /* MAC unreset */
> > MvGop110GmacReset (Port, UNRESET);
> > break;
> > + case MV_MODE_SFI:
> > + /* Configure PCS */
> > + MvGopXpcsModeCfg (Port, MVPP2_SFI_LANE_COUNT);
> > +
> > + MvGopMpcsModeCfg (Port);
> > +
> > + /* Configure MAC */
> > + MvGopXlgMacModeCfg (Port);
> > +
> > + /* PCS unreset */
> > + MvGopXpcsUnreset (Port);
> > +
> > + /* MAC unreset */
> > + MvGopXlgMacUnreset (Port);
> > + break;
> > default:
> > return -1;
> > }
> > @@ -4512,6 +4527,118 @@ Mvpp2SmiPhyAddrCfg (
> > return 0;
> > }
> >
> > +/* Set the internal mux's to the required PCS */
> > +EFI_STATUS
> > +MvGopXpcsModeCfg (
> > + IN PP2DXE_PORT *Port,
> > + IN INT32 NumOfLanes
> > + )
> > +{
> > + UINT8 LaneCoeff;
> > +
> > + switch (NumOfLanes) {
> > + case 1:
> > + case 2:
> > + case 4:
> > + LaneCoeff = NumOfLanes >> 1;
> > + default:
> > + return EFI_INVALID_PARAMETER;
> > + }
> > +
> > + /* Configure XG MAC mode */
> > + MmioAndThenOr32 (
> > + Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG,
> > + ~(MVPP22_XPCS_PCSMODE_MASK | MVPP22_XPCS_LANEACTIVE_MASK),
> > + LaneCoeff << MVPP22_XPCS_LANEACTIVE_OFFS
> > + );
> > +
> > + return EFI_SUCCESS;
> > +}
> > +
> > +VOID
> > +MvGopMpcsModeCfg (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + /* Configure MPCS40G COMMON CONTROL */
> > + MmioAnd32 (
> > + Port->Priv->MpcsBase + MVPP22_MPCS40G_COMMON_CONTROL,
> > + ~MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK
> > + );
> > +
> > + /* Configure MPCS CLOCK RESET */
> > + MmioAndThenOr32 (
> > + Port->Priv->MpcsBase + MVPP22_MPCS_CLOCK_RESET,
> > + ~(MVPP22_MPCS_CLK_DIVISION_RATIO_MASK | MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK),
> > + MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT | MVPP22_MPCS_MAC_CLK_RESET_MASK |
> > + MVPP22_MPCS_RX_SD_CLK_RESET_MASK | MVPP22_MPCS_TX_SD_CLK_RESET_MASK
> > + );
> > +}
> > +
> > +/* Set the internal mux's to the required MAC in the GOP */
> > +VOID
> > +MvGopXlgMacModeCfg (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + /* Configure 10G MAC mode */
> > + MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_RXFCEN_MASK);
> > +
> > + MmioAndThenOr32 (
> > + Port->XlgBase + MV_XLG_PORT_MAC_CTRL3_REG,
> > + ~MV_XLG_MAC_CTRL3_MACMODESELECT_MASK,
> > + MV_XLG_MAC_CTRL3_MACMODESELECT_10G
> > + );
> > +
> > + MmioAndThenOr32 (
> > + Port->XlgBase + MV_XLG_PORT_MAC_CTRL4_REG,
> > + ~(MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK | MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK),
> > + MV_XLG_MAC_CTRL4_FORWARD_PFC_EN_MASK | MV_XLG_MAC_CTRL4_FORWARD_802_3X_FC_EN_MASK
> > + );
> > +
> > + /* Configure frame size limit */
> > + MmioAndThenOr32 (
> > + Port->XlgBase + MV_XLG_PORT_MAC_CTRL1_REG,
> > + ~MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK,
> > + MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT
> > + );
> > +
> > + /* Mask all port's external interrupts */
> > + MvGop110XlgPortLinkEventMask (Port);
> > +
> > + /* Unmask link change interrupt - enable automatic status update */
> > + MmioOr32 (
> > + Port->XlgBase + MV_XLG_INTERRUPT_MASK_REG,
> > + MV_XLG_INTERRUPT_LINK_CHANGE_MASK | MV_XLG_SUMMARY_INTERRUPT_MASK
> > + );
> > +}
> > +
> > +/* Set PCS to exit from reset */
> > +VOID
> > +MvGopXpcsUnreset (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + MmioOr32 (Port->Priv->XpcsBase + MVPP22_XPCS_GLOBAL_CFG_0_REG, MVPP22_XPCS_PCSRESET);
> > +}
> > +
> > +/* Set the MAC to exit from reset */
> > +VOID
> > +MvGopXlgMacUnreset (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + MmioOr32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, MV_XLG_MAC_CTRL0_MACRESETN_MASK);
> > +}
> > +
> > +BOOLEAN
> > +MvGop110XlgLinkStatusGet (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + return MmioRead32 (Port->XlgBase + MV_XLG_MAC_PORT_STATUS_REG) & MV_XLG_MAC_PORT_STATUS_LINKSTATUS_MASK;
> > +}
> > +
> > BOOLEAN
> > MvGop110PortIsLinkUp (
> > IN PP2DXE_PORT *Port
> > @@ -4522,6 +4649,8 @@ MvGop110PortIsLinkUp (
> > case MV_MODE_SGMII:
> > case MV_MODE_QSGMII:
> > return MvGop110GmacLinkStatusGet (Port);
> > + case MV_MODE_SFI:
> > + return MvGop110XlgLinkStatusGet (Port);
> > case MV_MODE_XAUI:
> > case MV_MODE_RXAUI:
> > return FALSE;
> > @@ -4546,6 +4675,32 @@ MvGop110GmacLinkStatusGet (
> > return (Val & 1) ? TRUE : FALSE;
> > }
> >
> > +STATIC
> > +VOID
> > +MvGop110XlgPortEnable (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + /* Enable port and MIB counters update */
> > + MmioAndThenOr32 (
> > + Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG,
> > + ~MV_XLG_MAC_CTRL0_MIBCNTDIS_MASK,
> > + MV_XLG_MAC_CTRL0_PORTEN_MASK
> > + );
> > +}
> > +
> > +STATIC
> > +VOID
> > +MvGop110XlgPortDisable (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + /* Mask all port's external interrupts */
> > + MvGop110XlgPortLinkEventMask (Port);
> > +
> > + MmioAnd32 (Port->XlgBase + MV_XLG_PORT_MAC_CTRL0_REG, ~MV_XLG_MAC_CTRL0_PORTEN_MASK);
> > +}
> > +
> > VOID
> > MvGop110PortDisable (
> > IN PP2DXE_PORT *Port
> > @@ -4557,6 +4712,11 @@ MvGop110PortDisable (
> > case MV_MODE_QSGMII:
> > MvGop110GmacPortDisable (Port);
> > break;
> > + case MV_MODE_XAUI:
> > + case MV_MODE_RXAUI:
> > + case MV_MODE_SFI:
> > + MvGop110XlgPortDisable (Port);
> > + break;
> > default:
> > return;
> > }
> > @@ -4573,6 +4733,11 @@ MvGop110PortEnable (
> > case MV_MODE_QSGMII:
> > MvGop110GmacPortEnable (Port);
> > break;
> > + case MV_MODE_XAUI:
> > + case MV_MODE_RXAUI:
> > + case MV_MODE_SFI:
> > + MvGop110XlgPortEnable (Port);
> > + break;
> > default:
> > return;
> > }
> > @@ -4622,6 +4787,17 @@ MvGop110GmacPortLinkEventMask (
> > MvGop110GmacWrite (Port, MV_GMAC_INTERRUPT_SUM_MASK_REG, RegVal);
> > }
> >
> > +VOID
> > +MvGop110XlgPortLinkEventMask (
> > + IN PP2DXE_PORT *Port
> > + )
> > +{
> > + MmioAnd32 (
> > + Port->XlgBase + MV_XLG_EXTERNAL_INTERRUPT_MASK_REG,
> > + ~MV_XLG_EXTERNAL_INTERRUPT_LINK_CHANGE_MASK
> > + );
> > +}
> > +
> > INT32
> > MvGop110PortEventsMask (
> > IN PP2DXE_PORT *Port
> > @@ -4634,6 +4810,11 @@ MvGop110PortEventsMask (
> > case MV_MODE_QSGMII:
> > MvGop110GmacPortLinkEventMask (Port);
> > break;
> > + case MV_MODE_XAUI:
> > + case MV_MODE_RXAUI:
> > + case MV_MODE_SFI:
> > + MvGop110XlgPortLinkEventMask (Port);
> > + break;
> > default:
> > return -1;
> > }
> > @@ -4655,6 +4836,7 @@ MvGop110FlCfg (
> > break;
> > case MV_MODE_XAUI:
> > case MV_MODE_RXAUI:
> > + case MV_MODE_SFI:
> > return 0;
> > default:
> > return -1;
> > @@ -4679,6 +4861,7 @@ MvGop110SpeedDuplexSet (
> > break;
> > case MV_MODE_XAUI:
> > case MV_MODE_RXAUI:
> > + case MV_MODE_SFI:
> > break;
> > default:
> > return -1;
> > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
> > index d7d5dcb..a7011f7 100644
> > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
> > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2Lib.h
> > @@ -433,6 +433,32 @@ Mvpp2SmiPhyAddrCfg (
> > IN INT32 Addr
> > );
> >
> > +EFI_STATUS
> > +MvGopXpcsModeCfg (
> > + IN PP2DXE_PORT *Port,
> > + IN INT32 NumOfLanes
> > + );
> > +
> > +VOID
> > +MvGopMpcsModeCfg (
> > + IN PP2DXE_PORT *Port
> > + );
> > +
> > +VOID
> > +MvGopXlgMacModeCfg (
> > + IN PP2DXE_PORT *Port
> > + );
> > +
> > +VOID
> > +MvGopXpcsUnreset (
> > + IN PP2DXE_PORT *Port
> > + );
> > +
> > +VOID
> > +MvGopXlgMacUnreset (
> > + IN PP2DXE_PORT *Port
> > + );
> > +
> > BOOLEAN
> > MvGop110PortIsLinkUp (
> > IN PP2DXE_PORT *Port
> > @@ -473,6 +499,11 @@ MvGop110PortEventsMask (
> > IN PP2DXE_PORT *Port
> > );
> >
> > +VOID
> > +MvGop110XlgPortLinkEventMask (
> > + IN PP2DXE_PORT *Port
> > + );
> > +
> > INT32
> > MvGop110FlCfg (
> > IN PP2DXE_PORT *Port
> > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> > index 868be53..52509b0 100644
> > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Mvpp2LibHw.h
> > @@ -885,6 +885,30 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MVPP2_PORT_CTRL4_LEDS_NUMBER_MASK \
> > (0x0000003f << MVPP2_PORT_CTRL4_LEDS_NUMBER_OFFS)
> >
> > +/* XPCS registers */
> > +
> > +/* Global Configuration 0 */
> > +#define MVPP22_XPCS_GLOBAL_CFG_0_REG 0x0
> > +#define MVPP22_XPCS_PCSRESET BIT(0)
> > +#define MVPP22_XPCS_PCSMODE_OFFS 3
> > +#define MVPP22_XPCS_PCSMODE_MASK (0x3 << MVPP22_XPCS_PCSMODE_OFFS)
> > +#define MVPP22_XPCS_LANEACTIVE_OFFS 5
> > +#define MVPP22_XPCS_LANEACTIVE_MASK (0x3 << MVPP22_XPCS_LANEACTIVE_OFFS)
> > +
> > +/* MPCS registers */
> > +
> > +#define MVPP22_MPCS40G_COMMON_CONTROL 0x14
> > +#define MVPP22_MPCS_FORWARD_ERROR_CORRECTION_MASK BIT(10)
> > +
> > +#define MVPP22_MPCS_CLOCK_RESET 0x14c
> > +#define MVPP22_MPCS_TX_SD_CLK_RESET_MASK BIT(0)
> > +#define MVPP22_MPCS_RX_SD_CLK_RESET_MASK BIT(1)
> > +#define MVPP22_MPCS_MAC_CLK_RESET_MASK BIT(2)
> > +#define MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS 4
> > +#define MVPP22_MPCS_CLK_DIVISION_RATIO_MASK (0x7 << MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS)
> > +#define MVPP22_MPCS_CLK_DIVISION_RATIO_DEFAULT (0x1 << MVPP22_MPCS_CLK_DIVISION_RATIO_OFFS)
> > +#define MVPP22_MPCS_CLK_DIV_PHASE_SET_MASK BIT(11)
> > +
> > /* Descriptor ring Macros */
> > #define MVPP2_QUEUE_NEXT_DESC(q, index) (((index) < (q)->LastDesc) ? ((index) + 1) : 0)
> >
> > @@ -1089,6 +1113,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS 0
> > #define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_MASK \
> > (0x00001fff << MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_OFFS)
> > +#define MV_XLG_MAC_CTRL1_FRAMESIZELIMIT_DEFAULT 0x1400
> >
> > #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_OFFS 13
> > #define MV_XLG_MAC_CTRL1_MACLOOPBACKEN_MASK \
> > @@ -1167,7 +1192,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > (0x00000001 << MV_XLG_MAC_PORT_STATUS_PFC_SYNC_FIFO_FULL_OFFS)
> >
> > /* Port Fifos Thresholds Configuration */
> > -#define MV_XLG_PORT_FIFOS_THRS_CFG_REG (0x001)
> > +#define MV_XLG_PORT_FIFOS_THRS_CFG_REG (0x0010)
> > #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS 0
> > #define MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_MASK \
> > (0x0000001f << MV_XLG_MAC_PORT_FIFOS_THRS_CFG_RXFULLTHR_OFFS)
> > @@ -1193,6 +1218,8 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS 13
> > #define MV_XLG_MAC_CTRL3_MACMODESELECT_MASK \
> > (0x00000007 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
> > +#define MV_XLG_MAC_CTRL3_MACMODESELECT_10G \
> > + (0x00000001 << MV_XLG_MAC_CTRL3_MACMODESELECT_OFFS)
> >
> > /* Port Per Prio Flow Control Status */
> > #define MV_XLG_PORT_PER_PRIO_FLOW_CTRL_STATUS_REG (0x0020)
> > @@ -1382,6 +1409,10 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_MASK \
> > (0x00000001 << MV_XLG_MAC_CTRL4_MAC_MODE_DMA_1G_OFFS)
> >
> > +#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK 14
> > +#define MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK_MASK \
> > + (0x00000001 << MV_XLG_MAC_CTRL4_EN_IDLE_CHECK_FOR_LINK)
> > +
> > /* Port Mac Control5 */
> > #define MV_XLG_PORT_MAC_CTRL5_REG (0x0088)
> > #define MV_XLG_MAC_CTRL5_TXIPGLENGTH_OFFS 0
> > @@ -1542,6 +1573,9 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MV_XLG_INTERRUPT_CAUSE_REG (0x0014)
> > /* Port Interrupt Mask */
> > #define MV_XLG_INTERRUPT_MASK_REG (0x0018)
> > +#define MV_XLG_SUMMARY_INTERRUPT_OFFSET 0
> > +#define MV_XLG_SUMMARY_INTERRUPT_MASK \
> > + (0x1 << MV_XLG_SUMMARY_INTERRUPT_OFFSET)
> > #define MV_XLG_INTERRUPT_LINK_CHANGE_OFFS 1
> > #define MV_XLG_INTERRUPT_LINK_CHANGE_MASK \
> > (0x1 << MV_XLG_INTERRUPT_LINK_CHANGE_OFFS)
> > @@ -1926,6 +1960,9 @@ typedef struct {
> > #define MVPP2_B_HDR_INFO_LAST_MASK BIT(12)
> > #define MVPP2_B_HDR_INFO_IS_LAST(info) ((info & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
> >
> > +/* SerDes */
> > +#define MVPP2_SFI_LANE_COUNT 1
> > +
> > /* Net Complex */
> > enum MvNetcTopology {
> > MV_NETC_GE_MAC0_RXAUI_L23 = BIT(0),
> > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> > index d53f3b7..bdaf1a0 100644
> > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.c
> > @@ -1171,6 +1171,8 @@ Pp2DxeInitialise (
> >
> > Mvpp2Shared->Base = PcdGet64 (PcdPp2SharedAddress);
> > Mvpp2Shared->Rfu1Base = Mvpp2Shared->Base + MVPP22_RFU1_OFFSET;
> > + Mvpp2Shared->XpcsBase = Mvpp2Shared->Base + MVPP22_XPCS_OFFSET;
> > + Mvpp2Shared->MpcsBase = Mvpp2Shared->Base + MVPP22_MPCS_OFFSET;
> > Mvpp2Shared->SmiBase = Mvpp2Shared->Base + MVPP22_SMI_OFFSET;
> > Mvpp2Shared->Tclk = PcdGet32 (PcdPp2ClockFrequency);
> >
> > diff --git a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> > index a179638..1e03a69 100644
> > --- a/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> > +++ b/Platform/Marvell/Drivers/Net/Pp2Dxe/Pp2Dxe.h
> > @@ -116,6 +116,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> > #define MV_MODE_RGMII PHY_CONNECTION_RGMII
> > #define MV_MODE_XAUI PHY_CONNECTION_XAUI
> > #define MV_MODE_RXAUI PHY_CONNECTION_RXAUI
> > +#define MV_MODE_SFI PHY_CONNECTION_SFI
> > #define MV_MODE_QSGMII 100
> > #define PP2DXE_MAX_PHY 2
> >
> > @@ -263,9 +264,10 @@ typedef struct Pp2DxePort PP2DXE_PORT;
> > typedef struct {
> > /* Shared registers' base addresses */
> > UINT64 Base;
> > + UINT64 MpcsBase;
> > UINT64 Rfu1Base;
> > UINT64 SmiBase;
> > - VOID *LmsBase;
> > + UINT64 XpcsBase;
> >
> > /* List of pointers to Port structures */
> > PP2DXE_PORT **PortList;
> > diff --git a/Platform/Marvell/Include/Protocol/MvPhy.h b/Platform/Marvell/Include/Protocol/MvPhy.h
> > index 43a9e0b..a91759a 100644
> > --- a/Platform/Marvell/Include/Protocol/MvPhy.h
> > +++ b/Platform/Marvell/Include/Protocol/MvPhy.h
> > @@ -47,7 +47,8 @@ typedef enum {
> > PHY_CONNECTION_SGMII,
> > PHY_CONNECTION_RTBI,
> > PHY_CONNECTION_XAUI,
> > - PHY_CONNECTION_RXAUI
> > + PHY_CONNECTION_RXAUI,
> > + PHY_CONNECTION_SFI
> > } PHY_CONNECTION;
> >
> > typedef enum {
> > --
> > 1.8.3.1
> >
next prev parent reply other threads:[~2017-09-01 9:36 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-09-01 2:37 [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Marcin Wojtas
2017-09-01 2:37 ` [platforms: PATCH 1/7] Drivers/Net/Pp2Dxe: Move registers' description to macros Marcin Wojtas
2017-09-01 9:22 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 2/7] Drivers/Net/Pp2Dxe: Add SFI support Marcin Wojtas
2017-09-01 9:26 ` Ard Biesheuvel
2017-09-01 9:39 ` Marcin Wojtas [this message]
2017-09-01 9:40 ` Ard Biesheuvel
2017-09-01 9:49 ` Marcin Wojtas
2017-09-01 9:51 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 3/7] Drivers/Net/Pp2Dxe: Support multiple ethernet ports simultaneously Marcin Wojtas
2017-09-01 9:30 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 4/7] Drivers/Net/Pp2Dxe: Increase amount of ingress resources Marcin Wojtas
2017-09-01 9:30 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 5/7] Platforms/Marvell: Update ethernet ports types on A70x0 DB Marcin Wojtas
2017-09-01 9:31 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 6/7] Drivers/Net/Pp2Dxe: Move devices description to MvHwDescLib Marcin Wojtas
2017-09-01 9:33 ` Ard Biesheuvel
2017-09-01 2:37 ` [platforms: PATCH 7/7] Drivers/Net/Pp2Dxe: Enable using ports from different controllers Marcin Wojtas
2017-09-01 9:34 ` Ard Biesheuvel
2017-09-01 9:27 ` [platforms: PATCH 0/7] Armada 70x0/80x0 network improvements Ard Biesheuvel
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