From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=nDFJN2TC; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.160.195, mailfrom: mw@semihalf.com) Received: from mail-qt1-f195.google.com (mail-qt1-f195.google.com [209.85.160.195]) by groups.io with SMTP; Fri, 16 Aug 2019 14:05:03 -0700 Received: by mail-qt1-f195.google.com with SMTP id y26so7592683qto.4 for ; Fri, 16 Aug 2019 14:05:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=aO0nQawd0mJL2bX5jfxrkOtK25TRRtVBttyTS1u5TZg=; b=nDFJN2TCO0ZolV4XnxknJzLKDU3D4l02Ko1fZcQR2/uf6Oi/Ixe7iszKh0xSbrovC6 qVfkQ7epw2Pdj28Xf9IDnSxSiMuo0hiLDVtubkrr1XLY62GI455xXByoHzFp33MAfeDH O3GQZWlrFK/ZLkey2MkvBeXexqSIuX7wzqIxc7W1/Vek+391W0qfmKgLrUZAJqy/RvnK e5LWygK5+dtRz6EMWy67eBlxyVML3dS7EvnMQWBDVjF9gBAG1Ecwl6lUTQ51T6Fk/XOt nhudYSp0HzJF/gYxF23XSE8MN+yKB8rg/FCCLAZCUBnoiRaz3QFaWm8Qadxgf+9537+C OhFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=aO0nQawd0mJL2bX5jfxrkOtK25TRRtVBttyTS1u5TZg=; b=GSj7UM05vqRj876ISA1CR+4Z+JnFlJFF3Jojca63XOSfZGXhDIQfr+dYc6r+rLSfaU E8+vSwvym+SD/UtV61FH97yI/WP8aT4uMvHj0hUOL5QyoeeZ0o1RlOzc8kQvQt7yAUHw VXbTDJt9fXcDqmQtEtH5FXqhLV17T/eoqOB0F1z+U7daWAjapOWZ+wKnsMLylLbM/Dl+ s4JP12Km6RZ9HWyoXYO4ceyATfD3nu6V6fPiG/+9WePEaN6XKO8mkY2sw+BfuigqZrCu 8Igc6HDvnEhpXL4mDKD47yNJ5yuCXMORKEvqHZTyWgVnHvgYpkxBBHKsqRanrpPgNzls gbNg== X-Gm-Message-State: APjAAAXuIVNpNMztWSLOEMk7JavUrsPDJHHCPy9fmqa2XU1bSa0zcbll Yubrr3to/YxL9uK7FJAG819oXjfoRm4TEBBNIN2Y9A== X-Google-Smtp-Source: APXvYqygimO44g0F6PuETnazcDO/3lggk8HZ2YPRHsftEcSy0TfNvlmXeRLCaZFPL1GrbS+KeLRQ+VVd6/LKpJvk7ew= X-Received: by 2002:ac8:4808:: with SMTP id g8mr11017976qtq.0.1565989502307; Fri, 16 Aug 2019 14:05:02 -0700 (PDT) MIME-Version: 1.0 References: <1565837654-13258-1-git-send-email-mw@semihalf.com> <1565837654-13258-7-git-send-email-mw@semihalf.com> <20190816173615.GY29255@bivouac.eciton.net> In-Reply-To: <20190816173615.GY29255@bivouac.eciton.net> From: "Marcin Wojtas" Date: Fri, 16 Aug 2019 23:04:53 +0200 Message-ID: Subject: Re: [edk2-devel] [edk2-platforms: PATCH v2 06/10] Marvell/Library: MppLib: Allow to configure more Xenon PHYs To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, pt., 16 sie 2019 o 19:36 Leif Lindholm napisa= =C5=82(a): > > On Thu, Aug 15, 2019 at 04:54:10AM +0200, Marcin Wojtas wrote: > > Hitherto MppLib code assumed that there could be only two > > Xenon SdMmc controllers' PHYs. Remove this limitation, so that to > > support CN913x SoCs, which may have up to 4 of such interfaces. > > Should this be merged with the preceding patch? > Yes it could - I will squash both patches. Thanks, Marcin > / > Leif > > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Library/MppLib/MppLib.c | 4 +--- > > 1 file changed, 1 insertion(+), 3 deletions(-) > > > > diff --git a/Silicon/Marvell/Library/MppLib/MppLib.c b/Silicon/Marvell= /Library/MppLib/MppLib.c > > index 40d9077..f20668d 100644 > > --- a/Silicon/Marvell/Library/MppLib/MppLib.c > > +++ b/Silicon/Marvell/Library/MppLib/MppLib.c > > @@ -139,11 +139,9 @@ SetSdMmcPhyMpp ( > > case 0: > > Offset =3D SD_MMC_PHY_AP_MPP_OFFSET; > > break; > > - case 1: > > + default: > > Offset =3D SD_MMC_PHY_CP0_MPP_OFFSET; > > break; > > - default: > > - return; > > } > > > > /* > > -- > > 2.7.4 > > > > > >=20 > >