From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f172.google.com (mail-qk1-f172.google.com [209.85.222.172]) by mx.groups.io with SMTP id smtpd.web09.465.1627923612575632297 for ; Mon, 02 Aug 2021 10:00:12 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=LSBVRMfM; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.172, mailfrom: mw@semihalf.com) Received: by mail-qk1-f172.google.com with SMTP id z24so17220766qkz.7 for ; Mon, 02 Aug 2021 10:00:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=5BfR+gBuS3O6PZExtjArB1RmJIM/3rbHCxB3nHKH7bw=; b=LSBVRMfMwmOSu/i2D1YUr5QluQuyXYfE8KozPVUlpyCQCuAuyoCXkPRNowa+sLRp7S tqiB8ueisgTGsJxQJhbqxh4PXo0GRBjbmztCH9CxkJhWiulLCKiWLgKieH+h4aGf/3Wr /PQGCGNQx/R4rcEptdy2OMWu8+AeFnfm9bUPsASk0dBruViSDPjRESHSAakrZsjohzqW oQ48UAK7SiMuYr4hB5JC274CWZisjPIUZjdDWqDZxQsxeOvYZTnS/lP/8FE6SkNoepiK m34+qnvoBiMfRuYoeU4pH5bdKjbpwgy/DFJkN/w6KGT5ozTvvyR1Zax5ztzUkSPxsDrP gxEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=5BfR+gBuS3O6PZExtjArB1RmJIM/3rbHCxB3nHKH7bw=; b=Hx+5BCwJjrS46taWra2FUnhRGykH8tUwEUZQ5hABXTAXsOC1uzHvVsTa3xwK1L6ZyH l8Lvo6TQKLrqFTESP72uOEa4qONozIuR0HZdXlVNDECZ6vCrxOfEV92XelZe02QmEhCa uk232nrKzI32I4cAVKrLiBtcc1Bpkj9VGKcWN02lsBdFts30nriMzEQnb8ae2bKxs3Hb 2e7/fqUPrNdbTO6b40YwMi/sSdxPg0sMj3xffyS9XmiJPMGRo6RwHDF6bgdHFl/VjDXt YLQfk4FWgGTmW4mStSqbQuzcp+s259CN2qMGX40zZxT7JxwZebpvsqM+Z2RGRHWqrX9e SJ1g== X-Gm-Message-State: AOAM531gQfaie4qfd3//C841IPa2T8VroRK3fJ/G0DDUrlz2T6Qkuplm HPiByOedFDUZvn8uDBJbM/S+mIBnTTVx3KE7ONhe6A== X-Google-Smtp-Source: ABdhPJzLA4WX80jkfo4nx0idePkrJAFe2JX2jeqyHa2NK7jvyJuybynGDoRO9hUTToJQl7KkYLuhLHGRHAcp7T3p4xg= X-Received: by 2002:a05:620a:21d0:: with SMTP id h16mr16504980qka.385.1627923611423; Mon, 02 Aug 2021 10:00:11 -0700 (PDT) MIME-Version: 1.0 References: <20210802050051.2831716-1-mw@semihalf.com> <20210802050051.2831716-4-mw@semihalf.com> In-Reply-To: From: "Marcin Wojtas" Date: Mon, 2 Aug 2021 19:00:00 +0200 Message-ID: Subject: Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation To: Ard Biesheuvel Cc: edk2-devel-groups-io , Leif Lindholm , Ard Biesheuvel , Grzegorz Jaszczyk , Grzegorz Bernacki , upstream@semihalf.com, Samer El-Haj-Mahmoud , Jon Nettleton Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Ard, pon., 2 sie 2021 o 10:43 Ard Biesheuvel napisa=C5=82(a): > > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote: > > > > On CN913x-based platforms it is possible to have up to 9 PCIE > > root complexes. In such case it may be necessary to configure > > more configuration spaces with smaller bus count, so that > > to fit the memory layout constraints. For that purpose remove > > forcing ECAM base to be divisible by SIZE_256MB. > > > > There is one subtlety here that we need to take into account: IIUC, > PCIe requires that the ECAM start address of bus N equals N MB modulo > 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, the > bus range has to start at bus 128. > > I think OSes are usually quite lax about this, but it is something to > double check regardless, even for existing platforms > I tested a wide range of OSs (various Linux distributions, Win10 PE, FreeBSD, OpenBSD and of course EDK2) and with 7 ECAMs, of which 6 are squeezed within 256MB memory chunk together with their mmio32 and no issue was observed. Moreover, if you recall, contrary to the EDK2, where the full bus number is used, in ACPI we expose a single 1MB space with the ECAM base address aligned to 0x8000. Do you wish to change the assertion in EDK2 instead of removing? Thanks, Marcin > > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostB= ridgeLibConstructor.c | 1 - > > 1 file changed, 1 deletion(-) > > > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridge= Lib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/Arma= da7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > > index 067e57a2dc..87e57aeae3 100644 > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/Pci= HostBridgeLibConstructor.c > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/Pci= HostBridgeLibConstructor.c > > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor ( > > PcieController =3D &(BoardPcieDescription->PcieControllers[Index])= ; > > > > ASSERT (PcieController->PcieBusMin =3D=3D 0); > > - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB =3D=3D 0); > > > > if (PcieController->HaveResetGpio =3D=3D TRUE) { > > /* Reset PCIE slot */ > > -- > > 2.29.0 > >