From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=OvENb5v/; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.196, mailfrom: mw@semihalf.com) Received: from mail-qk1-f196.google.com (mail-qk1-f196.google.com [209.85.222.196]) by groups.io with SMTP; Fri, 24 May 2019 14:22:14 -0700 Received: by mail-qk1-f196.google.com with SMTP id t64so9367254qkh.1 for ; Fri, 24 May 2019 14:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=lmJmIuKTxijGu4Q3MLAc3MLdph0PeREZPAR50Jab1og=; b=OvENb5v/S4C/B/dgDW1JP3Mgt9lZl+l3Ct2eWXTYka9AdGKDXRKn9mhU8Qpmb2pMkn jPV/3jeDSyYKS8a59dLtgStkE3BpbAnd0oj6eC70X5XLId+jVLA46lnk1EvZqTERb8sE JAROYf9F6KdPJdfN4GIIODSgJ2MKcxB9X6z9d+LIgXfQ1i/ty7c1ee6ZXRz9BRoKc3gk /ncdSYNrLJP64Nh7P6AIA555MIodsSPoj/JPPM16LufIPheflagxwBls9yjalLjjiD5k 6IhaKheP/6A7vkx45pkXsNNVzRJsvizShtQ/mJsVavgAet0S1YHMutAAoEQc1A7GgljP p8CA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=lmJmIuKTxijGu4Q3MLAc3MLdph0PeREZPAR50Jab1og=; b=HaFkG6LECRW94pS1fBbMlPYhkCG0/5UwXYRXspVX6w2wLA7Ep3bM3iWmGetswySAiH 286stlRaFtyWeDKUTFmrfAGWS/XYATFzVITU/F3b+wwLWElLAVfJIgfQ9BUvJHnNU4SB 9Tmoab6lvMAUJk6cScVpoL+/VvVuZYyRl1YnQhWhBweqb8WWf1Tp80FOEodGlM4hQEH6 gtAtvdZmQWYaXIgP47WifglNGOS5kKxv9ET6WgnJgnzZ3R7mCqwzcQQW1+KVpC9zm5Az J2YQqfP2B67pEhJJQ7NNXss6QJdMnRt79vhlCwrxa0CWoDGvsZ+9TPChjkmYUYTAVbop o/QA== X-Gm-Message-State: APjAAAWi2pus3uQdLc8bgSc9mVE8c+koWx8bVVl1PzcdHejGzpiMT0NO cIn9s23KHNoDqo6C2alDzqp7V43CYU8zPYFvhaIglA== X-Google-Smtp-Source: APXvYqxjb+svlhzoMxNtzrU35wIMETeZRIGUqmzBeZ/E+Cmm0sfY7DjfKE3VtKLIY7VJwATUpx3freVusXz66DnEDwk= X-Received: by 2002:aed:3686:: with SMTP id f6mr70234168qtb.30.1558732933108; Fri, 24 May 2019 14:22:13 -0700 (PDT) MIME-Version: 1.0 References: <1558713551-25363-1-git-send-email-mw@semihalf.com> In-Reply-To: From: "Marcin Wojtas" Date: Fri, 24 May 2019 23:22:03 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v3 00/14] Armada7k8k PCIE support To: Ard Biesheuvel Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Ard, pt., 24 maj 2019 o 18:57 Ard Biesheuvel napisa= =C5=82(a): > > On Fri, 24 May 2019 at 17:59, Marcin Wojtas wrote: > > > > Hi, > > > > The v3 of Armada PCIE support brings one change - the custom > > PciExpressLib was replaced with PciSegmentLib, that will > > allow to extend the support with more slots available > > on some platforms. > > > > The patches are available in the github: > > https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits= /pcie-upstream-r20190524 > > > > I'm looking forward to your comments or remarks. > > > > Best regards, > > Marcin > > > > For the series > Reviewed-by: Ard Biesheuvel > > Pushed as 21e36d78ddae..50a9caf82b81 > > Thanks a lot! I'm happy we finally have this stuff merged. > > Me too! Thanks for the review and the last hint about the PciSegmentLib. Only Smbios resend left for now. Best regards, Marcin > > > > Changelog: > > v2->v3: > > * 6/14 > > - Replace PciExpressLib with PciSegmentLib > > > > * 8/14 > > - Adjust to new dependecies > > > > v1->v2: > > *All > > - s/PcieBaseAddress/PcieDbiAdress/ > > > > *2/14 > > - fix alignment in comment > > > > * 3/14 > > - add CONST** to library callback > > > > * 4/14 > > - add missing reset GPIO to McBin description > > > > * 5/15 > > - add CONST** to protocol callback > > > > * 6/14 > > - cleanup all casting in file > > - use MAX_UINTx macros > > - add Linaro copyright > > - use MmioWrite8 instead of volatile in PciExpressReadBuffer > > - correct commient in IgnoreBusDeviceFunction () > > - fix typo in commit message > > > > * 7/10 > > - correct line endings > > - use temporary variable for memory description in PciHostBridgeReso= urceConflict > > - use MAX_UINTx macros > > - add comments around stalls and MemoryFence in GPIO reset > > - keep the reset active for 150ms > > - assign translation values instead of asserting > > > > *8/14 > > - assign gArmTokenSpaceGuid.PcdPciIoTranslation value in .dsc > > > > * 9-11/14 > > - correct line endings > > - remove unused methods > > - extend commit messages with 32k shift description > > > > > > Marcin Wojtas (14): > > Marvell/Library: MvGpioLib: Extend GPIO pin description > > Marvell/Library: ArmadaSoCDescLib: Add PCIE information > > Marvell/Library: ArmadaBoardDescLib: Add PCIE information > > Marvell/Armada7k8k: Extend board description libraries with PCIE > > Marvell/Armada7k8k: MvBoardDesc: Extend protocol with PCIE support > > Marvell/Armada7k8k: Add PciSegmentLib implementation > > Marvell/Armada7k8k: Implement PciHostBridgeLib > > Marvell/Armada7k8k: Enable PCIE support > > Marvell/Armada80x0McBin: Enable ACPI PCIE support > > Marvell/Armada80x0Db: Enable ACPI PCIE support > > Marvell/Armada70x0Db: Enable ACPI PCIE support > > Marvell/Armada80x0McBin: DeviceTree: Use pci-host-generic driver > > Marvell/Armada7k8k: Remove duplication in .dsc files > > Marvell/Armada7k8: Add 'acpiview' shell command to build > > > > Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc = | 15 + > > Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc = | 4 +- > > Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc = | 4 +- > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc = | 4 +- > > Silicon/Marvell/Armada7k8k/Armada7k8k.fdf = | 5 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db.inf = | 1 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db.inf = | 1 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf = | 1 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostB= ridgeLib.inf | 52 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentL= ib.inf | 33 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Pcie.h = | 26 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Pcie.h = | 26 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Pcie.h = | 26 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostB= ridgeLibConstructor.h | 95 ++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.h | 6 + > > Silicon/Marvell/Include/Library/ArmadaBoardDescLib.h = | 46 + > > Silicon/Marvell/Include/Library/ArmadaSoCDescLib.h = | 20 + > > Silicon/Marvell/Include/Library/MvGpioLib.h = | 1 + > > Silicon/Marvell/Include/Protocol/BoardDesc.h = | 22 + > > Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoa= rdDescLib.c | 48 + > > Platform/Marvell/Armada70x0Db/NonDiscoverableInitLib/NonDiscoverableIn= itLib.c | 4 + > > Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoa= rdDescLib.c | 48 + > > Platform/Marvell/Armada80x0Db/NonDiscoverableInitLib/NonDiscoverableIn= itLib.c | 6 + > > Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80= x0McBinBoardDescLib.c | 54 + > > Platform/SolidRun/Armada80x0McBin/NonDiscoverableInitLib/NonDiscoverab= leInitLib.c | 1 + > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostB= ridgeLib.c | 265 ++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostB= ridgeLibConstructor.c | 345 +++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentL= ib.c | 1390 ++++++++++++++++++++ > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kSoCDescLib/Armada7k8kSoCD= escLib.c | 44 + > > Silicon/Marvell/Drivers/BoardDesc/MvBoardDescDxe.c = | 86 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl = | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Mcfg.aslc = | 47 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl = | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Mcfg.aslc = | 47 + > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl = | 108 ++ > > Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Mcfg.aslc = | 47 + > > Silicon/Marvell/Armada7k8k/DeviceTree/armada-8040-mcbin.dts = | 3 + > > 37 files changed, 3138 insertions(+), 9 deletions(-) > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHos= tBridgeLib/PciHostBridgeLib.inf > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSeg= mentLib/PciSegmentLib.inf > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/= Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/= Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McB= in/Pcie.h > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHos= tBridgeLib/PciHostBridgeLibConstructor.h > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHos= tBridgeLib/PciHostBridgeLib.c > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHos= tBridgeLib/PciHostBridgeLibConstructor.c > > create mode 100644 Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSeg= mentLib/PciSegmentLib.c > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/= Mcfg.aslc > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/= Mcfg.aslc > > create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McB= in/Mcfg.aslc > > > > -- > > 2.7.4 > >