From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id E52A2203525F5 for ; Thu, 26 Oct 2017 06:55:30 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id p186so5528581ioe.12 for ; Thu, 26 Oct 2017 06:59:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=2xXmA5hkKdJrbe+86VgIycRx0vGYBIHDlHCfiFarS5E=; b=vifoHo1HJ/Jt5yM8HO/mxYaw/OACdxw6JGVUU2EOK9R5HiCuhXSXOCPr6Vk8JAG+dc o4RjNRg/mfZ5DxbIhosWK/G5ki7IwCJEMGg+ukvyWJaGcEZoKmkp5S9sJvOZiL5LahjZ hup7YaqcusMlLHb+LQ3LNPLBxNIlvZcEr3Yyvz5//QiqLKh0kbLHDOh3eVXotqiA74TC YVceRAfRk7S8XkHfwuu7XWbEa+dlLWARFUmuczptLQb40UpB6Gsb22v7fzyFWzgUFx1Z EZR7XRQi/qt1k3778SxA+NQL569NKos2tqO+4WV+aleNs2klLfSjvfzpX0VOcGWrYVtu pitQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=2xXmA5hkKdJrbe+86VgIycRx0vGYBIHDlHCfiFarS5E=; b=eJ2y8pRV+r0cIcZlvQ1X35ytefSr5xMlmINNCbViJ8ygyeS2liT38saAOhED/P+0aV YNSRi7Ew2KhJJJ0wpf4Sp+QJK3R4BxHkw5Ycm4lV0mpA0wkCSO+zu/ni0bBgh7rCPKxU rWzt/xbtL+V8crrUiKnXxLrvLFwTA2oVAKPkzE5r04IhPG8SDsqQhRqagn246hCEjFS6 I4yD1ciEHpH2bBLoGzDm2bVXyatSvAJQSLTKuD92ss/z8W9Kc/o/OQTzG7LzqH5iXSnP egRuQlIajMsY5QlcKsLWQznWNefhx4vIlyslWeIwITpDWLx0hnPwjG6sf+s5kgil1LQk xADA== X-Gm-Message-State: AMCzsaWbtEOYVZuL0u291jg2LE+/y/lV4Fsc4g1RIo8ebtX+GKM2rm3c Ed9V8vFpGJ57LU+2hSbjZ08UikiemxLmWz9lxZfl8A== X-Google-Smtp-Source: ABhQp+TkAVKd4CBY0xBWgaeojjsoRKbyTMLyIYaTmNCZgPP7GggfugKIb0CUWdO0A3rlawCe9PUEAgfmDoWKRB8Y0PE= X-Received: by 10.107.68.10 with SMTP id r10mr30732962ioa.202.1509026356559; Thu, 26 Oct 2017 06:59:16 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.167.208 with HTTP; Thu, 26 Oct 2017 06:59:15 -0700 (PDT) In-Reply-To: References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> From: Marcin Wojtas Date: Thu, 26 Oct 2017 15:59:15 +0200 Message-ID: To: Ard Biesheuvel Cc: Leif Lindholm , edk2-devel-01 , Nadav Haklai , Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , semihalf-dabros-jan Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:55:31 -0000 Content-Type: text/plain; charset="UTF-8" 2017-10-26 15:55 GMT+02:00 Ard Biesheuvel : > On 26 October 2017 at 14:54, Marcin Wojtas wrote: >> 2017-10-26 15:46 GMT+02:00 Leif Lindholm : >>> On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >>>> Incorrectly the clock divisor was calculated relatively >>>> to 255MHz instead of actual 400MHz. >>> >>> This describes the specific symptom, not the problem with the existing >>> code. >>> >>>> Fix this. >>>> >>>> Contributed-under: TianoCore Contribution Agreement 1.1 >>>> Signed-off-by: Marcin Wojtas >>>> --- >>>> Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- >>>> 1 file changed, 2 insertions(+), 2 deletions(-) >>>> >>>> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>>> index ccbf355..0b9328b 100644 >>>> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>>> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >>>> @@ -16,6 +16,7 @@ >>>> **/ >>>> >>>> #include "SdMmcPciHcDxe.h" >>>> +#include "XenonSdhci.h" >>>> >>>> /** >>>> Dump the content of SD/MMC host controller's Capability Register. >>>> @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( >>>> // >>>> // Calculate a divisor for SD clock frequency >>>> // >>>> - ASSERT (Capability.BaseClkFreq != 0); >>>> >>>> - BaseClkFreq = Capability.BaseClkFreq; >>> >>> Why is Capability.BaseClkFreq the wrong frequency to use? >>> >> >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. >> An alternative would be change this generic type to UINT16 and update >> field properly during initialization - do you prefer that? >> > > Isn't that value read from device registers? This field in generic Capability1 register is only 8-bit wide, hence the 255MHz limitation. Xenon controller however is fed with 400MHz and it clearly cannot be obtained from there. Marcin