From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x234.google.com (mail-io0-x234.google.com [IPv6:2607:f8b0:4001:c06::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 19F8A81EB1 for ; Thu, 24 Nov 2016 01:08:00 -0800 (PST) Received: by mail-io0-x234.google.com with SMTP id j65so69409404iof.0 for ; Thu, 24 Nov 2016 01:07:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=4QgJkYg3+SmFWtK8gncY7QtMe6MTCCGw1yGizDW7vjA=; b=gDu6I7Ke3YTygUjVFKC3ZDR51ZT5efDafFp2sokhFk8mq+L5rFHXmr5HpAlVvoiPNx hNakNe+oMJrUQ/lGjdMLaocif3bv+FgyUpvZo60UZouNeQobTNpXCmY+bNf3Yy8G0zI8 4/FJCt9NZh8w0FUmJ05qZqarUHFqw1vrIaiwfDe+M2D+I6f7daCgesPxkmoC9hIeD0sd AlzUuxTPrpcsEbsF9B3E+6KnUJ+ZDWUERICZ9rLV6nlLycwpXXe/anrtn3ocKtQRcOaz oV1H9M25L440MUGvgQ9dte6B3MSKA8DhyYhmg1xbBwj1TO+yp//50ioElAGmSdRJ33OL t6DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=4QgJkYg3+SmFWtK8gncY7QtMe6MTCCGw1yGizDW7vjA=; b=lkYgrTA88a7Pbrpkg+sbqP8cQ40fHy2vJ+103RCScrZigF8huqlynfHr+4uwhbU54L Geqn9VrKBFr9OGhoYP3SsvCIFeF8gHyvFkKetZzOH4bB9eVsr6ezlIRAOS1Ka3s/LlrW nogTFeeJ8wfELXfGYQGPU3m7gL6tIIJG2dqdTX69NwxM6d7rGMX3UxOMetwsIfVF4chE f9x0GtoyEyoktGOHxI/GOMfEiACogKKjKabZAnID5gk8GWUJsVoNxYEW6hjG7PNrS9O/ rDASOEU69hGemMaPC1/GCGBw4FmNK7Pd4VQixsAoCICOAjIxn8Nxj0JlpNmEpf69lyh+ 5LhQ== X-Gm-Message-State: AKaTC00TAIR6sHz5u9PHjjdCMWCrWkENaRdx9gBvLBLEoN7rfaNL3eVebwH9E4ukYnt2Vr+QI9JQSBoGVg9TMw== X-Received: by 10.107.58.195 with SMTP id h186mr1097498ioa.117.1479978479301; Thu, 24 Nov 2016 01:07:59 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.25.140 with HTTP; Thu, 24 Nov 2016 01:07:58 -0800 (PST) In-Reply-To: <7F1BAD85ADEA444D97065A60D2E97EE566E53C0C@SHSMSX101.ccr.corp.intel.com> References: <1479974073-29154-1-git-send-email-mw@semihalf.com> <7F1BAD85ADEA444D97065A60D2E97EE566E53C0C@SHSMSX101.ccr.corp.intel.com> From: Marcin Wojtas Date: Thu, 24 Nov 2016 10:07:58 +0100 Message-ID: To: "Tian, Feng" Cc: "edk2-devel@lists.01.org" , "ard.biesheuvel@linaro.org" , "leif.lindholm@linaro.org" , "Gao, Liming" , "Kinney, Michael D" Subject: Re: [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 09:08:00 -0000 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi, Yes, it would be great. Thanks, Marcin 2016-11-24 9:35 GMT+01:00 Tian, Feng : > Reviewed-by: Feng Tian > > Do you want me to push it into EDKII trunk? > > Thanks > Feng > > -----Original Message----- > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf Of Ma= rcin Wojtas > Sent: Thursday, November 24, 2016 3:55 PM > To: edk2-devel@lists.01.org > Cc: Tian, Feng ; ard.biesheuvel@linaro.org; leif.lin= dholm@linaro.org; Gao, Liming ; Kinney, Michael D > Subject: [edk2] [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE b= it is always set in Ahci > > According to AHCI Spec 1.3 GHC.AE bit description: > "The implementation of this bit is dependent upon the value of the CAP.SA= M bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall have a = reset value of '0'. If CAP.SAM is '1', then AE shall be read-only and shall= have a reset value of '1'." > > Being in AhciMode, for proper operation it is required, that GHC.AE bit i= s always set, before any other AHCI registers are written to. Current AhciM= ode implementation, both in AhciReset() and AhciModeInitialization() functi= ons, set GHC.AE bit only depending on 'CAP.SAM =3D=3D 0' condition, assumin= g (according to the AHCI spec), that otherwise it has to be set anyway. It = may however happen, that even if 'CAP.SAM =3D=3D 1', GHC.AE requires updati= ng by software. > > This patch enables in AhciMode setting GHC.AE in case its initial value i= s '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC families.= The change is transparent to all other platforms. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: Marcin Wojtas > Signed-off-by: Jan Dabros > > --- > Changelog: > v1 -> v2 > > * Instead of doing it uncoditionally, enable setting GHC.AE bit only in > case its initial value is '0' > > --- > MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 21 ++++++++++--------= --- > 1 file changed, 10 insertions(+), 11 deletions(-) > > diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModule= Pkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > index 533d201..4d01c1d 100644 > --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c > @@ -1451,17 +1451,13 @@ AhciReset ( > { > UINT64 Delay; > UINT32 Value; > - UINT32 Capability; > > // > - // Collect AHCI controller information > - // > - Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); > - > - // > - // Enable AE before accessing any AHCI registers if Supports AHCI Mode= Only is not set > + // Make sure that GHC.AE bit is set before accessing any AHCI register= s. > // > - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { > + Value =3D AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); > + > + if ((Value & EFI_AHCI_GHC_ENABLE) =3D=3D 0) { > AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); > } > > @@ -2252,6 +2248,7 @@ AhciModeInitialization ( > EFI_ATA_COLLECTIVE_MODE *SupportedModes; > EFI_ATA_TRANSFER_MODE TransferMode; > UINT32 PhyDetectDelay; > + UINT32 Value; > > if (Instance =3D=3D NULL) { > return EFI_INVALID_PARAMETER; > @@ -2270,11 +2267,13 @@ AhciModeInitialization ( > // Collect AHCI controller information > // > Capability =3D AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); > - > + > // > - // Enable AE before accessing any AHCI registers if Supports AHCI Mode= Only is not set > + // Make sure that GHC.AE bit is set before accessing any AHCI register= s. > // > - if ((Capability & EFI_AHCI_CAP_SAM) =3D=3D 0) { > + Value =3D AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); > + > + if ((Value & EFI_AHCI_GHC_ENABLE) =3D=3D 0) { > AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); > } > > -- > 1.8.3.1 > > _______________________________________________ > edk2-devel mailing list > edk2-devel@lists.01.org > https://lists.01.org/mailman/listinfo/edk2-devel