From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::d44; helo=mail-io1-xd44.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd44.google.com (mail-io1-xd44.google.com [IPv6:2607:f8b0:4864:20::d44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id C4FAE2116371C for ; Mon, 8 Oct 2018 07:52:18 -0700 (PDT) Received: by mail-io1-xd44.google.com with SMTP id x26-v6so16056312iog.11 for ; Mon, 08 Oct 2018 07:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=8oIcBAx0YoEojRQYf74aa0cF1P0ww/jMsvzcFwIqdw4=; b=HCLm8byxA8mg3y0Y7yIIJH0JKN8y96qKnTbx1mnHFQFkRXKN0Xo75aEn0oNoXhjeQs x8s7rJVTJz27Qy9L5NziuunGZ/qF/j1/SXs5fp6r4gN3p1O35u4DkqNtStFFCw1epeaf NP6iLvV/gFo/PHz+Gg84BQG9fuhmycFoBXGbw2XJddIZG3gqmOVYw6ZStu6D/s3vL3Rj YKgNJr1hTyPD+Cgm9G0d8r9eP6BezUAfGN1H/nT48qESP4E1sIgNDvMvnPG6dE/lItrr 5K+oNtDUdehP9wVQygpUG+pet+/lTGs9Gbja9tO9nDegETmI3s/Lna4p33WcMtGrYW5o 1r6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=8oIcBAx0YoEojRQYf74aa0cF1P0ww/jMsvzcFwIqdw4=; b=bS4PxDQQMDd3Lej4p/moMoMnhvM6mlkZ2LQQdmDJnHydYJxXhCOrjOaTtox/bwupdG MNHZEv3vigBf1Ao6iwrvZz+/Pm30h0R9p/qgHO8ODTl6+l1VASZBMlSZ0rZcHXCWYU6q z7kepkB2azBLlwvNMExIypxzUcFO+nUoHG83rkR4w5YWvG0wPKLWjvLX0Uspy+UtArXt r1IYQuQ7o8Yh2Lacikn7IN6n3/yQIjV2OG0tEndbqH/OIE+6douoD02S180POfZP+uXf ewrrR0Rav7Oinu+pXLNsCFj0Bx2yE6dYVfDJ6OoUA2EAISZcr2qaegNUkmJy1LP4YOjS m/Ag== X-Gm-Message-State: ABuFfogfm3V8uudMw98nAO/gqogzWVpkO54XNhMSH1apTo1EZ6NLrFY6 G7oj4KPz4vjg04tsg5pYCPGYksIn50UA+PcX1IPNfvbzT5g= X-Google-Smtp-Source: ACcGV63fm8yyDhyEHuIjSRaBozY7I+cTESG1Pu54i17TdxA9pH00VeAaTqSJVdgnCvhKXt75m5LbJHl+tyTRA6WhbRU= X-Received: by 2002:a6b:7e0c:: with SMTP id i12-v6mr16441367iom.221.1539010337815; Mon, 08 Oct 2018 07:52:17 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Mon, 8 Oct 2018 16:52:06 +0200 Message-ID: To: Ard Biesheuvel Cc: "Zeng, Star" , eric.dong@intel.com, "Ni, Ruiyu" , edk2-devel-01 , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , hao.a.wu@intel.com, nadavh@marvell.com, "jsd@semihalf.com" , Tomasz Michalec Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Oct 2018 14:52:19 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pon., 8 pa=C5=BA 2018 o 15:43 Ard Biesheuvel na= pisa=C5=82(a): > > On 8 October 2018 at 15:37, Marcin Wojtas wrote: > > pon., 8 pa=C5=BA 2018 o 15:27 Ard Biesheuvel napisa=C5=82(a): > >> > >> On 8 October 2018 at 15:17, Marcin Wojtas wrote: > >> > pon., 8 pa=C5=BA 2018 o 15:07 Ard Biesheuvel napisa=C5=82(a): > >> >> > >> >> On 8 October 2018 at 14:59, Marcin Wojtas wrote: > >> >> > Hi Ard, > >> >> > > >> >> > pon., 8 pa=C5=BA 2018 o 14:41 Ard Biesheuvel napisa=C5=82(a): > >> >> >> > >> >> >> (add MdeModulePkg maintainers) > >> >> >> > >> >> >> On 5 October 2018 at 15:25, Marcin Wojtas wrot= e: > >> >> >> > From: Tomasz Michalec > >> >> >> > > >> >> >> > Some SD Host Controlers use different values in Host Control 2= Register > >> >> >> > to select UHS Mode. This patch adds a new UhsSignaling type ro= utine to > >> >> >> > the NotifyPhase of the SdMmcOverride protocol. > >> >> >> > > >> >> >> > UHS signaling configuration is moved to a common, default rout= ine > >> >> >> > (SdMmcHcUhsSignaling), which is called when SdMmcOverride does= not > >> >> >> > cover this functionality. > >> >> >> > > >> >> >> > Contributed-under: TianoCore Contribution Agreement 1.1 > >> >> >> > Signed-off-by: Marcin Wojtas > >> >> >> > --- > >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 50 ++++++= + > >> >> >> > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 2 + > >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 153 ++++++= ++++++-------- > >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 37 +++-- > >> >> >> > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 69 ++++++= +++ > >> >> >> > 5 files changed, 243 insertions(+), 68 deletions(-) > >> >> >> > > >> >> >> > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h = b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > >> >> >> > index e389d52..a03160d 100644 > >> >> >> > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > >> >> >> > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > >> >> >> > @@ -63,6 +63,39 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF AN= Y KIND, EITHER EXPRESS OR IMPLIED. > >> >> >> > #define SD_MMC_HC_CTRL_VER 0xFE > >> >> >> > > >> >> >> > // > >> >> >> > +// SD Host Controler bits to HOST_CTRL2 register > >> >> >> > +// > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007 > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000 > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001 > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002 > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003 > >> >> >> > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004 > >> >> >> > +#define SD_MMC_HC_CTRL_MMC_DDR52 0x0004 > >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR50 0x0002 > >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR25 0x0001 > >> >> >> > +#define SD_MMC_HC_CTRL_MMC_SDR12 0x0000 > >> >> >> > +#define SD_MMC_HC_CTRL_HS200 0x0003 > >> >> >> > +#define SD_MMC_HC_CTRL_HS400 0x0005 > >> >> >> > + > > > > In case we move enums to SdMmcOverride.h, would it be desired, to move > > there register fields values as well? Or should I rather use Xenon > > macros for all of above locally? > > > > No, I think the macros should be kept locally. > > >> >> >> > +// > >> >> >> > +// Timing modes for uhs > >> >> >> > +// > >> >> >> > +typedef enum { > >> >> >> > + SdMmcUhsSdr12, > >> >> >> > + SdMmcUhsSdr25, > >> >> >> > + SdMmcUhsSdr50, > >> >> >> > + SdMmcUhsSdr104, > >> >> >> > + SdMmcUhsDdr50, > >> >> >> > + SdMmcMmcDdr52, > >> >> >> > + SdMmcMmcSdr50, > >> >> >> > + SdMmcMmcSdr25, > >> >> >> > + SdMmcMmcSdr12, > >> >> >> > + SdMmcMmcHs200, > >> >> >> > + SdMmcMmcHs400, > >> >> >> > +} SD_MMC_UHS_TIMING; > >> >> >> > + > >> >> >> > >> >> >> Here, we end up with two sets of symbolic constants for the same > >> >> >> thing, and I suppose this enum will be duplicated in your > >> >> >> SdMmcOverride implementation? > >> >> >> > >> >> > > >> >> > Why duplicated? Macros are for generic UHS_MODE_SEL field values = for > >> >> > SD and MMC in HostControl2Register. > >> >> > > >> >> > SD_MMC_UHS_TIMING is just a timing mode indicator, it can be used= not > >> >> > only in UhsSignaling routine (actually the next patch, with > >> >> > SwitchClockFreqPost, use it...). > >> >> > > >> >> > In my SdMmcOverride implementation this enum is not duplicated, > >> >> > because this file (SdMmcPciHci.h) is included via > >> >> > Protocol/SdMmcOverride.h. > >> >> > > >> >> > >> >> Ah ok. Please don't expose internal headers of the SD/MMC driver vi= a > >> >> Protocol/SdMmcOverride.h > >> >> > >> > > >> > OK. > >> > > >> >> I think it should be fine to add the enum definition to > >> >> Protocol/SdMmcOverride.h instead. > >> >> > >> > > >> > OK. > >> > > >> >> But wouldn't it be much easier to have a hook for setting > >> >> HostControl2Register that decodes the value and modifies it accordi= ng > >> >> to what the platform requires? > >> >> > >> > > >> > Can you please explain, how it will be different from UhsSignaling i= n > >> > current shape (read required timing value and update UHS_MODE_SEL > >> > field)? > >> > > >> > >> Well, you decode the value, and if, e.g., the SD_MMC_HC_CTRL_HS200 > >> bits are set, you substitute them with the appropriate xenon values. > > > > Because values can be same for SD and MMC (e.g. UHS_104 and HS200), > > from the controller driver perspective, how would I know, which mode > > is requested? > > > > Good point. > > >> > >> Also, how important is it to drive the SD/MMC at its max rated speed > >> at boot time? On Synquacer, I just disable HS200 in the capability > >> struct so I can forget about all this stuff > > > > Some customers want it - a real life scenario from one of them: > > applications, Linux binaries and rootfs stores in the MMC. Each boot a > > couple of hundreds of MB to be loaded. Thanks to HS200 we have huge > > time saving. > > > > Do you mean in the initrd? Because otherwise, Linux will use its own > driver and select its own mode. No, I mean loading >300MB images from eMMC to memory in the DXE phase, before booting anything. > > And btw, does the spec permit using different HC2 values for HS200 / HS40= 0 ? According to SD Host Controller Specification v4.20, UHS_MODE_SEL values 0x5 and 0x6 are "reserved". According to Linux code, HS400 value is treated as "non-standard" and HS200 should be same as for SDR104 (0x3). Nothing is written about permiting different values, but given Linux 'sdhci_set_uhs_signaling' and whole bunch of other quirks used under drivers/mmc overriding standard behavior is very common. Please let know your desired way of handling custom UhsSignaling. Best regards, MArcin