From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c06::242; helo=mail-io0-x242.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io0-x242.google.com (mail-io0-x242.google.com [IPv6:2607:f8b0:4001:c06::242]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 3C89420352609 for ; Thu, 26 Oct 2017 06:50:57 -0700 (PDT) Received: by mail-io0-x242.google.com with SMTP id p186so5496887ioe.12 for ; Thu, 26 Oct 2017 06:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=qySlD3jN2NTtoqPe/hEEVEdFgCgKEtgxhiXNL9DPFA4=; b=Bx7idS8lYEP5FFg0zSJ1hOH4aEoeMrvqwoh7RkzfJArkLv6bXk+EPxBDhpwg6Rp723 RB/euDhN/LRjsDox4uTkPbVaiTfti4+jDuPa9z8fnWKlzidxJ4UxNq02hQCPkMca+XZC 2pDMrnKIwM0Vn30FEy4++oSePJgv/ff6E7Enz6a4s7cy/aD6FU1md4uCIu+dnojojKRY bveiBjZG9u6v4lwRTQfuMmXqtadOYTP3GAcrMZStIgPcWo8BjJjh54/sC6RXDvQLq8E3 CQbGtanqjIE+rTG07uRhH3TuYblrHuAREK34qxDUhOb3IN6sd5hpCvJqS1xSj6VypUQg PzVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=qySlD3jN2NTtoqPe/hEEVEdFgCgKEtgxhiXNL9DPFA4=; b=V08ox9k5k0kMifIVIHaKcNiRf8+crUzjXJodeRVHKwud981YmEO4y3XZ0umasNYqCU e5XzTexJjasDO4EN7wo8HUirMd8K48ppKCRiUvaI7XBdsSlOfaD9tIKEpxL/i4k2GIOT E3TULCWvomAPkBHNU1bawcQjHu1opo/vi9Zwr4TyVuz7fUcCbojKbhV8+uzX5xTnvvgL VN9ygQPYYnc92mIoz0w2USPOI2Ty53AdjU0WRHqFLIG4kMjdsqHKQs5o/DVtB8p9UwyE hkxZ5OMkgv4zlthajBWukvZgUJzW961VL2LaAr7+aHkkzgy9ccK5WMlNyliQ2QotKWZm q7CQ== X-Gm-Message-State: AMCzsaWbHQZZdiyomxjCtxHRiD9pMQWxt3EWqIVNb9yKq3olMCj7Nh4m LTVWU1tsmO7psuujHmTIhjLZ+LLUVZqWHPYoPP+p0kQW X-Google-Smtp-Source: ABhQp+RaD/m0dEAAXGPMaS6gjnjSC6wcaTu7b0ld7j+WsyVHwQbGtGhtlkP7sDAp+yXiMIMs09DDAzLttcIunaVxck4= X-Received: by 10.107.10.98 with SMTP id u95mr31734706ioi.30.1509026082644; Thu, 26 Oct 2017 06:54:42 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.167.208 with HTTP; Thu, 26 Oct 2017 06:54:41 -0700 (PDT) In-Reply-To: <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> From: Marcin Wojtas Date: Thu, 26 Oct 2017 15:54:41 +0200 Message-ID: To: Leif Lindholm Cc: edk2-devel-01 , Ard Biesheuvel , nadavh@marvell.com, Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , semihalf-dabros-jan Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 13:50:57 -0000 Content-Type: text/plain; charset="UTF-8" 2017-10-26 15:46 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >> Incorrectly the clock divisor was calculated relatively >> to 255MHz instead of actual 400MHz. > > This describes the specific symptom, not the problem with the existing > code. > >> Fix this. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Marcin Wojtas >> --- >> Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> index ccbf355..0b9328b 100644 >> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> @@ -16,6 +16,7 @@ >> **/ >> >> #include "SdMmcPciHcDxe.h" >> +#include "XenonSdhci.h" >> >> /** >> Dump the content of SD/MMC host controller's Capability Register. >> @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( >> // >> // Calculate a divisor for SD clock frequency >> // >> - ASSERT (Capability.BaseClkFreq != 0); >> >> - BaseClkFreq = Capability.BaseClkFreq; > > Why is Capability.BaseClkFreq the wrong frequency to use? > The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. An alternative would be change this generic type to UINT16 and update field properly during initialization - do you prefer that? Marcin