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a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=DgoF+an9en04CAxjDKcfZ6v1tTXXBq3wgtutleRJegg=; b=hYC6gVIu3WKelLRq6tncdBakxjjWZemiP42aHjKkYL6UD087bQPf6Gva7zwzJgMUsw uI3b62MuwnKDTBBwicV7Yqw0Q2K1D5ynwKK0VdXBrd4p4PIljFb3cGwdL5lReyvLsW7e 0vwr7r9ox2qZCZa/EO4kY8hDLrW/LEOtmWcMj3SWrPqZQ4SlKDVYY3w3y7lpQ2oYRmQA yXhQ+XUOc3paDRnl9nILvusXlIpkT0DYm0cJ7/Oedtj7NIP/LYyMwePXgS4tD49HtGJI m3fM/EyGov5G+FEzaNc4DpZYiWO/dhkEKr/O6ajtR9AHfrZG8QtaMr6BhvyRZHqEkbwo FL2A== X-Gm-Message-State: AGRZ1gIiLDB2sCBsqZ5XdEk/mmUKJH9dbxdS1nYNmKrGG9nq6evElif3 6ACGW46VoVsAoWyVhT8WVTfrNLmYAJqosq0YWKeOeg== X-Google-Smtp-Source: AJdET5cXedJr9/DKAbzge/6QqV2LSreBnP4ieogk8FAoRCFiBJdrh6v1DDgaIx+w1WHrncgh1oYCmW4PLC5MLsUd5PM= X-Received: by 2002:a6b:7f44:: with SMTP id m4-v6mr551855ioq.221.1541675770915; Thu, 08 Nov 2018 03:16:10 -0800 (PST) MIME-Version: 1.0 References: <1541642255-15602-1-git-send-email-mw@semihalf.com> <1541642255-15602-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Thu, 8 Nov 2018 12:15:59 +0100 Message-ID: To: Ard Biesheuvel Cc: edk2-devel-01 , Leif Lindholm , hao.a.wu@intel.com, "Kinney, Michael D" , "Gao, Liming" , nadavh@marvell.com, "jsd@semihalf.com" , Tomasz Michalec , Grzegorz Jaszczyk Subject: Re: [PATCH v3 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 X-List-Received-Date: Thu, 08 Nov 2018 11:16:12 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Ard, I'm glad you're back :) czw., 8 lis 2018 o 12:06 Ard Biesheuvel napisa= =C5=82(a): > > On 8 November 2018 at 02:57, Marcin Wojtas wrote: > > From: Tomasz Michalec > > > > Some SD Host Controllers use different values in Host Control 2 Registe= r > > to select UHS Mode. This patch adds a new UhsSignaling type routine to > > the NotifyPhase of the SdMmcOverride protocol. > > > > UHS signaling configuration is moved to a common, default routine > > (SdMmcHcUhsSignaling). After it is executed, the protocol producer > > can override the values if needed.. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 32 +++++ > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 17 +++ > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 136 +++++++++++++--= ----- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 31 ++++- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 66 ++++++++++ > > 5 files changed, 225 insertions(+), 57 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h b/MdeModu= lePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > > index 7e3f588..1a11d51 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h > > @@ -63,6 +63,21 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, E= ITHER EXPRESS OR IMPLIED. > > #define SD_MMC_HC_CTRL_VER 0xFE > > > > // > > +// SD Host Controller bits to HOST_CTRL2 register > > +// > > +#define SD_MMC_HC_CTRL_UHS_MASK 0x0007 > > +#define SD_MMC_HC_CTRL_UHS_SDR12 0x0000 > > +#define SD_MMC_HC_CTRL_UHS_SDR25 0x0001 > > +#define SD_MMC_HC_CTRL_UHS_SDR50 0x0002 > > +#define SD_MMC_HC_CTRL_UHS_SDR104 0x0003 > > +#define SD_MMC_HC_CTRL_UHS_DDR50 0x0004 > > +#define SD_MMC_HC_CTRL_MMC_LEGACY 0x0000 > > +#define SD_MMC_HC_CTRL_MMC_HS_SDR 0x0001 > > +#define SD_MMC_HC_CTRL_MMC_HS_DDR 0x0004 > > +#define SD_MMC_HC_CTRL_MMC_HS200 0x0003 > > +#define SD_MMC_HC_CTRL_MMC_HS400 0x0005 > > + > > +// > > // The transfer modes supported by SD Host Controller > > // Simplified Spec 3.0 Table 1-2 > > // > > @@ -518,4 +533,21 @@ SdMmcHcInitTimeoutCtrl ( > > IN UINT8 Slot > > ); > > > > +/** > > + Set SD Host Controller control 2 registry according to selected spee= d. > > + > > + @param[in] PciIo The PCI IO protocol instance. > > + @param[in] Slot The slot number of the SD card to send the= command to. > > + @param[in] Timing The timing to select. > > + > > + @retval EFI_SUCCESS The timing is set successfully. > > + @retval Others The timing isn't set successfully. > > +**/ > > +EFI_STATUS > > +SdMmcHcUhsSignaling ( > > + IN EFI_PCI_IO_PROTOCOL *PciIo, > > + IN UINT8 Slot, > > + IN SD_MMC_BUS_MODE Timing > > + ); > > + > > #endif > > diff --git a/MdeModulePkg/Include/Protocol/SdMmcOverride.h b/MdeModuleP= kg/Include/Protocol/SdMmcOverride.h > > index 8a7669e..f948bef 100644 > > --- a/MdeModulePkg/Include/Protocol/SdMmcOverride.h > > +++ b/MdeModulePkg/Include/Protocol/SdMmcOverride.h > > @@ -26,11 +26,28 @@ > > > > typedef struct _EDKII_SD_MMC_OVERRIDE EDKII_SD_MMC_OVERRIDE; > > > > +// > > +// Bus timing modes > > +// > > +typedef enum { > > + SdMmcUhsSdr12, > > + SdMmcUhsSdr25, > > + SdMmcUhsSdr50, > > + SdMmcUhsSdr104, > > + SdMmcUhsDdr50, > > + SdMmcMmcLegacy, > > + SdMmcMmcHsSdr, > > + SdMmcMmcHsDdr, > > + SdMmcMmcHs200, > > + SdMmcMmcHs400, > > +} SD_MMC_BUS_MODE; > > + > > typedef enum { > > EdkiiSdMmcResetPre, > > EdkiiSdMmcResetPost, > > EdkiiSdMmcInitHostPre, > > EdkiiSdMmcInitHostPost, > > + EdkiiSdMmcUhsSignaling, > > } EDKII_SD_MMC_PHASE_TYPE; > > > > /** > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c b/MdeModul= ePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > index c5fd214..473df8d 100755 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > @@ -740,10 +740,13 @@ EmmcSwitchToHighSpeed ( > > IN UINT8 BusWidth > > ) > > { > > - EFI_STATUS Status; > > - UINT8 HsTiming; > > - UINT8 HostCtrl1; > > - UINT8 HostCtrl2; > > + EFI_STATUS Status; > > + UINT8 HsTiming; > > + UINT8 HostCtrl1; > > + SD_MMC_BUS_MODE Timing; > > + SD_MMC_HC_PRIVATE_DATA *Private; > > + > > + Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); > > > > Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, Bu= sWidth); > > if (EFI_ERROR (Status)) { > > @@ -758,29 +761,37 @@ EmmcSwitchToHighSpeed ( > > return Status; > > } > > > > - // > > - // Clean UHS Mode Select field of Host Control 2 reigster before upd= ate > > - // > > - HostCtrl2 =3D (UINT8)~0x7; > > - Status =3D SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof= (HostCtrl2), &HostCtrl2); > > - if (EFI_ERROR (Status)) { > > - return Status; > > - } > > - // > > - // Set UHS Mode Select field of Host Control 2 reigster to SDR12/25/= 50 > > - // > > if (IsDdr) { > > - HostCtrl2 =3D BIT2; > > + Timing =3D SdMmcMmcHsDdr; > > } else if (ClockFreq =3D=3D 52) { > > - HostCtrl2 =3D BIT0; > > + Timing =3D SdMmcMmcHsSdr; > > } else { > > - HostCtrl2 =3D 0; > > + Timing =3D SdMmcMmcLegacy; > > } > > - Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); > > + > > + Status =3D SdMmcHcUhsSignaling (PciIo, Slot, Timing); > > if (EFI_ERROR (Status)) { > > return Status; > > } > > > > + if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > > + Status =3D mOverride->NotifyPhase ( > > + Private->ControllerHandle, > > + Slot, > > + EdkiiSdMmcUhsSignaling, > > + &Timing > > + ); > > + if (EFI_ERROR (Status)) { > > + DEBUG (( > > + DEBUG_ERROR, > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n", > > + __FUNCTION__, > > + Status > > + )); > > + return Status; > > + } > > + } > > + > > Can we move the override handling into SdMmcHcUhsSignaling()? That > way, we no longer have to duplicate it 4 times. Sure! I should've come up on this on my own... Thanks, Marcin > > > HsTiming =3D 1; > > Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming= , ClockFreq); > > > > @@ -814,10 +825,13 @@ EmmcSwitchToHS200 ( > > IN UINT8 BusWidth > > ) > > { > > - EFI_STATUS Status; > > - UINT8 HsTiming; > > - UINT8 HostCtrl2; > > - UINT16 ClockCtrl; > > + EFI_STATUS Status; > > + UINT8 HsTiming; > > + UINT16 ClockCtrl; > > + SD_MMC_BUS_MODE Timing; > > + SD_MMC_HC_PRIVATE_DATA *Private; > > + > > + Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); > > > > if ((BusWidth !=3D 4) && (BusWidth !=3D 8)) { > > return EFI_INVALID_PARAMETER; > > @@ -837,22 +851,32 @@ EmmcSwitchToHS200 ( > > if (EFI_ERROR (Status)) { > > return Status; > > } > > - // > > - // Clean UHS Mode Select field of Host Control 2 reigster before upd= ate > > - // > > - HostCtrl2 =3D (UINT8)~0x7; > > - Status =3D SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof= (HostCtrl2), &HostCtrl2); > > + > > + Timing =3D SdMmcMmcHs200; > > + > > + Status =3D SdMmcHcUhsSignaling (PciIo, Slot, Timing); > > if (EFI_ERROR (Status)) { > > return Status; > > } > > - // > > - // Set UHS Mode Select field of Host Control 2 reigster to SDR104 > > - // > > - HostCtrl2 =3D BIT0 | BIT1; > > - Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); > > - if (EFI_ERROR (Status)) { > > - return Status; > > + > > + if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > > + Status =3D mOverride->NotifyPhase ( > > + Private->ControllerHandle, > > + Slot, > > + EdkiiSdMmcUhsSignaling, > > + &Timing > > + ); > > + if (EFI_ERROR (Status)) { > > + DEBUG (( > > + DEBUG_ERROR, > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n", > > + __FUNCTION__, > > + Status > > + )); > > + return Status; > > + } > > } > > + > > // > > // Wait Internal Clock Stable in the Clock Control register to be 1 = before set SD Clock Enable bit > > // > > @@ -910,9 +934,12 @@ EmmcSwitchToHS400 ( > > IN UINT32 ClockFreq > > ) > > { > > - EFI_STATUS Status; > > - UINT8 HsTiming; > > - UINT8 HostCtrl2; > > + EFI_STATUS Status; > > + UINT8 HsTiming; > > + SD_MMC_BUS_MODE Timing; > > + SD_MMC_HC_PRIVATE_DATA *Private; > > + > > + Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); > > > > Status =3D EmmcSwitchToHS200 (PciIo, PassThru, Slot, Rca, ClockFreq,= 8); > > if (EFI_ERROR (Status)) { > > @@ -933,21 +960,30 @@ EmmcSwitchToHS400 ( > > if (EFI_ERROR (Status)) { > > return Status; > > } > > - // > > - // Clean UHS Mode Select field of Host Control 2 reigster before upd= ate > > - // > > - HostCtrl2 =3D (UINT8)~0x7; > > - Status =3D SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof= (HostCtrl2), &HostCtrl2); > > + > > + Timing =3D SdMmcMmcHs400; > > + > > + Status =3D SdMmcHcUhsSignaling (PciIo, Slot, Timing); > > if (EFI_ERROR (Status)) { > > return Status; > > } > > - // > > - // Set UHS Mode Select field of Host Control 2 reigster to HS400 > > - // > > - HostCtrl2 =3D BIT0 | BIT2; > > - Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); > > - if (EFI_ERROR (Status)) { > > - return Status; > > + > > + if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > > + Status =3D mOverride->NotifyPhase ( > > + Private->ControllerHandle, > > + Slot, > > + EdkiiSdMmcUhsSignaling, > > + &Timing > > + ); > > + if (EFI_ERROR (Status)) { > > + DEBUG (( > > + DEBUG_ERROR, > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n", > > + __FUNCTION__, > > + Status > > + )); > > + return Status; > > + } > > } > > > > HsTiming =3D 3; > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c b/MdeModuleP= kg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > > index 6ee9ed7..850ad26 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c > > @@ -784,8 +784,8 @@ SdCardSetBusMode ( > > UINT8 BusWidth; > > UINT8 AccessMode; > > UINT8 HostCtrl1; > > - UINT8 HostCtrl2; > > UINT8 SwitchResp[64]; > > + SD_MMC_BUS_MODE Timing; > > SD_MMC_HC_PRIVATE_DATA *Private; > > > > Private =3D SD_MMC_HC_PRIVATE_FROM_THIS (PassThru); > > @@ -817,18 +817,23 @@ SdCardSetBusMode ( > > if (S18A && (Capability->Sdr104 !=3D 0) && ((SwitchResp[13] & BIT3) = !=3D 0)) { > > ClockFreq =3D 208; > > AccessMode =3D 3; > > + Timing =3D SdMmcUhsSdr104; > > } else if (S18A && (Capability->Sdr50 !=3D 0) && ((SwitchResp[13] & = BIT2) !=3D 0)) { > > ClockFreq =3D 100; > > AccessMode =3D 2; > > + Timing =3D SdMmcUhsSdr50; > > } else if (S18A && (Capability->Ddr50 !=3D 0) && ((SwitchResp[13] & = BIT4) !=3D 0)) { > > ClockFreq =3D 50; > > AccessMode =3D 4; > > + Timing =3D SdMmcUhsDdr50; > > } else if ((SwitchResp[13] & BIT1) !=3D 0) { > > ClockFreq =3D 50; > > AccessMode =3D 1; > > + Timing =3D SdMmcUhsSdr25; > > } else { > > ClockFreq =3D 25; > > AccessMode =3D 0; > > + Timing =3D SdMmcUhsSdr12; > > } > > > > Status =3D SdCardSwitch (PassThru, Slot, AccessMode, 0xF, 0xF, 0xF, = TRUE, SwitchResp); > > @@ -854,15 +859,27 @@ SdCardSetBusMode ( > > } > > } > > > > - HostCtrl2 =3D (UINT8)~0x7; > > - Status =3D SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof= (HostCtrl2), &HostCtrl2); > > + Status =3D SdMmcHcUhsSignaling (PciIo, Slot, Timing); > > if (EFI_ERROR (Status)) { > > return Status; > > } > > - HostCtrl2 =3D AccessMode; > > - Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); > > - if (EFI_ERROR (Status)) { > > - return Status; > > + > > + if (mOverride !=3D NULL && mOverride->NotifyPhase !=3D NULL) { > > + Status =3D mOverride->NotifyPhase ( > > + Private->ControllerHandle, > > + Slot, > > + EdkiiSdMmcUhsSignaling, > > + &Timing > > + ); > > + if (EFI_ERROR (Status)) { > > + DEBUG (( > > + DEBUG_ERROR, > > + "%a: SD/MMC uhs signaling notifier callback failed - %r\n", > > + __FUNCTION__, > > + Status > > + )); > > + return Status; > > + } > > } > > > > Status =3D SdMmcHcClockSupply (PciIo, Slot, ClockFreq * 1000, *Capab= ility); > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c b/MdeModu= lePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > index 923c55b..85aa625 100644 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c > > @@ -1138,6 +1138,72 @@ SdMmcHcInitHost ( > > } > > > > /** > > + Set SD Host Controler control 2 registry according to selected speed= . > > + > > + @param[in] PciIo The PCI IO protocol instance. > > + @param[in] Slot The slot number of the SD card to send the= command to. > > + @param[in] Timing The timing to select. > > + > > + @retval EFI_SUCCESS The timing is set successfully. > > + @retval Others The timing isn't set successfully. > > +**/ > > +EFI_STATUS > > +SdMmcHcUhsSignaling ( > > + IN EFI_PCI_IO_PROTOCOL *PciIo, > > + IN UINT8 Slot, > > + IN SD_MMC_BUS_MODE Timing > > + ) > > +{ > > + EFI_STATUS Status; > > + UINT8 HostCtrl2; > > + > > + HostCtrl2 =3D (UINT8)~SD_MMC_HC_CTRL_UHS_MASK; > > + Status =3D SdMmcHcAndMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof= (HostCtrl2), &HostCtrl2); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + > > + switch (Timing) { > > + case SdMmcUhsSdr12: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_UHS_SDR12; > > + break; > > + case SdMmcUhsSdr25: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_UHS_SDR25; > > + break; > > + case SdMmcUhsSdr50: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_UHS_SDR50; > > + break; > > + case SdMmcUhsSdr104: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_UHS_SDR104; > > + break; > > + case SdMmcUhsDdr50: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_UHS_DDR50; > > + break; > > + case SdMmcMmcLegacy: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_MMC_LEGACY; > > + break; > > + case SdMmcMmcHsSdr: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_MMC_HS_SDR; > > + break; > > + case SdMmcMmcHsDdr: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_MMC_HS_DDR; > > + break; > > + case SdMmcMmcHs200: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_MMC_HS200; > > + break; > > + case SdMmcMmcHs400: > > + HostCtrl2 =3D SD_MMC_HC_CTRL_MMC_HS400; > > + break; > > + default: > > + HostCtrl2 =3D 0; > > + break; > > + } > > + Status =3D SdMmcHcOrMmio (PciIo, Slot, SD_MMC_HC_HOST_CTRL2, sizeof = (HostCtrl2), &HostCtrl2); > > + > > + return Status; > > +} > > + > > +/** > > Turn on/off LED. > > > > @param[in] PciIo The PCI IO protocol instance. > > -- > > 2.7.4 > >