From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::d2e; helo=mail-io1-xd2e.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd2e.google.com (mail-io1-xd2e.google.com [IPv6:2607:f8b0:4864:20::d2e]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 280212112B1F9 for ; Mon, 17 Sep 2018 15:44:10 -0700 (PDT) Received: by mail-io1-xd2e.google.com with SMTP id w11-v6so12940977iob.2 for ; Mon, 17 Sep 2018 15:44:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=9F/rXqi6X37wX1hb44uSPJurGomH+Hfndn1AeStyRuw=; b=e+IhfEb45564rB1xiK3UMVpJqdjgL8IZOizdllVKYhz3+COMw37ZVyQhSRQ4N1doK9 xwFGHmfMXACtu/aSU0xe4Ce8ELtkYYMvlmckaXSPBuXFA6S7smvULNIu3Exd3OUkNcP2 yhPqpA0KV0uIkDKRCQrDlw2hvc/BjPxM8hFHYoZEMqrc8GHxkQc8qKBDbFbyff+9EWOv 3E/wSI3ZXTUMahSe8vyviJIgM+xgWzz057OzFj+sE5j2Z2lVxbIRxkUQIHup5ehtARq6 taoZtkqo/smNlZCW5C2BGGFElfYjo+CqmxFCzi/G0LKiyjoeQfRttdcVNG+MpNC8gtVV u4yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=9F/rXqi6X37wX1hb44uSPJurGomH+Hfndn1AeStyRuw=; b=kfpJMRNfFcOasvh6DMemobQe21f3nUanMHmazEeF9bzPy+YZxiO3/T9b3UKT9Ctvjw qx8dBHrf5Su9sDb1qjsZpS+cGsEHumDgIhK62SYUPqlH5DlzDIvoH47e6M1iavdLfL/Z DNvRp7xFTcdusqPOxZTTTNeWfYQWCjxtcYbM9QYRNzKaQfv7vus2LS+hIbTq0MYCXtOU VpRslq6oDml1O9k3ybrZ4yBOcm9rEG8lFJwdQbFeGPSjx68a/U238c8uWclXDraAnty5 MMlpvqVZ74gEw8EdTHldF8HOiTgi7uPqSng+mpc8RiBi0gbZQ+QznOPwyWfXjIflSxF6 jcfQ== X-Gm-Message-State: APzg51AfGBmqeJTCwA1ZSzXA5GaFYXyyAqtPlPG7ctO/Dm62I/9s+8em zGVkFjaLvu0bplWZuQX1hzesuFvb4lq3Wc3CIAVilQ== X-Google-Smtp-Source: ANB0VdaV5XF/0ryo7FoSZrCyYjEVMr09HcXQ2HtTufEqsnwqHAgQ8Q73LUIGncv9Rj1jQmkoH3TKi55CyE6xROx22wM= X-Received: by 2002:a6b:b846:: with SMTP id i67-v6mr22547893iof.248.1537224249187; Mon, 17 Sep 2018 15:44:09 -0700 (PDT) MIME-Version: 1.0 References: <1537050346-16445-1-git-send-email-mw@semihalf.com> <1537050346-16445-2-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Tue, 18 Sep 2018 00:43:57 +0200 Message-ID: To: hao.a.wu@intel.com Cc: edk2-devel-01 , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , Ard Biesheuvel , nadavh@marvell.com, "jsd@semihalf.com" , Tomasz Michalec Subject: Re: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock and bus width sequence X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 17 Sep 2018 22:44:10 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Hao, pon., 17 wrz 2018 o 09:18 Wu, Hao A napisa=C5=82(a): > > > -----Original Message----- > > From: Marcin Wojtas [mailto:mw@semihalf.com] > > Sent: Sunday, September 16, 2018 6:26 AM > > To: edk2-devel@lists.01.org > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linaro.or= g; Wu, > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com; mw@semihalf.com; > > jsd@semihalf.com; tm@semihalf.com > > Subject: [PATCH v3 1/3] MdeModulePkg/SdMmcPciHcDxe: Adjust eMMC clock > > and bus width sequence > > > > According to JESD84-B50-1 chapter A.6 (documentation about eMMC4.5 > > standard) step "Changing the data bus width" (A.6.3) should be > > executed after step "Switching to high-speed mode" (A.6.2). > > Hi, > > My understanding to the spec is that the spec seems do not impose a > sequence for 'Switching to high-speed mode' and 'Changing the data bus > width'. > > My find is that both operation (A.6.2 & A.6.3 of JESD84-B50-1 ) requires: > > * Do these steps after the bus is initialized according to A.6.1, Bus > * initialization. > > Also, for HS200 mode selection, the flow chart in Section 6.6.4 shows the > bus width set before bus mode switch. So I think the current code is > taking this as a reference when switching the 'High Speed' mode. > > I tried the eMMC device on my side, the current code implementation and > codes after applying your patch both work. So do you met with issues with > certain device with this sequence? If not, I prefer to keep the current > logic. > I re-checked on my boards with unchanged logic - all 3 can work in High Speed. Patch is pretty old, I can't recall exact circumstances. I'll drop it in v4. Best regards, Marcin > Best Regards, > Hao Wu > > > > > This patch fixes the bus-width/clock-setting sequence > > in EmmcSwitchToHighSpeed (). > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Signed-off-by: Marcin Wojtas > > --- > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 9 +++++---- > > 1 file changed, 5 insertions(+), 4 deletions(-) > > > > diff --git a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > index c5fd214..12935ef 100755 > > --- a/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > +++ b/MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c > > @@ -745,10 +745,6 @@ EmmcSwitchToHighSpeed ( > > UINT8 HostCtrl1; > > UINT8 HostCtrl2; > > > > - Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, Bu= sWidth); > > - if (EFI_ERROR (Status)) { > > - return Status; > > - } > > // > > // Set to Hight Speed timing > > // > > @@ -783,6 +779,11 @@ EmmcSwitchToHighSpeed ( > > > > HsTiming =3D 1; > > Status =3D EmmcSwitchClockFreq (PciIo, PassThru, Slot, Rca, HsTiming= , > > ClockFreq); > > + if (EFI_ERROR (Status)) { > > + return Status; > > + } > > + > > + Status =3D EmmcSwitchBusWidth (PciIo, PassThru, Slot, Rca, IsDdr, Bu= sWidth); > > > > return Status; > > } > > -- > > 2.7.4 >