From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=ReBn0HpY; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.160.195, mailfrom: mw@semihalf.com) Received: from mail-qt1-f195.google.com (mail-qt1-f195.google.com [209.85.160.195]) by groups.io with SMTP; Wed, 26 Jun 2019 02:59:03 -0700 Received: by mail-qt1-f195.google.com with SMTP id m29so1705246qtu.1 for ; Wed, 26 Jun 2019 02:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=17QuqRLaHI9PERM0pqGotBi258tHVkZl0R28fGq71Cg=; b=ReBn0HpYSzvuiWY0ihx5brxj5NnBCKG2Qb7B4spzfATVxXm/68wnjUhSBb91SIor4F J4TAq1gZgCCJVQBJeRAEC1iuYSNOxfoQ1IXMr7jQfciHSnMdmxnbbzuOcWk9f1pYsq4L K8hCAvnsEBXb6c7W2e0BAVGVTEJH5pJa3u8Oz6Vd7YyVy6yX3rz3DgFAFrgU+2uvLbq3 CaWjCMhwX24gbC5SLxIO6CY3mMTMcc83JwOaQ3K1wVkYT4HBk/4+dGjUSd3T5ft2Whcj y4yKlP053YhsN44kV/cAF5Vs8NHnlRlZkA7Ag48cdn8mdTUet/CWOKz2tbcr3amMs+fc QHwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=17QuqRLaHI9PERM0pqGotBi258tHVkZl0R28fGq71Cg=; b=NIlal129dN2h/7FAfTx1C9n9QnEkvso3uKoAQxL0raBDmsHhMBoPmOfs5lMkSKpF7E UVwYVmGrPTd1Le5SnLYYbVWXtfWSndMLyO7EBKklnVgVBufEEAaM36iRAeKGgPkxkSHl QaKy5X3ob5t6/DBTav0wZt34LL2ffJAxHZEmOy3Usn99r1AgrzcjXJwGQSyYUKJS3lMO qYImTMZrabWhm6wW+rzGFYkTbDGOSeSBvSvI49/GMnpjL2J4OwEpbi6t0/Nf7KwV5z2n mJWtKsLR5gl+TMBAHYVx/FthY/hTkXf0w3Piqai7Z+PY2l7jbu/n9dhHisbU4MLktOEH R8Iw== X-Gm-Message-State: APjAAAUgeGXkAe1Ry7+2du0KsmIY2pRhbwqYHKO1gs5UCgIBQj/c9iU1 PUuqOp2fGCDY2TNMpBERNcliP+DxADR7SdmDxE/RMQ== X-Google-Smtp-Source: APXvYqzHeAgeZqDCyqb4YRKneKRh9qli/CXPcohuMsPKmTv+mYev2IGwBC+5bk9/mDhuSzjVgfDMtXXu4ANUHZDPVYo= X-Received: by 2002:aed:39e7:: with SMTP id m94mr3095242qte.0.1561543142006; Wed, 26 Jun 2019 02:59:02 -0700 (PDT) MIME-Version: 1.0 References: <1561532654-6277-1-git-send-email-mw@semihalf.com> <20190626093155.bjetr56imew7q74v@bivouac.eciton.net> In-Reply-To: <20190626093155.bjetr56imew7q74v@bivouac.eciton.net> From: "Marcin Wojtas" Date: Wed, 26 Jun 2019 11:58:49 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH] Marvell/Drivers: XenonDxe: Explicitly disable HS400 To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, =C5=9Br., 26 cze 2019 o 11:31 Leif Lindholm napi= sa=C5=82(a): > > On Wed, Jun 26, 2019 at 09:04:14AM +0200, Marcin Wojtas wrote: > > Ensure that in case of SlowMode or 3.3V operation, > > also the HS400 capability will be disabled in the > > SdMmc driver. > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > Well done on keeping this tag. But I'm thinking we need to do that > relicensing sooner rather than later, and drop the tag. I left it, as this file is still not 2-clause SPDX tagged. > > > However, can you clarify what problem this solves? > On another SoC revision, the capability register marks HS400 support as enabled. However the interface itself is powered with 3.3V and it turned out that my flags in SdMmcOverride driver did not cover this case, which resulted in an unsuccessful EmmcSwitchToHS400 () execution - it shouldn't be done at all. Best regards, Marcin > / > Leif > > > Signed-off-by: Marcin Wojtas > > --- > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-- > > 2 files changed, 4 insertions(+), 2 deletions(-) > > > > diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Sili= con/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > index 8bf1835..2d7c7f0 100644 > > --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > @@ -82,6 +82,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH = DAMAGE. > > #define SDHC_CAP_SDR50 BIT32 > > #define SDHC_CAP_SDR104 BIT33 > > #define SDHC_CAP_DDR50 BIT34 > > +#define SDHC_CAP_HS400 BIT63 > > #define SDHC_MAX_CURRENT_CAP 0x0048 > > #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 > > #define SDHC_FORCE_EVT_ERR_INT 0x0052 > > diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.= c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > index 7a9266e..55ebcf8 100644 > > --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > @@ -357,7 +357,8 @@ XenonSdMmcCapability ( > > Capability &=3D ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE_3= 0); > > } else { > > Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | > > - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); > > + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | > > + SDHC_CAP_VOLTAGE_18); > > } > > > > if (!SdMmcDesc.Xenon8BitBusEnabled) { > > @@ -365,7 +366,7 @@ XenonSdMmcCapability ( > > } > > > > if (SdMmcDesc.XenonSlowModeEnabled) { > > - Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); > > + Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDHC_= CAP_HS400); > > } > > > > Capability &=3D ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); > > -- > > 2.7.4 > >