From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f171.google.com (mail-qk1-f171.google.com [209.85.222.171]) by mx.groups.io with SMTP id smtpd.web09.2107.1627975791256304323 for ; Tue, 03 Aug 2021 00:29:51 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=aM2Pe527; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.171, mailfrom: mw@semihalf.com) Received: by mail-qk1-f171.google.com with SMTP id a19so643057qkg.2 for ; Tue, 03 Aug 2021 00:29:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=oJt98z8lYgXfwh1jSH/75wJC8qPnhXcqV6sXqiW4rl4=; b=aM2Pe5275KDilB+6ixKY1k0CDgviN9pWjZGifJod9aRWmDWkFfFKxzWaGA5nXmuiaz zxln3581pkE8uUTMqNhBnhSIGgW0ZncVbrRcnS977n1mYvtZwRf6L8gCsSEz2KlpZRYQ +uZtavmXASMmUXQ3vgASPRxPJzNRSQNaIwa8DnC37EU32j+4PLxEON6ZZdPFWTFb2DJx iV6XeDyrK2tDhV8t/S641wKG4VuQdZMu3ZUmoovYTrECsPqlV2B9pmPLBKwoOUs7Hh3m dmJAxwcVlrBpq57Zw+rh+pE0OOft/dJAPDpPfhMCBPaeLr7P9pc2sxradn6c3CW+9V7E /l2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=oJt98z8lYgXfwh1jSH/75wJC8qPnhXcqV6sXqiW4rl4=; b=aWt5O+0y/IkdRJZW+wpKxyneTNTnc3sP2D93taZPNM8txjaa0UL5ptZZn+2ORx/qPA +Oh7dJ37cErCxcFuM2zMzLganJe6cm938NJ7hN+cGIJ7DPShIb3WoeZaA2CHPW7ikGAB o/l6r/uEX/R/LR7ZSN7NshiI8YL0WgDddtJ6wX9d8T4VYKlJFFn1y/lKpjFV5oY/UIeK VsmVQRuOtqTgG+9DzqL36R8/dZex8yDimXRWo3Xdb2FyF6Moa2eu0AVo/ph2RHf9YbKq LNbD5GYbJIbxadGD39tFO4K0t3Kzwu/0RfJuBIbeovJZnvvh+q2a/r03sq5Cfc9Db31d umEQ== X-Gm-Message-State: AOAM531zlDC3maYMO2Bged8oAdgP7gNRUx/veYkBnqtuDepBKK+ATDEG b47Cf1BUva6Tiofps/mDPnKutAmoxOTuDxJwBOs2bw== X-Google-Smtp-Source: ABdhPJyH9NpA0LlpHSDCqAnK6efsOgSIM9PwKU3QQ2KTRefa+BV6kVqnL8xHdwTu9amxdSY7qUT+QgUWGKk0ALR7/1I= X-Received: by 2002:a37:313:: with SMTP id 19mr18902239qkd.295.1627975790311; Tue, 03 Aug 2021 00:29:50 -0700 (PDT) MIME-Version: 1.0 References: <20210802050051.2831716-1-mw@semihalf.com> <20210802050051.2831716-4-mw@semihalf.com> In-Reply-To: From: "Marcin Wojtas" Date: Tue, 3 Aug 2021 09:29:39 +0200 Message-ID: Subject: Re: [edk2-platforms PATCH 3/6] Marvell: Armada7k8kPciHostBridgeLib: Remove ECAM base limitation To: Ard Biesheuvel Cc: edk2-devel-groups-io , Leif Lindholm , Ard Biesheuvel , Grzegorz Jaszczyk , Grzegorz Bernacki , upstream@semihalf.com, Samer El-Haj-Mahmoud , Jon Nettleton Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable wt., 3 sie 2021 o 08:53 Ard Biesheuvel napisa=C5=82(a): > > On Mon, 2 Aug 2021 at 19:00, Marcin Wojtas wrote: > > > > Hi Ard, > > > > pon., 2 sie 2021 o 10:43 Ard Biesheuvel napisa=C5=82(= a): > > > > > > On Mon, 2 Aug 2021 at 07:01, Marcin Wojtas wrote: > > > > > > > > On CN913x-based platforms it is possible to have up to 9 PCIE > > > > root complexes. In such case it may be necessary to configure > > > > more configuration spaces with smaller bus count, so that > > > > to fit the memory layout constraints. For that purpose remove > > > > forcing ECAM base to be divisible by SIZE_256MB. > > > > > > > > > > There is one subtlety here that we need to take into account: IIUC, > > > PCIe requires that the ECAM start address of bus N equals N MB modulo > > > 256 MB. In other words, if your ECAM range lives at 1 GB + 128 MB, th= e > > > bus range has to start at bus 128. > > > > > > I think OSes are usually quite lax about this, but it is something to > > > double check regardless, even for existing platforms > > > > > > > I tested a wide range of OSs (various Linux distributions, Win10 PE, > > FreeBSD, OpenBSD and of course EDK2) and with 7 ECAMs, of which 6 are > > squeezed within 256MB memory chunk together with their mmio32 and no > > issue was observed. Moreover, if you recall, contrary to the EDK2, > > where the full bus number is used, in ACPI we expose a single 1MB > > space with the ECAM base address aligned to 0x8000. > > > > Ah yes, I had forgotten about that hack :-) A great one though. > > > Do you wish to change the assertion in EDK2 instead of removing? > > > > No worries - if all those OSes are fine with this, I don't see a point > in being pedantic. I will note, however, that you can still comply > with this requirement by changing the bus ranges: each RC only uses a > single bus, but that bus number could be (ECAM base address / 1M) % > 256 > For OS's there is indeed only bus0 exposed, but I plan to make it tunable, so that to use entire range (e.g. for FreeBSD). In EDK2 there is full coverage. FYI, in the platform I plan to submit after this patchset there 7 RC's: 1 with 255 and 6 with 15 busses (the last 1 MB in each case is used for IO space). Best regards, Marcin > > > > > > > > Signed-off-by: Marcin Wojtas > > > > --- > > > > Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciH= ostBridgeLibConstructor.c | 1 - > > > > 1 file changed, 1 deletion(-) > > > > > > > > diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBr= idgeLib/PciHostBridgeLibConstructor.c b/Silicon/Marvell/Armada7k8k/Library/= Armada7k8kPciHostBridgeLib/PciHostBridgeLibConstructor.c > > > > index 067e57a2dc..87e57aeae3 100644 > > > > --- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib= /PciHostBridgeLibConstructor.c > > > > +++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib= /PciHostBridgeLibConstructor.c > > > > @@ -219,7 +219,6 @@ Armada7k8kPciHostBridgeLibConstructor ( > > > > PcieController =3D &(BoardPcieDescription->PcieControllers[Ind= ex]); > > > > > > > > ASSERT (PcieController->PcieBusMin =3D=3D 0); > > > > - ASSERT (PcieController->ConfigSpaceAddress % SIZE_256MB =3D=3D= 0); > > > > > > > > if (PcieController->HaveResetGpio =3D=3D TRUE) { > > > > /* Reset PCIE slot */ > > > > -- > > > > 2.29.0 > > > >