From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 604F474003C for ; Fri, 12 Jan 2024 11:27:14 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=eXxr3rfHFzQDwDUfyaCLyGhUhBVtfhg+pVxGYtArClY=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1705058832; v=1; b=uoaHby0HdSZhBkkfkxGoIdPtx/FLUaGXTL9TB2iuDHWHQADYEHWSovWNnGPPbG0jZfOHmZRW aTb8a7bxhmlwU0CTUBokWg9AkFWmlktBnX7uVm5tvuA/RfPRk+O4WtHtea7t+hgd0/H9rR45lnB UWW9bAqOd+fWGEd6q6amJu/A= X-Received: by 127.0.0.2 with SMTP id 07XyYY7687511xcFJ53UMWP1; Fri, 12 Jan 2024 03:27:12 -0800 X-Received: from mail-oo1-f52.google.com (mail-oo1-f52.google.com [209.85.161.52]) by mx.groups.io with SMTP id smtpd.web11.5066.1705058832076874868 for ; Fri, 12 Jan 2024 03:27:12 -0800 X-Received: by mail-oo1-f52.google.com with SMTP id 006d021491bc7-598a5448ef5so1269365eaf.0 for ; Fri, 12 Jan 2024 03:27:11 -0800 (PST) X-Gm-Message-State: r75D1wBPiAheDVooJZRUCtrDx7686176AA= X-Google-Smtp-Source: AGHT+IFCqsv0YSMmHrNuqXaXPYQ4if7BiIXL+fCbhhWWuKWKHG64f+Rih4LA1YztXhVf4vTt7umvzGJMr/TETF1fevk= X-Received: by 2002:a4a:a84d:0:b0:596:31c6:c13c with SMTP id p13-20020a4aa84d000000b0059631c6c13cmr616980oom.12.1705058831226; Fri, 12 Jan 2024 03:27:11 -0800 (PST) MIME-Version: 1.0 References: <20231221005427.13932-1-ndhillon@marvell.com> <20231221005427.13932-3-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-3-ndhillon@marvell.com> From: "Marcin Wojtas via groups.io" Date: Fri, 12 Jan 2024 12:27:00 +0100 Message-ID: Subject: Re: [edk2-devel] [edk2-platforms PATCH v2 2/8] Silicon/Marvell: Odyssey ArmPlatformLib To: Narinder Dhillon Cc: devel@edk2.groups.io, quic_llindhol@quicinc.com, sbalcerak@marvell.com, marcin.s.wojtas@gmail.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=uoaHby0H; dmarc=none; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io +marcin.s.wojtas@gmail.com Hi Narinder, czw., 21 gru 2023 o 01:54 napisa=C5=82(a): > > From: Narinder Dhillon > > This patch adds ArmPlatformLib for Marvell Odyssey SoC. > > Signed-off-by: Narinder Dhillon > --- > .../AArch64/ArmPlatformHelper.S | 86 ++++++++++++ > .../Library/ArmPlatformLib/ArmPlatformLib.c | 79 +++++++++++ > .../Library/ArmPlatformLib/ArmPlatformLib.inf | 55 ++++++++ > .../ArmPlatformLib/ArmPlatformLibMem.c | 131 ++++++++++++++++++ > 4 files changed, 351 insertions(+) > create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPla= tformHelper.S > create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib= .c > create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib= .inf > create mode 100644 Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib= Mem.c Please move this implementation of ArmPlatformLib to: Silicon/Marvell/OdysseyPkg/Library Armada7k8 has its own implementation in Silicon/Marvell/Armada7k8k/Library/ - such Silicon/Platform specific libraries or drivers should be kept separately under proper SoC families' directories. Thanks, Marcin > > diff --git a/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHe= lper.S b/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S > new file mode 100644 > index 0000000000..757c032f84 > --- /dev/null > +++ b/Silicon/Marvell/Library/ArmPlatformLib/AArch64/ArmPlatformHelper.S > @@ -0,0 +1,86 @@ > +/** @file > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* https://spdx.org/licenses > +* > +* Copyright (C) 2023 Marvell > +* > +* Source file for Marvell ARM Platform library > +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull > +**/ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* x1 - node number > + */ > + > +.text > +.align 2 > + > +GCC_ASM_EXPORT(ArmPlatformPeiBootAction) > +GCC_ASM_EXPORT(ArmPlatformIsPrimaryCore) > +GCC_ASM_EXPORT(ArmPlatformGetPrimaryCoreMpId) > +GCC_ASM_EXPORT(ArmPlatformGetCorePosition) > +GCC_ASM_EXPORT(ArmGetCpuCountPerCluster) > + > +GCC_ASM_IMPORT(mSystemMemoryEnd) > + > +ASM_FUNC(ArmPlatformPeiBootAction) > + adr x1, PrimaryCoreMpid > + str w0, [x1] > + ldr x0, =3DMV_SMC_ID_DRAM_SIZE > + mov x1, xzr > + smc #0 > + sub x0, x0, #1 // Last valid address > + adr x1, mSystemMemoryEnd > + str x0, [x1] // Set mSystemMemoryEnd > + > + ret > + > + > +//UINTN > +//ArmPlatformGetPrimaryCoreMpId ( > +// VOID > +// ); > +ASM_FUNC(ArmPlatformGetPrimaryCoreMpId) > + MOV32(w0, FixedPcdGet32(PcdArmPrimaryCore)) > + ret > + > +//UINTN > +//ArmPlatformIsPrimaryCore ( > +// IN UINTN MpId > +// ); > +ASM_FUNC(ArmPlatformIsPrimaryCore) > + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCoreMask)) > + and x0, x0, x1 > + MOV32 (w1, FixedPcdGet32 (PcdArmPrimaryCore)) > + cmp w0, w1 > + mov x0, #1 > + mov x1, #0 > + csel x0, x0, x1, eq > + ret > + > +//UINTN > +//ArmPlatformGetCorePosition ( > +// IN UINTN MpId > +// ); > +ASM_FUNC(ArmPlatformGetCorePosition) > +/* > + Affinity Level 0: single thread 0 > + Affinity Level 1: clustering 0( > + Affinity Level 2: number of clusters up to 64 (CN10K)/ 80 (Odyssey)/ 1= 6 (Iliad) > + Affinity Level 3: number of chip 0 > + LinearId =3D Aff2 > +*/ > + and x0, x0, #ARM_CORE_AFF2 > + lsr x0, x0, #16 > + ret > + > +ASM_FUNCTION_REMOVE_IF_UNREFERENCED > + > +PrimaryCoreMpid: .word 0x0 > diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c b/Si= licon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c > new file mode 100644 > index 0000000000..ed48a00950 > --- /dev/null > +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.c > @@ -0,0 +1,79 @@ > +/** @file > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* https://spdx.org/licenses > +* > +* Copyright (C) 2022 Marvell > +* > +* Source file for Marvell ARM Platform library > +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull > +**/ > + > +#include > +#include // EFI_BOOT_MODE > +#include // EFI_PEI_PPI_DESCRIPTOR > +#include // ASSERT > +#include // ArmPlatformIsPrimaryCore > +#include // ARM_MP_CORE_INFO_PPI > + > +/** > + Return the current Boot Mode > + > + This function returns the boot reason on the platform > + > + @return Return the current Boot Mode of the platform > + > +**/ > +EFI_BOOT_MODE > +ArmPlatformGetBootMode ( > + VOID > + ) > +{ > + return BOOT_WITH_FULL_CONFIGURATION; > +} > + > +/** > + Initialize controllers that must setup in the normal world > + > + This function is called by the ArmPlatformPkg/PrePei or ArmPlatformPkg= /Pei/PlatformPeim > + in the PEI phase. > + > +**/ > +RETURN_STATUS > +ArmPlatformInitialize ( > + IN UINTN MpId > + ) > +{ > + ASSERT(ArmPlatformIsPrimaryCore (MpId)); > + > + return RETURN_SUCCESS; > +} > + > +EFI_STATUS > +PrePeiCoreGetMpCoreInfo ( > + OUT UINTN *CoreCount, > + OUT ARM_CORE_INFO **ArmCoreTable > + ) > +{ > + return EFI_UNSUPPORTED; > +} > + > +ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi =3D { PrePeiCoreGetMpCoreInfo }; > + > +EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] =3D { > + { > + EFI_PEI_PPI_DESCRIPTOR_PPI, > + &gArmMpCoreInfoPpiGuid, > + &mMpCoreInfoPpi > + } > +}; > + > +VOID > +ArmPlatformGetPlatformPpiList ( > + OUT UINTN *PpiListSize, > + OUT EFI_PEI_PPI_DESCRIPTOR **PpiList > + ) > +{ > + *PpiListSize =3D sizeof(gPlatformPpiTable); > + *PpiList =3D gPlatformPpiTable; > +} > diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf b/= Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf > new file mode 100644 > index 0000000000..1a4b81adb4 > --- /dev/null > +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLib.inf > @@ -0,0 +1,55 @@ > +#/** @file > +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# https://spdx.org/licenses > +# > +# Copyright (C) 2022 Marvell > +# > +# Marvell ARM Platform library > +# Based on ArmPlatformPkg/Library/ArmPlatformLibNull > +# > +#**/ > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D ArmPlatformLib > + FILE_GUID =3D 7ea0f45b-0e06-4e45-8353-9c28b091a11= c > + MODULE_TYPE =3D BASE > + VERSION_STRING =3D 1.0 > + LIBRARY_CLASS =3D ArmPlatformLib > + > +[Packages] > + MdePkg/MdePkg.dec > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec # Include ArmPlatformLib.h > + Silicon/Marvell/MarvellSiliconPkg/MarvellSiliconPkg.dec > + > +[LibraryClasses] > + ArmLib > + HobLib > + DebugLib > + MemoryAllocationLib > + SmcLib > + > +[Sources] > + ArmPlatformLib.c > + ArmPlatformLibMem.c > + > +[Sources.AARCH64] > + AArch64/ArmPlatformHelper.S > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFdSize > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + gArmTokenSpaceGuid.PcdArmPrimaryCoreMask > + gArmTokenSpaceGuid.PcdArmPrimaryCore > + > + gMarvellSiliconTokenSpaceGuid.PcdNodeDramBase > + gMarvellSiliconTokenSpaceGuid.PcdIoBaseAddress > + gMarvellSiliconTokenSpaceGuid.PcdNodeIoBaseAddress > + gMarvellSiliconTokenSpaceGuid.PcdIoSize > + > +[Ppis] > + gArmMpCoreInfoPpiGuid > diff --git a/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c b= /Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c > new file mode 100644 > index 0000000000..1626dea6c5 > --- /dev/null > +++ b/Silicon/Marvell/Library/ArmPlatformLib/ArmPlatformLibMem.c > @@ -0,0 +1,131 @@ > +/** @file > +* > +* SPDX-License-Identifier: BSD-2-Clause-Patent > +* https://spdx.org/licenses > +* > +* Copyright (C) 2022 Marvell > +* > +* Source file for Marvell ARM Platform library > +* Based on ArmPlatformPkg/Library/ArmPlatformLibNull > +**/ > + > +#include // Basic UEFI types > +#include // DEBUG > +#include // EFI_BOOT_MODE required by P= iHob.h > +#include // EFI_RESOURCE_ATTRIBUTE_TYPE > +#include // BuildResourceDescriptorHob > +#include // PcdGet64 > +#include // ARM_MEMORY_REGION_ATTRIBUTE= _WRITE_BACK > +#include // SmcGetRamSize > +#include // AllocatePages > + > +// Number of Virtual Memory Map Descriptors > +#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS 129 > +#define MAX_NODES 1 > + > +// DDR attributes > +#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRIT= E_BACK > +#define DDR_ATTRIBUTES_UNCACHED ARM_MEMORY_REGION_ATTRIBUTE_UNCA= CHED_UNBUFFERED > + > +/** > + Return the Virtual Memory Map of your platform > + > + This Virtual Memory Map is used by MemoryInitPei Module to initialize = the MMU on your platform. > + > + @param[out] VirtualMemoryMap Array of ARM_MEMORY_REGION_DESCRIPTO= R describing a Physical-to- > + Virtual Memory mapping. This array m= ust be ended by a zero-filled > + entry > + > +**/ > +VOID > +ArmPlatformGetVirtualMemoryMap ( > + IN ARM_MEMORY_REGION_DESCRIPTOR** VirtualMemoryMap > + ) > +{ > + ARM_MEMORY_REGION_ATTRIBUTES CacheAttributes; > + ARM_MEMORY_REGION_DESCRIPTOR *VirtualMemoryTable; > + UINT64 VirtualMemoryTableSize; > + UINT64 MemoryBase; > + UINT64 MemorySize; > + UINTN Index =3D 0; > + UINTN Node; > + EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes; > + > + ASSERT (VirtualMemoryMap !=3D NULL); > + > + VirtualMemoryTableSize =3D sizeof(ARM_MEMORY_REGION_DESCRIPTOR) * MAX_= VIRTUAL_MEMORY_MAP_DESCRIPTORS; > + VirtualMemoryTable =3D AllocatePages (EFI_SIZE_TO_PAGES (VirtualMemory= TableSize)); > + > + if (VirtualMemoryTable =3D=3D NULL) { > + return; > + } > + > + CacheAttributes =3D DDR_ATTRIBUTES_CACHED; > + > + ResourceAttributes =3D > + EFI_RESOURCE_ATTRIBUTE_PRESENT | > + EFI_RESOURCE_ATTRIBUTE_INITIALIZED | > + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE | > + EFI_RESOURCE_ATTRIBUTE_TESTED; > + > + > + VirtualMemoryTable[Index].PhysicalBase =3D PcdGet64(PcdFdBaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D PcdGet64(PcdFdBaseAddress); > + VirtualMemoryTable[Index].Length =3D PcdGet32(PcdFdSize); > + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; > + Index++; > + > + BuildResourceDescriptorHob (EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + PcdGet64 (PcdFdBaseAddress), > + PcdGet32 (PcdFdSize)); > + > + for (Node =3D 0; Node < MAX_NODES; Node++) { > + MemoryBase =3D Node * FixedPcdGet64(PcdNodeDramBase); > + MemorySize =3D SmcGetRamSize(Node); > + > + MemoryBase +=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : = 0; > + MemorySize -=3D (Node =3D=3D 0) ? PcdGet64(PcdSystemMemoryBase) : = 0; > + > + BuildResourceDescriptorHob ( > + EFI_RESOURCE_SYSTEM_MEMORY, > + ResourceAttributes, > + MemoryBase, > + MemorySize); > + > + DEBUG ((DEBUG_LOAD | DEBUG_INFO, "Memory %lx @ %lx\n", MemorySize= , MemoryBase)); > + VirtualMemoryTable[Index].PhysicalBase =3D MemoryBase; > + VirtualMemoryTable[Index].VirtualBase =3D MemoryBase; > + VirtualMemoryTable[Index].Length =3D MemorySize; > + VirtualMemoryTable[Index].Attributes =3D CacheAttributes; > + > + Index++; > + } > + > + for (Node =3D 0; Node < MAX_NODES; Node++) { > + VirtualMemoryTable[Index].PhysicalBase =3D FixedPcdGet64(PcdIoBaseA= ddress) + > + Node * FixedPcdGet64(Pcd= NodeIoBaseAddress); > + VirtualMemoryTable[Index].VirtualBase =3D FixedPcdGet64(PcdIoBaseA= ddress) + > + Node * FixedPcdGet64(Pcd= NodeIoBaseAddress); > + VirtualMemoryTable[Index].Length =3D FixedPcdGet64(PcdIoSize)= ; > + VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB= UTE_DEVICE; > + > + DEBUG ((DEBUG_LOAD | DEBUG_INFO, > + "IO %lx @ %lx\n", > + VirtualMemoryTable[Index].Length, > + VirtualMemoryTable[Index].PhysicalBase)); > + > + Index++; > + } > + > + // End of Table > + VirtualMemoryTable[Index].PhysicalBase =3D 0; > + VirtualMemoryTable[Index].VirtualBase =3D 0; > + VirtualMemoryTable[Index].Length =3D 0; > + VirtualMemoryTable[Index].Attributes =3D (ARM_MEMORY_REGION_ATTRIBUT= ES)0; > + > + *VirtualMemoryMap =3D VirtualMemoryTable; > +} > -- > 2.34.1 > -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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