From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=Mc4Zgse2; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.194, mailfrom: mw@semihalf.com) Received: from mail-qk1-f194.google.com (mail-qk1-f194.google.com [209.85.222.194]) by groups.io with SMTP; Thu, 09 May 2019 03:16:40 -0700 Received: by mail-qk1-f194.google.com with SMTP id k189so1110031qkc.0 for ; Thu, 09 May 2019 03:16:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=o69UPg2NQmCyOfdnNtotg2kUcsa3SXWGs9e7CWwSDVU=; b=Mc4Zgse23jywATKpar+TZ2Ul9qNW5Whb+oBPAhth1D/FJU7gqiNThjLoCQFMLf5F+d SgTSJreqQYvJzjNMdGfUYPPVDaf0hBRaafuVy0SKt+QrOmyJQZvELgFvypMqel54zV8e x/KVfPoPvX0RVkAyRb3+yUPvxiHROZ1wrY65VTH42/v2oMwE4pmY/a1G6JoP610Nie0j BbD+jZBjw2T3Ima6ehmedOIn2wGdcOitL2+TFUKVwUvxNi4LOAqTGBn8NKUjD9qkLx1c oxEG3yqctafN0a9l1NssCdQKZ0+Pqd+koEKzxjyTgA8bFnGz+VNsHmCJwMsSzAYDF7Y/ mhFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=o69UPg2NQmCyOfdnNtotg2kUcsa3SXWGs9e7CWwSDVU=; b=UgWc30hzqc8duqw1HseAj/X7gPECB+Dbgt1dsaImU/AFmSDJ5XurqFmyDXkwmgUbjG J+OKx7yKcrWCxqvt71zQ2fiM34VC9twqjIQImKTvCV0RcZMwT1bFoT/R9TGygIBkM2aV vVWK3fE9M8a/4HdV8hOeHqNCqmp6Yo5Ixtdp5fd1iIj7f5WZZMHsbiEcSrpDfbNalJfG jQ7Coiauw5wLBJd8+r8NZsmF8eF4p/GO5+dNcggYNp7lXTAnPM5xJFK0NymwdSJfbz5L W7OqGL6SKi/kdtCxMGFOHcSUdD8UZKxNp66UUg68ck68jzncq8G2BIfzth0cJMz0Zvhz PIbA== X-Gm-Message-State: APjAAAWKfryhNJjK+aQdTiAnjbVj5NuvLsLcEkvi1cXJ6k2T1AlAF4gG y2az0zEi+HaqyILnRf/DvEV8OtkSFt/2ZZRsZEJrzeEEODs= X-Google-Smtp-Source: APXvYqwYnOPjxvXdJXmA0O7iJL0NIVeBYOLwfdIjCnpcjtxKm6BazhFaPaVbqFqOnTYcyLUtvpGsjELiP8MHLaYQynM= X-Received: by 2002:a37:4ccd:: with SMTP id z196mr2571865qka.57.1557396998511; Thu, 09 May 2019 03:16:38 -0700 (PDT) MIME-Version: 1.0 References: <1557395622-32425-1-git-send-email-mw@semihalf.com> <1557395622-32425-5-git-send-email-mw@semihalf.com> In-Reply-To: <1557395622-32425-5-git-send-email-mw@semihalf.com> From: "Marcin Wojtas" Date: Thu, 9 May 2019 12:16:26 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH 04/14] Marvell/Armada7k8k: Extend board description libraries with PCIE To: edk2-devel-groups-io Cc: Leif Lindholm , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable czw., 9 maj 2019 o 11:53 Marcin Wojtas napisa=C5=82(a): > > This patch extends ArmadaBoardDescLib libraries for all > existing Armada7k8k-based platforms with PCIE. > It introduces ArmadaBoardPcieControllerGet routine with > per-board PCIE controllers description. > > Contributed-under: TianoCore Contribution Agreement 1.1 > Signed-off-by: Marcin Wojtas > --- > Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0DbBoard= DescLib.c | 48 ++++++++++++++++++++ > Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0DbBoard= DescLib.c | 48 ++++++++++++++++++++ > Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armada80x0= McBinBoardDescLib.c | 48 ++++++++++++++++++++ > 3 files changed, 144 insertions(+) > > diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armad= a70x0DbBoardDescLib.c b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDesc= Lib/Armada70x0DbBoardDescLib.c > index f0133ec..cbd23cc 100644 > --- a/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0Db= BoardDescLib.c > +++ b/Platform/Marvell/Armada70x0Db/Armada70x0DbBoardDescLib/Armada70x0Db= BoardDescLib.c > @@ -46,6 +46,54 @@ ArmadaBoardGpioExpanderGet ( > } > > // > +// PCIE > +// > +STATIC > +MV_PCIE_CONTROLLER mPcieController[] =3D { > + { /* PCIE2 @0xF2640000 */ > + .PcieBaseAddress =3D 0xF2640000, > + .ConfigSpaceAddress =3D 0xE0000000, > + .HaveResetGpio =3D FALSE, > + .PcieResetGpio =3D { 0 }, > + .PcieBusMin =3D 0, > + .PcieBusMax =3D 0xFE, > + .PcieIoTranslation =3D 0xEFF00000, > + .PcieIoWinBase =3D 0x0, > + .PcieIoWinSize =3D 0x10000, > + .PcieMmio32Translation =3D 0, > + .PcieMmio32WinBase =3D 0xC0000000, > + .PcieMmio32WinSize =3D 0x20000000, > + .PcieMmio64Translation =3D 0, > + .PcieMmio64WinBase =3D 0x800000000, > + .PcieMmio64WinSize =3D 0x100000000, > + } > +}; > + > +/** > + Return the number and description of PCIE controllers used on the plat= form. > + > + @param[in out] **PcieControllers Array containing PCIE controller= s' > + description. > + @param[in out] *PcieControllerCount Amount of used PCIE controllers. > + > + @retval EFI_SUCCESS The data were obtained successfu= lly. > + @retval other Return error status. > + > +**/ > +EFI_STATUS > +EFIAPI > +ArmadaBoardPcieControllerGet ( > + IN OUT MV_PCIE_CONTROLLER **PcieControllers, > + IN OUT UINTN *PcieControllerCount > + ) > +{ > + *PcieControllers =3D mPcieController; > + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); > + > + return EFI_SUCCESS; > +} > + > +// > // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoC= DescLib > // > STATIC > diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armad= a80x0DbBoardDescLib.c b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDesc= Lib/Armada80x0DbBoardDescLib.c > index 61b6202..5781756 100644 > --- a/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0Db= BoardDescLib.c > +++ b/Platform/Marvell/Armada80x0Db/Armada80x0DbBoardDescLib/Armada80x0Db= BoardDescLib.c > @@ -52,6 +52,54 @@ ArmadaBoardGpioExpanderGet ( > } > > // > +// PCIE > +// > +STATIC > +MV_PCIE_CONTROLLER mPcieController[] =3D { > + { /* PCIE0 @0xF2600000 */ > + .PcieBaseAddress =3D 0xF2600000, > + .ConfigSpaceAddress =3D 0xE0000000, > + .HaveResetGpio =3D FALSE, > + .PcieResetGpio =3D { 0 }, > + .PcieBusMin =3D 0, > + .PcieBusMax =3D 0xFE, > + .PcieIoTranslation =3D 0xEFF00000, > + .PcieIoWinBase =3D 0x0, > + .PcieIoWinSize =3D 0x10000, > + .PcieMmio32Translation =3D 0, > + .PcieMmio32WinBase =3D 0xC0000000, > + .PcieMmio32WinSize =3D 0x20000000, > + .PcieMmio64Translation =3D 0, > + .PcieMmio64WinBase =3D 0x800000000, > + .PcieMmio64WinSize =3D 0x100000000, > + } > +}; > + > +/** > + Return the number and description of PCIE controllers used on the plat= form. > + > + @param[in out] **PcieControllers Array containing PCIE controller= s' > + description. > + @param[in out] *PcieControllerCount Amount of used PCIE controllers. > + > + @retval EFI_SUCCESS The data were obtained successfu= lly. > + @retval other Return error status. > + > +**/ > +EFI_STATUS > +EFIAPI > +ArmadaBoardPcieControllerGet ( > + IN OUT MV_PCIE_CONTROLLER **PcieControllers, > + IN OUT UINTN *PcieControllerCount > + ) > +{ > + *PcieControllers =3D mPcieController; > + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); > + > + return EFI_SUCCESS; > +} > + > +// > // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoC= DescLib > // > STATIC > diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLi= b/Armada80x0McBinBoardDescLib.c b/Platform/SolidRun/Armada80x0McBin/Armada8= 0x0McBinBoardDescLib/Armada80x0McBinBoardDescLib.c > index 32596ad..11a889b 100644 > --- a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armad= a80x0McBinBoardDescLib.c > +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBinBoardDescLib/Armad= a80x0McBinBoardDescLib.c > @@ -39,6 +39,54 @@ ArmadaBoardGpioExpanderGet ( > } > > // > +// PCIE > +// > +STATIC > +MV_PCIE_CONTROLLER mPcieController[] =3D { > + { /* PCIE0 @0xF2600000 */ > + .PcieBaseAddress =3D 0xF2600000, > + .ConfigSpaceAddress =3D 0xE0000000, > + .HaveResetGpio =3D FALSE, > + .PcieResetGpio =3D { 0 }, Just after pushing the patches I noticed my mistake. The reset GPIO on MacchiatoBin must be set and above fields should look like this: - .HaveResetGpio =3D FALSE, - .PcieResetGpio =3D { 0 }, + .HaveResetGpio =3D TRUE, + .PcieResetGpio =3D + { + MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER, + MV_GPIO_CP0_CONTROLLER1, + 20, + FALSE + }, This will be sent in v2, however the binary pointed in the cover letter is updated and performs the reset properly. Best regards, Marcin > + .PcieBusMin =3D 0, > + .PcieBusMax =3D 0xFE, > + .PcieIoTranslation =3D 0xEFF00000, > + .PcieIoWinBase =3D 0x0, > + .PcieIoWinSize =3D 0x10000, > + .PcieMmio32Translation =3D 0, > + .PcieMmio32WinBase =3D 0xC0000000, > + .PcieMmio32WinSize =3D 0x20000000, > + .PcieMmio64Translation =3D 0, > + .PcieMmio64WinBase =3D 0x800000000, > + .PcieMmio64WinSize =3D 0x100000000, > + } > +}; > + > +/** > + Return the number and description of PCIE controllers used on the plat= form. > + > + @param[in out] **PcieControllers Array containing PCIE controller= s' > + description. > + @param[in out] *PcieControllerCount Amount of used PCIE controllers. > + > + @retval EFI_SUCCESS The data were obtained successfu= lly. > + @retval other Return error status. > + > +**/ > +EFI_STATUS > +EFIAPI > +ArmadaBoardPcieControllerGet ( > + IN OUT MV_PCIE_CONTROLLER **PcieControllers, > + IN OUT UINTN *PcieControllerCount > + ) > +{ > + *PcieControllers =3D mPcieController; > + *PcieControllerCount =3D ARRAY_SIZE (mPcieController); > + > + return EFI_SUCCESS; > +} > + > +// > // Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoC= DescLib > // > STATIC > -- > 2.7.4 >