From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c0b::243; helo=mail-it0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it0-x243.google.com (mail-it0-x243.google.com [IPv6:2607:f8b0:4001:c0b::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 38CDF207DF2A7 for ; Fri, 1 Jun 2018 09:43:02 -0700 (PDT) Received: by mail-it0-x243.google.com with SMTP id d10-v6so2560112itj.1 for ; Fri, 01 Jun 2018 09:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=wfXiENQI+wFXTFm0Gm9Mm0bo3ZpSgGUvNt1RZ43GXTA=; b=y6NKMdcXUH346BFXeGRmnAP5lEweIDzm0TXc1E9rTAfCoJBdn0i4Bg8MDh4O6gjNab KiiA2QBiEjTOxNqqCde76EorXs1ZjIPeVDjywGn1ui2/G15pxtnBfPWejxPZ/16VcEup aMCUNW/z4UBm3ue5lA4Rl7sZzslb3Tm6MHr+mStLwKbJZTQ8qVpv7ELPUvqKYpBc80U1 R6reZjFnOPCFERc/vQhZ1hXFgaUa86Fkj8bLf/w6aPm8l2f8eqFoXYaMwHtv/P+BgHiJ XK1Gjir4Qlf0JBA9nV4hzj/QHjNTodg2CEuA2bockhmBnTncUQHsezKZ1p53cEHPs7L7 cwNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=wfXiENQI+wFXTFm0Gm9Mm0bo3ZpSgGUvNt1RZ43GXTA=; b=lc2kGyZ18ZAlZdWz/HLNf/jBUEE3AFXhyTZfePOhjLUmppFpW/EdsMYZ9zyCRdSW/4 2HVDSyppo+vB9ulaGDBG1yV14d5UC0DM2b2g5y+n1oHbv/iYoAeoTytpxJqn+dmKu6GQ 736s4cHCWdzwKpi5YQ0/RPqLW7tGEi5mxCsh7Pp466WXZEOm0vPvfkGzMezeNa4rV7Br 27D+ggM00byJJ5b9KZz+t22viM3VIKUg6jUrFGwPAFEV/4djBMLAQezZrVChG/Jw1+pZ x4Ulp1f5RZ9hXFb2SR8tr09CJZnP6aeaqDKwVMolxPesGKiC9aiVkMJD6H3EbXgGPCrT GnMQ== X-Gm-Message-State: ALKqPweVoqtICNb2aZLJO3sgoRS92/4i0NpwteQS+8d4pBYluyYoAdPQ abjnnLSJC615XIhs/fPuNF+8Wgb53Hn2Vhvh1qyudA== X-Google-Smtp-Source: ADUXVKL5QFFe55FqczbkyCJitp5Q1bCG3nM92j/z7FLFcfXqkWLejAC4/kw/08JTCiJ3YYmcUFmztRb/vyJuoxHLHsw= X-Received: by 2002:a24:2706:: with SMTP id g6-v6mr5311429ita.5.1527871381112; Fri, 01 Jun 2018 09:43:01 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:c6cc:0:0:0:0:0 with HTTP; Fri, 1 Jun 2018 09:43:00 -0700 (PDT) In-Reply-To: References: <1527863526-5494-1-git-send-email-mw@semihalf.com> <1527863526-5494-3-git-send-email-mw@semihalf.com> From: Marcin Wojtas Date: Fri, 1 Jun 2018 18:43:00 +0200 Message-ID: To: Ard Biesheuvel Cc: "edk2-devel@lists.01.org" , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Hua Jing , Grzegorz Jaszczyk , David Sniatkiwicz Subject: Re: [platforms PATCH 2/4] Marvell/Aramda7k8k: Enable PEI booting stage X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Jun 2018 16:43:02 -0000 Content-Type: text/plain; charset="UTF-8" 2018-06-01 17:30 GMT+02:00 Ard Biesheuvel : > On 1 June 2018 at 16:32, Marcin Wojtas wrote: >> PEI phase will allow to use more robust platform initialization, >> with new features like the capsule support. Wire up all >> dependencies for that purpose. >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> Signed-off-by: Marcin Wojtas >> --- >> Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf | 15 ++++++-- >> Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 40 ++++++++++++++++++-- >> 2 files changed, 48 insertions(+), 7 deletions(-) >> >> diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf >> index 69cb4cd..bf04f4d 100644 >> --- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf >> +++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf >> @@ -63,7 +63,7 @@ DATA = { >> !endif >> } >> >> -0x00001000|0x000ff000 >> +0x00001000|0x001ff000 >> gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize >> FV = FVMAIN_COMPACT >> >> @@ -221,7 +221,14 @@ READ_STATUS = TRUE >> READ_LOCK_CAP = TRUE >> READ_LOCK_STATUS = TRUE >> >> - INF ArmPlatformPkg/PrePi/PeiUniCore.inf >> + INF ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf >> + INF MdeModulePkg/Core/Pei/PeiMain.inf >> + INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf >> + INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf >> + INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf >> + INF ArmPkg/Drivers/CpuPei/CpuPei.inf >> + INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf >> + INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf >> >> FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 { >> SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { >> @@ -264,14 +271,14 @@ READ_LOCK_STATUS = TRUE >> >> [Rule.Common.PEI_CORE] >> FILE PEI_CORE = $(NAMED_GUID) { >> - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi >> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi >> UI STRING ="$(MODULE_NAME)" Optional >> } >> >> [Rule.Common.PEIM] >> FILE PEIM = $(NAMED_GUID) { >> PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex >> - TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi >> + TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi >> UI STRING="$(MODULE_NAME)" Optional >> } >> >> diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc >> index 4129742..195b6b7 100644 >> --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc >> +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc >> @@ -145,13 +145,28 @@ >> MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf >> HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf >> PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf >> - PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf >> ArmGicArchLib|ArmPkg/Library/ArmGicArchSecLib/ArmGicArchSecLib.inf >> PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >> >> [LibraryClasses.common.SEC, LibraryClasses.common.PEIM] >> - MemoryInitPeiLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf >> BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf >> + PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf >> + >> +[LibraryClasses.common.PEI_CORE, LibraryClasses.common.PEIM] >> + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf >> + BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf >> + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf >> + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf >> + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf >> + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf >> + PeiServicesTablePointerLib|ArmPkg/Library/PeiServicesTablePointerLib/PeiServicesTablePointerLib.inf >> + >> +[LibraryClasses.common.PEI_CORE] >> + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf >> + >> +[LibraryClasses.common.PEIM] >> + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf >> + MemoryInitPeiLib|Silicon/Marvell/Armada7k8k/Library/Armada7k8kMemoryInitPeiLib/Armada7k8kMemoryInitPeiLib.inf >> >> [LibraryClasses.common.DXE_CORE] >> HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf >> @@ -336,8 +351,13 @@ >> # ARM Pcds >> gArmTokenSpaceGuid.PcdSystemMemoryBase|0 >> gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000 >> + >> + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|36 >> gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|36 >> >> + gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000 >> + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFFC0 >> + > > These were copy/pasted from SynQuacer, I suppose? > SynQuacer and ARM VExpress use this value, I also checked ones used in HiSilicon Platforms - I didn't notice any issue with neither of them. > Ideally, these should point to some memory that is not exposed to the > OS, so that the PEI phase cannot corrupt a capsule image that has been > left in DRAM by the OS. > > This only becomes relevant once we implement support for PSCI warm > reboot, otherwise DRAM will be cleared anyway. However, pointing these > into a random slice of main memory feels a little risky. Currently we have also a hole between 0xc0000000 - 4GB for the config space, so how about squeezing those 64kB there? Alternatively would you recommend to use value outside the DRAM space (e.g. above max DRAM size)? > > Do you have non-secure SRAM on this SoC? There are a couple of SRAMs (for offload CM3 CPUs), one configured as secure. Not sure about others. Why do you ask? Best regards, Marcin > >> # Secure region reservation >> gMarvellTokenSpaceGuid.PcdSecureRegionBase|0x4000000 >> gMarvellTokenSpaceGuid.PcdSecureRegionSize|0x0200000 >> @@ -364,7 +384,21 @@ >> [Components.common] >> >> # PEI Phase modules >> - ArmPlatformPkg/PrePi/PeiUniCore.inf >> + ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf >> + MdeModulePkg/Core/Pei/PeiMain.inf >> + MdeModulePkg/Universal/PCD/Pei/Pcd.inf { >> + >> + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf >> + } >> + ArmPlatformPkg/PlatformPei/PlatformPeim.inf >> + ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf >> + ArmPkg/Drivers/CpuPei/CpuPei.inf >> + MdeModulePkg/Universal/Variable/Pei/VariablePei.inf >> + MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf { >> + >> + NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf >> + } >> + >> >> # DXE >> MdeModulePkg/Core/Dxe/DxeMain.inf { >> -- >> 2.7.4 >>