From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::d2c; helo=mail-io1-xd2c.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io1-xd2c.google.com (mail-io1-xd2c.google.com [IPv6:2607:f8b0:4864:20::d2c]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 867DB21168222 for ; Fri, 12 Oct 2018 09:49:18 -0700 (PDT) Received: by mail-io1-xd2c.google.com with SMTP id w11-v6so9698230iob.2 for ; Fri, 12 Oct 2018 09:49:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=tVBjFfabZyv1q9dQVjSWV/8SoTjL4JVHxB6Vk+jke3M=; b=pXO+dzdyNIL9BXnCk8S09z6pLZG2yE+04RVhYw+i9kUFvQcdAddDvPhdcIRNTq2Php BnWhV92U1O4PV363hpWfS7DgWd8jE6wWo1i2wRtzdGzxO/IvFVnvNHKh1JGhtxPwxXtN /Xdd2IN8zs/iT6KsKMZTbNOAvCI8G9g6aVjP+cyTe711pZD4+rTIFR6bksq16EGsjfGE rMiHT0UWex3OuLjHvRoukkRw2zq504NDduVDYU0PdA9OIUMIAh2VnPdhygSyT17xu5Wr j/OUAKG6USj0a0uGt5BZNnyGQb7N5QiN3Q3nt7m13Z825YYFYMAl0S1uljUlBiUNhfgb 5Pmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=tVBjFfabZyv1q9dQVjSWV/8SoTjL4JVHxB6Vk+jke3M=; b=LnJdNIBYbs9w4ru2hQFaV5AEFws+CVrP5SHZltMnkozFaQTtaFgCZMU+yZxcqLBcSV /yHY6DGrCm3Ym9pGPE8jSYxz+VP8aY1dhrpBtJhP2ebe+EfYjc5Xe/+wB83VWApYtnba oFEH5luELVEck82CWRzyBGEiMDc6/jSURSo3dwLOWHo2H4X+Mmj+rVuVeuVQ4PCg/enO 6BXNN84Xxzi567TZURo1dPuQflCT5bcXLA6UlqtZN5eoIv5EnhHW9Ua++Q/11Spm1X7x 3vJ8ZltM5+JA1mM2dBC92FusBN0n7US7aie/Abf7+7IuKIBSC/8VBlXfdC+GN7yAEI/r x46g== X-Gm-Message-State: ABuFfohF2jA81+xmfyfopA1I9CEivQhKyG8nG13+aNmqru49G/Lg+pxx 6QnxlZuVqlCF19PRGkHD3+5q4wM6lfhOivjOdisZOw== X-Google-Smtp-Source: ACcGV63D6qq7cRzbYfVCAAiiseM0yqzk8sZeOV0S/WaTZ59Gw4Rj5H+FK+ItdUIMUNLauKvgCVO8nvfXiOHnDTon3tA= X-Received: by 2002:a5e:c643:: with SMTP id s3-v6mr4925957ioo.108.1539362957585; Fri, 12 Oct 2018 09:49:17 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Fri, 12 Oct 2018 18:49:05 +0200 Message-ID: To: Ard Biesheuvel Cc: "Gao, Liming" , "Kinney, Michael D" , "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , "Zeng, Star" , edk2-devel-01 , eric.dong@intel.com, hao.a.wu@intel.com, nadavh@marvell.com Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 16:49:18 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pt., 12 pa=C5=BA 2018 o 18:24 Ard Biesheuvel na= pisa=C5=82(a): > > On Fri 12 Oct 2018 at 18:04, Marcin Wojtas wrote: > > > > pt., 12 pa=C5=BA 2018 o 17:55 Ard Biesheuvel napisa=C5=82(a): > > > > > > On 12 October 2018 at 07:06, Marcin Wojtas wrote: > > > > pt., 12 pa=C5=BA 2018 o 03:41 Wu, Hao A napisa= =C5=82(a): > > > >> > > > >> > -----Original Message----- > > > >> > From: Marcin Wojtas [mailto:mw@semihalf.com] > > > >> > Sent: Thursday, October 11, 2018 11:43 PM > > > >> > To: Wu, Hao A > > > >> > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong= , Eric; edk2- > > > >> > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Ze= ng, Star > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: A= dd > > > >> > UhsSignaling to SdMmcOverride protocol > > > >> > > > > >> > wt., 9 pa=C5=BA 2018 o 13:51 Marcin Wojtas nap= isa=C5=82(a): > > > >> > > > > > >> > > wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel > > > >> > napisa=C5=82(a): > > > >> > > > > > > >> > > > On 9 October 2018 at 13:32, Marcin Wojtas = wrote: > > > >> > > > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napisa=C5=82(a): > > > >> > > > >> > > > >> > > > >> > -----Original Message----- > > > >> > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.or= g] On > > > >> > Behalf Of Ard > > > >> > > > >> > Biesheuvel > > > >> > > > >> > Sent: Monday, October 08, 2018 11:10 PM > > > >> > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A > > > >> > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel= -01; Gao, > > > >> > Liming; > > > >> > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star > > > >> > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPc= iHcDxe: > > > >> > Add > > > >> > > > >> > UhsSignaling to SdMmcOverride protocol > > > >> > > > >> > > > > >> > > > ... > > > >> > > > >> > > > > >> > > > >> > I suppose this is defined by the eMMC spec. > > > >> > > > >> > > > > >> > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 r= egister values > > > >> > > > >> > for HS200/HS400 defined by the eMMC spec? > > > >> > > > >> > > > >> > > > >> Hi Ard and Marcin, > > > >> > > > >> > > > >> > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (= latest) does > > > >> > not > > > >> > > > >> mention on how to set the "UHS Mode Select" field of the = Host > > > >> > Control 2 > > > >> > > > >> Register when switching to HS200/HS400. (Actually, the EM= MC spec > > > >> > does not > > > >> > > > >> mention Host Control 2 Register at all) > > > >> > > > >> > > > >> > > > >> When it comes to setting the bus mode for EMMC devices, t= he current > > > >> > > > >> implementation of the SdMmcPciHcDxe driver does a mapping= when > > > >> > setting the > > > >> > > > >> Host Control 2 Register: > > > >> > > > >> > > > >> > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single > > > >> > > > >> matches > > > >> > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single > > > >> > > > >> > > > >> > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual > > > >> > > > >> matches > > > >> > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual > > > >> > > > >> > > > >> > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single > > > >> > > > >> matches > > > >> > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single > > > >> > > > >> > > > >> > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual > > > >> > > > >> matches > > > >> > > > >> SD None > > > >> > > > >> > > > >> > > > >> And there is no obvious counterpart for the EMMC HS400 mo= de in the > > > >> > SD > > > >> > > > >> spec. The driver currently sets the "UHS Mode Select" fie= ld to a > > > >> > reserved > > > >> > > > >> value 0x5. > > > >> > > > >> > > > >> > > > > > > > >> > > > > Thank you Hao, above is on par with what the default UhsSi= gnaling > > > >> > > > > routine does in this patch. IMO especially in case the EMM= C standard > > > >> > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage t= o accept > > > >> > > > > some way of updating HostControl2 register, depending on t= he > > > >> > > > > implementation. What is your opinion Ard? > > > >> > > > > > > > >> > > > > > > >> > > > I would like to know where the current values in SdMmcPciHcD= xe come > > > >> > > > from if they are not defined in any spec. > > > >> > > > > > > >> > > > How do we know which ones are the correct ones? > > > >> > > > > > >> > > Hao, can you justify used values? > > > >> > > > > > >> > > > > >> > Hi Hao, > > > >> > > > > >> > Can you please take a look at the UHS_MODE_SEL values source for= eMMC? > > > >> > > > >> Hi Marcin, > > > >> > > > >> Sorry for the delayed response. > > > >> > > > >> For the current implementation of the SdMmcPciHcDxe driver, the se= lecting > > > >> of "UHS Mode Select" field value of the Host Control 2 Register is= based > > > >> on a Max Clock Frequency & Data Rate (Single or Dual) matching > > > >> relationship between the: > > > >> > > > >> A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simpli= fied > > > >> Specification Version 4.10 > > > >> > > > >> and > > > >> > > > >> B. Table 4 of the EMMC Electrical Standard Spec 5.1 > > > >> > > > >> The matching details was included in my previous reply. The only m= issing > > > >> part is there seems no matching for the EMMC HS400 mode in the SD > > > >> specifications. For this case, we are currently using the same app= roach > > > >> with the Linux implementation, that is to set the "UHS Mode Select= " to a > > > >> value of 0x5 (not standard). > > > >> > > > > > > > > Hao, > > > > > > > > Thanks a lot for the clarification. > > > > > > > > Ard, > > > > > > > > Knowing the numbers details, what is your view of the UhsSignaling = handling? > > > > > > > > > > I think it makes sense to be able to override the SD->MMC mapping for > > > HC2 attributes. But it seems to me that this mapping is rather ad-hoc > > > and so it should apply to all configuration that is inferred: > > > UhsSignalling does not quite cover it. > > > > > > So I think the approach is correct, but we need a better name. > > > > Do you mean to update more fields in HC2 than UHS_MODE_SEL? > > AIUI the EMMC spec does not mention HC2 at all, and yet we have to set > it to a sane value, and we are currently using fuzzy logic for it. > Or are the other fields less ambiguous? I don't think so. How about renaming the phase type to: EdkiiSdMmcBusSpeedModeSelect? Best regards, Marcin