From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=iCZQ5O2T; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.196, mailfrom: mw@semihalf.com) Received: from mail-qk1-f196.google.com (mail-qk1-f196.google.com [209.85.222.196]) by groups.io with SMTP; Fri, 27 Sep 2019 08:06:09 -0700 Received: by mail-qk1-f196.google.com with SMTP id 4so2213970qki.6 for ; Fri, 27 Sep 2019 08:06:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=7Hry5wWm3Cdzlu/5AEtza3+AhwkAuUq4/CeLhKBKDp4=; b=iCZQ5O2TdXeCKnFQME2/7qW5Oic3CpZpZFBSBnf+BgUhAMJZtuZflRVbYNjAOgbkd2 ReJ42CN1o6KE8uTmTchpw8JrRdsnYa6+iy0fFZzuPfPW4sWpCc5TMRXoj+yNob1QQHqO EE1SuSdYxbh/fnIjy323rgZMld+nFUanE58oaM+XBn12rhOfJXL0nM/sH91J43ax3T6o ueKMTZJ2cJRexuKeX5JrTSom1aPiqub/tX6fR2ki3YwU3IZldUnY3nYD3MWfnSrp4kcU GHrAjzixj5qndaa8iM7M5l7vsApt18xHstLrZ39Q53hh5sPwIVJ4EVw4e6UDRiwSeuFV PX5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=7Hry5wWm3Cdzlu/5AEtza3+AhwkAuUq4/CeLhKBKDp4=; b=LALFuGh5q+Gw9G00vB+WbUaejKjH7vFqxlh7+SeDWYO2cGspCiqlUYq/VRnkNBW2yA eYwI8lMYLjr+BE9dNtc8c+fMo7jDOJPwrBXSPlU3EjKFeN9kG6b9B5rKIBP60wQPtLmZ j1h+B5PMCuJ2Ct0K/JkQ1cZ9D4gKs/oLUTIk5ON0v616w+X54Co2cVP6LgnR3hwxDtCe WB3ZOG3xTf7IyWrNdoNn/ZDLXsJ38SCnRxr9gvCMbO941FhZVx4LhqQSZMV/efRcJy+3 QT8YCXvrctTPeoEbJgC7WWEDzG8uaqjAZjGusM/X4C+dj5+ymhiNTMh9/gSeaXHGF1ll AKuA== X-Gm-Message-State: APjAAAUnaqoQd2mdoCbKA4Ed7hH4TbbsLoAGBvDD6pPBAGxl7dDRxxXQ fzWfYtAaJUrJQSs24qWzXq7KQXOrOwIbGZxhG7abuw== X-Google-Smtp-Source: APXvYqxAfeFoY9wJQrz/u8zVmVg9I08xMssNNCtVmvaRSee7ZUIBIT8luCQsBC1lKDIdgiyZhHLbvjtLL+ODc6Qf2Pg= X-Received: by 2002:a37:c441:: with SMTP id h1mr4876464qkm.16.1569596768522; Fri, 27 Sep 2019 08:06:08 -0700 (PDT) MIME-Version: 1.0 References: <20190923083701.1496-1-mateusz.albecki@intel.com> In-Reply-To: From: "Marcin Wojtas" Date: Fri, 27 Sep 2019 17:05:56 +0200 Message-ID: Subject: Re: [PATCH 0/1] Fix eMMC bus timing switch issue To: "Wu, Hao A" Cc: "Albecki, Mateusz" , edk2-devel-groups-io Content-Type: multipart/alternative; boundary="000000000000d4247305938a39e3" --000000000000d4247305938a39e3 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Thanks! Everything keep working on my boards: Tested-by: Marcin Wojtas Best regards, Marcin pt., 27 wrz 2019 o 03:38 Wu, Hao A napisa=C5=82(a): > Hello Marcin, > > > > I have uploaded the V2 series to my fork. > > You can get the patch at: > > https://github.com/hwu25/edk2/tree/emmc_busmode_v2 > > > > Best Regards, > > Hao Wu > > > > *From:* Marcin Wojtas [mailto:mw@semihalf.com] > *Sent:* Thursday, September 26, 2019 3:25 PM > *To:* Albecki, Mateusz > *Cc:* edk2-devel-groups-io; Wu, Hao A > *Subject:* Re: [PATCH 0/1] Fix eMMC bus timing switch issue > > > > Hi Mateusz, > > > > For the v2, could you please push the patches to some repo, so that it > would be easy to fetch and test? > > > > Best regards, > > Marcin > > > > pon., 23 wrz 2019 o 10:37 Albecki, Mateusz > napisa=C5=82(a): > > SD host controller specification section 3.9 recommends that controller's > bus timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before > call to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > In HS200 switch sequence we removed stopping and starting the SD clock wh= en > switching the host controller timing. Stopping the clock before bus timin= g > switch is only neccessary if preset value enable is set in host > controller. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. > > Tests performed: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. > > Note: We were unable to test DDR speed mode because on test machines both > new flow > and old flow was failing with this speed. I suspect it is a hardware > problem. > > Cc: Hao A Wu > Cc: Marcin Wojtas > > Albecki, Mateusz (1): > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 > +++---------------------- > 1 file changed, 5 insertions(+), 49 deletions(-) > > -- > 2.14.1.windows.1 > > -------------------------------------------------------------------- > > Intel Technology Poland sp. z o.o. > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > 957-07-52-316 | Kapital zakladowy 200.000 PLN. > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego > adresata i moze zawierac informacje poufne. W razie przypadkowego > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale je= j > usuniecie; jakiekolwiek > przegladanie lub rozpowszechnianie jest zabronione. > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). If you are not the intended > recipient, please contact the sender and delete all copies; any review or > distribution by > others is strictly prohibited. > > --000000000000d4247305938a39e3 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Thanks! Everything keep working on my boards:

Tested-by: Marcin Wojtas <mw@s= emihalf.com>

Best regards,
Marcin=

pt., 27 wrz 2019 o 03:38=C2=A0Wu, Hao A <hao.a.wu@intel.com> napisa=C5=82(a):

Hello Marcin,

=C2=A0

I have uploaded the V2 series to my fork.=

You can get the patch at:

https://github.com/hwu25/edk2/tree/emmc_busmod= e_v2

=C2=A0

Best Regards,

Hao Wu

=C2=A0

From: Marcin Wojtas [mailto:mw@sem= ihalf.com]
Sent: Thursday, September 26, 2019 3:25 PM
To: Albecki, Mateusz
Cc: edk2-devel-groups-io; Wu, Hao A
Subject: Re: [PATCH 0/1] Fix eMMC bus timing switch issue<= /u>

=C2=A0

Hi Mateusz,

=C2=A0

For the v2, could you please push the patches to som= e repo, so that it would be easy to fetch and test?

=C2=A0

Best regards,

Marcin

=C2=A0

pon= ., 23 wrz 20= 19 o 10:37=C2=A0Albecki, Mateusz <mateusz.albecki@intel.com> napisa=C5=82(a):=

SD host controller spec= ification section 3.9 recommends that controller's bus timing
should be switched after card's bus timing has been switched. In curren= t eMMC
driver implementation every host controller switch has been done before cal= l to
EmmcSwitchBusTiming= which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when=
switching the host controller timing. Stopping the clock before bus timing<= br> switch is only neccessary<= /span> if preset value enable is set in host controller.
Current code doesn't check if this field is enabled or doesn't supp= ort
this feature for any other bus timing change so it has been removed.

Tests performed:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been fai= ling
with old driver and one that has been passing with old driver. Both control= lers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both n= ew flow
and old flow was failing with this speed. I suspect it is a hardware proble= m.

Cc: Hao A Wu <ha= o.a.wu@intel.com>
Cc: Marcin Wojtas <= mw@semihalf.com>

Albecki, Mateusz (1):
=C2=A0 MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

=C2=A0MdeModulePkg/Bus/Pci= /SdMmcPciHcDxe/Emmc= Device.c | 54 +++----------------------
=C2=A01 file changed, 5 insertions(+), 49 deletions(-)

--
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | = Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru<= /span> Sadowego - K= RS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest p= rzeznaczona dla okreslonego adresata i moze zawierac informacje= poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz= trwale jej usuniecie; jakiekolwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by
others is strictly prohibited.

--000000000000d4247305938a39e3--