* [platforms: PATCH 0/3] Armada7k8k new boards support
@ 2018-06-12 14:06 Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file Marcin Wojtas
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:06 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, jinghua, mw, jsd, jaz
Hi,
This short patchset introduces support for two Armada7k8k-based
boards: MacchiatoBin and Armada-8040-Db. In order to avoid further
duplication, they use common .fdf file for entire SoC family.
More details can be found in the commit logs.
The patches are available in the github:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/boards-upstream-r20180612
I'm looking forward to review and any comments/remarks.
Best regards,
Marcin
Marcin Wojtas (3):
Marvell/Armada7k8k: Use common .fdf file
Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
Marvell/Armada7k8k: Introduce support for Armada-8040-Db
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 2 +-
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 158 ++++++++++++++++++++
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
4 files changed, 309 insertions(+), 2 deletions(-)
create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf (97%)
--
2.7.4
^ permalink raw reply [flat|nested] 11+ messages in thread
* [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file
2018-06-12 14:06 [platforms: PATCH 0/3] Armada7k8k new boards support Marcin Wojtas
@ 2018-06-12 14:06 ` Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 3/3] Marvell/Armada7k8k: Introduce support for Armada-8040-Db Marcin Wojtas
2 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:06 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, jinghua, mw, jsd, jaz
As for the preparation for adding multiple boards support,
move common part of the .fdf file to the SoC family directory
and change output FD file name to more generic.
Once needed, possible per-board differences will be resolved
by including custom .fdf.inc file. This way adding new common
changes for entire SoC family won't require any
duplication and at the same time the per-board .fdf.inc
will allow better suiting the .FD file contents.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc | 2 +-
Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
rename Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf => Silicon/Marvell/Armada7k8k/Armada7k8k.fdf (97%)
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
index 46a1ea9..eedb025 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
+++ b/Platform/Marvell/Armada70x0Db/Armada70x0Db.dsc
@@ -43,7 +43,7 @@
SUPPORTED_ARCHITECTURES = AARCH64|ARM
BUILD_TARGETS = DEBUG|RELEASE
SKUID_IDENTIFIER = DEFAULT
- FLASH_DEFINITION = Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
diff --git a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
similarity index 97%
rename from Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
rename to Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
index e5e5443..180b6c9 100644
--- a/Platform/Marvell/Armada70x0Db/Armada70x0Db.fdf
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
@@ -24,7 +24,7 @@
#
################################################################################
-[FD.Armada70x0Db_EFI]
+[FD.Armada_EFI]
BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.
Size = 0x00400000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device
ErasePolarity = 1
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:06 [platforms: PATCH 0/3] Armada7k8k new boards support Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file Marcin Wojtas
@ 2018-06-12 14:06 ` Marcin Wojtas
2018-06-12 14:11 ` Ard Biesheuvel
2018-06-12 14:23 ` Leif Lindholm
2018-06-12 14:06 ` [platforms: PATCH 3/3] Marvell/Armada7k8k: Introduce support for Armada-8040-Db Marcin Wojtas
2 siblings, 2 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:06 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, jinghua, mw, jsd, jaz
Add new board description file Armada80x0McBin.dsc,
which uses common Armada7k8k.fdf file. By default
build capsule components.
Most of the interfaces are fully functional, except for:
- USB ports - it requires merging GPIO support and VBUS
power supply enabling
- SdMmc ports - they are kept enabled, as no issues were
observed on v1.3 board so far. However higher speed modes
(HS200) and full stability will be gained after Xenon
driver improvements merge.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
1 file changed, 149 insertions(+)
create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
new file mode 100644
index 0000000..1a811d5
--- /dev/null
+++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
@@ -0,0 +1,149 @@
+#Copyright (C) 2017 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Armada80x0McBin
+ PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010019
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+ CAPSULE_ENABLE = TRUE
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ #MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+ # APN806-A0 MPP SET
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+ # CP110 MPP SET - master
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # CP110 MPP SET - slave
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ #SPI
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+ #ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ # ComPhy0
+ # 0: PCIE0 5 Gbps
+ # 1: PCIE0 5 Gbps
+ # 2: PCIE0 5 Gbps
+ # 3: PCIE0 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SATA1 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
+ # ComPhy1
+ # 0: SGMII1 1.25 Gbps
+ # 1: SATA0 5 Gbps
+ # 2: USB3_HOST0 5 Gbps
+ # 3: SATA1 5 Gbps
+ # 4: SFI 10.31 Gbps
+ # 5: SGMII2 3.125 Gbps
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
+
+ #UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ #MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
+
+ #PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ #NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+ #PciEmulation
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+ #RTC
+ gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [platforms: PATCH 3/3] Marvell/Armada7k8k: Introduce support for Armada-8040-Db
2018-06-12 14:06 [platforms: PATCH 0/3] Armada7k8k new boards support Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin Marcin Wojtas
@ 2018-06-12 14:06 ` Marcin Wojtas
2 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:06 UTC (permalink / raw)
To: edk2-devel; +Cc: leif.lindholm, ard.biesheuvel, nadavh, jinghua, mw, jsd, jaz
Add new board description file Armada80x0Db.dsc,
which uses common Armada7k8k.fdf file.
Most of the interfaces are fully functional, except for:
- USB ports - it requires merging GPIO support and VBUS
power supply enabling
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc | 158 ++++++++++++++++++++
1 file changed, 158 insertions(+)
create mode 100644 Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
diff --git a/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
new file mode 100644
index 0000000..0fc00c1
--- /dev/null
+++ b/Platform/Marvell/Armada80x0Db/Armada80x0Db.dsc
@@ -0,0 +1,158 @@
+#Copyright (C) 2017 Marvell International Ltd.
+#
+#Marvell BSD License Option
+#
+#If you received this File from Marvell, you may opt to use, redistribute and/or
+#modify this File under the following licensing terms.
+#Redistribution and use in source and binary forms, with or without modification,
+#are permitted provided that the following conditions are met:
+#
+# * Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the following disclaimer.
+#
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+#
+# * Neither the name of Marvell nor the names of its contributors may be
+# used to endorse or promote products derived from this software without
+# specific prior written permission.
+#
+#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ PLATFORM_NAME = Armada80x0Db
+ PLATFORM_GUID = 5cc803a0-9c42-498e-9086-e176d4a1f598
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010019
+ OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
+ SUPPORTED_ARCHITECTURES = AARCH64|ARM
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
+
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFixedAtBuild.common]
+ #MPP
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3
+
+ # APN806-A0 MPP SET
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
+
+ # CP110 MPP SET - master
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0xFF, 0x7, 0x0, 0x7, 0xA, 0xA, 0x2, 0x2, 0x5 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x9, 0x9, 0x8, 0x8, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0xE, 0xE, 0xE, 0xE }
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # CP110 MPP SET - slave
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3 }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x8, 0x9, 0xA }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0xA, 0x8, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
+
+ # I2C
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50, 0x57, 0x50, 0x57, 0x21, 0x25 }
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0, 0x0, 0x1, 0x1, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x1, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdEepromI2cAddresses|{ 0x50, 0x57, 0x50, 0x57 }
+ gMarvellTokenSpaceGuid.PcdEepromI2cBuses|{ 0x0, 0x0, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000
+ gMarvellTokenSpaceGuid.PcdI2cBusCount|2
+
+ #SPI
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
+
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
+
+ #ComPhy
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
+ # ComPhy0
+ # 0: PCIE0 5 Gbps
+ # 1: SATA0 5 Gbps
+ # 2: SFI 10.31 Gbps
+ # 3: SATA1 5 Gbps
+ # 4: USB_HOST1 5 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA0), $(CP_SFI), $(CP_SATA1), $(CP_USB3_HOST1), $(CP_PCIE2) }
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G), $(CP_5G), $(CP_5G) }
+ # ComPhy1
+ # 0: PCIE0 5 Gbps
+ # 1: SATA0 5 Gbps
+ # 2: SFI 10.31 Gbps
+ # 3: SATA1 5 Gbps
+ # 4: PCIE1 5 Gbps
+ # 5: PCIE2 5 Gbps
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_SATA2), $(CP_SFI), $(CP_SATA3), $(CP_PCIE1), $(CP_PCIE2) }
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }
+
+ #UtmiPhy
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
+
+ #MDIO
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x1 }
+
+ #PHY
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
+
+ #NET
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x3, 0x0, 0x2 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_10000), $(PHY_SPEED_1000) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMII), $(PHY_SFI), $(PHY_RGMII) }
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x2, 0x0, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
+
+ #PciEmulation
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
+
+ #RTC
+ gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:06 ` [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin Marcin Wojtas
@ 2018-06-12 14:11 ` Ard Biesheuvel
2018-06-12 14:15 ` Marcin Wojtas
2018-06-12 14:23 ` Leif Lindholm
1 sibling, 1 reply; 11+ messages in thread
From: Ard Biesheuvel @ 2018-06-12 14:11 UTC (permalink / raw)
To: Marcin Wojtas
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
Marcin,
Thanks for focusing on McBin first.
On 12 June 2018 at 16:06, Marcin Wojtas <mw@semihalf.com> wrote:
> Add new board description file Armada80x0McBin.dsc,
> which uses common Armada7k8k.fdf file. By default
> build capsule components.
> Most of the interfaces are fully functional, except for:
> - USB ports - it requires merging GPIO support and VBUS
> power supply enabling
??
Didn't USB work absolutely fine over a year ago?
> - SdMmc ports - they are kept enabled, as no issues were
> observed on v1.3 board so far. However higher speed modes
> (HS200) and full stability will be gained after Xenon
> driver improvements merge.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
> 1 file changed, 149 insertions(+)
> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>
> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> new file mode 100644
> index 0000000..1a811d5
> --- /dev/null
> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> @@ -0,0 +1,149 @@
> +#Copyright (C) 2017 Marvell International Ltd.
> +#
> +#Marvell BSD License Option
> +#
> +#If you received this File from Marvell, you may opt to use, redistribute and/or
> +#modify this File under the following licensing terms.
> +#Redistribution and use in source and binary forms, with or without modification,
> +#are permitted provided that the following conditions are met:
> +#
> +# * Redistributions of source code must retain the above copyright notice,
> +# this list of conditions and the following disclaimer.
> +#
> +# * Redistributions in binary form must reproduce the above copyright
> +# notice, this list of conditions and the following disclaimer in the
> +# documentation and/or other materials provided with the distribution.
> +#
> +# * Neither the name of Marvell nor the names of its contributors may be
> +# used to endorse or promote products derived from this software without
> +# specific prior written permission.
> +#
> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +#
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + PLATFORM_NAME = Armada80x0McBin
> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010019
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
> + BUILD_TARGETS = DEBUG|RELEASE
> + SKUID_IDENTIFIER = DEFAULT
> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
> + CAPSULE_ENABLE = TRUE
> +
> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFixedAtBuild.common]
> + #MPP
> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
> +
> + # APN806-A0 MPP SET
> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
> +
> + # CP110 MPP SET - master
> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> +
> + # CP110 MPP SET - slave
> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> +
> + #SPI
> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
> +
> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
> +
> + #ComPhy
> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
> + # ComPhy0
> + # 0: PCIE0 5 Gbps
> + # 1: PCIE0 5 Gbps
> + # 2: PCIE0 5 Gbps
> + # 3: PCIE0 5 Gbps
> + # 4: SFI 10.31 Gbps
> + # 5: SATA1 5 Gbps
> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
> + # ComPhy1
> + # 0: SGMII1 1.25 Gbps
> + # 1: SATA0 5 Gbps
> + # 2: USB3_HOST0 5 Gbps
> + # 3: SATA1 5 Gbps
> + # 4: SFI 10.31 Gbps
> + # 5: SGMII2 3.125 Gbps
> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
> +
> + #UtmiPhy
> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> +
> + #MDIO
> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
> +
> + #PHY
> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> +
> + #NET
> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
> +
> + #PciEmulation
> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
> +
> + #RTC
> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:11 ` Ard Biesheuvel
@ 2018-06-12 14:15 ` Marcin Wojtas
0 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:15 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: edk2-devel@lists.01.org, Leif Lindholm, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
2018-06-12 16:11 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> Marcin,
>
> Thanks for focusing on McBin first.
>
>
> On 12 June 2018 at 16:06, Marcin Wojtas <mw@semihalf.com> wrote:
>> Add new board description file Armada80x0McBin.dsc,
>> which uses common Armada7k8k.fdf file. By default
>> build capsule components.
>> Most of the interfaces are fully functional, except for:
>> - USB ports - it requires merging GPIO support and VBUS
>> power supply enabling
>
> ??
>
> Didn't USB work absolutely fine over a year ago?
>
Indeed, same as ACPI, DTB and all other stuff, that I didn't have
bandwidth to upstream. Please let me submit reworked handling for it
in follow-up patches.
Best regards,
Marcin
>
>> - SdMmc ports - they are kept enabled, as no issues were
>> observed on v1.3 board so far. However higher speed modes
>> (HS200) and full stability will be gained after Xenon
>> driver improvements merge.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
>> 1 file changed, 149 insertions(+)
>> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>>
>> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> new file mode 100644
>> index 0000000..1a811d5
>> --- /dev/null
>> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> @@ -0,0 +1,149 @@
>> +#Copyright (C) 2017 Marvell International Ltd.
>> +#
>> +#Marvell BSD License Option
>> +#
>> +#If you received this File from Marvell, you may opt to use, redistribute and/or
>> +#modify this File under the following licensing terms.
>> +#Redistribution and use in source and binary forms, with or without modification,
>> +#are permitted provided that the following conditions are met:
>> +#
>> +# * Redistributions of source code must retain the above copyright notice,
>> +# this list of conditions and the following disclaimer.
>> +#
>> +# * Redistributions in binary form must reproduce the above copyright
>> +# notice, this list of conditions and the following disclaimer in the
>> +# documentation and/or other materials provided with the distribution.
>> +#
>> +# * Neither the name of Marvell nor the names of its contributors may be
>> +# used to endorse or promote products derived from this software without
>> +# specific prior written permission.
>> +#
>> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
>> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
>> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
>> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
>> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
>> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
>> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> +#
>> +################################################################################
>> +#
>> +# Defines Section - statements that will be processed to create a Makefile.
>> +#
>> +################################################################################
>> +[Defines]
>> + PLATFORM_NAME = Armada80x0McBin
>> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
>> + PLATFORM_VERSION = 0.1
>> + DSC_SPECIFICATION = 0x00010019
>> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
>> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
>> + BUILD_TARGETS = DEBUG|RELEASE
>> + SKUID_IDENTIFIER = DEFAULT
>> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
>> + CAPSULE_ENABLE = TRUE
>> +
>> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
>> +
>> +################################################################################
>> +#
>> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
>> +#
>> +################################################################################
>> +[PcdsFixedAtBuild.common]
>> + #MPP
>> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
>> +
>> + # APN806-A0 MPP SET
>> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
>> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
>> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
>> +
>> + # CP110 MPP SET - master
>> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
>> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> +
>> + # CP110 MPP SET - slave
>> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
>> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> +
>> + #SPI
>> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
>> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
>> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
>> +
>> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
>> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
>> +
>> + #ComPhy
>> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
>> + # ComPhy0
>> + # 0: PCIE0 5 Gbps
>> + # 1: PCIE0 5 Gbps
>> + # 2: PCIE0 5 Gbps
>> + # 3: PCIE0 5 Gbps
>> + # 4: SFI 10.31 Gbps
>> + # 5: SATA1 5 Gbps
>> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
>> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
>> + # ComPhy1
>> + # 0: SGMII1 1.25 Gbps
>> + # 1: SATA0 5 Gbps
>> + # 2: USB3_HOST0 5 Gbps
>> + # 3: SATA1 5 Gbps
>> + # 4: SFI 10.31 Gbps
>> + # 5: SGMII2 3.125 Gbps
>> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
>> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
>> +
>> + #UtmiPhy
>> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
>> +
>> + #MDIO
>> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
>> +
>> + #PHY
>> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
>> +
>> + #NET
>> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
>> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
>> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
>> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
>> +
>> + #PciEmulation
>> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>> +
>> + #RTC
>> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:06 ` [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin Marcin Wojtas
2018-06-12 14:11 ` Ard Biesheuvel
@ 2018-06-12 14:23 ` Leif Lindholm
2018-06-12 14:27 ` Ard Biesheuvel
1 sibling, 1 reply; 11+ messages in thread
From: Leif Lindholm @ 2018-06-12 14:23 UTC (permalink / raw)
To: Marcin Wojtas; +Cc: edk2-devel, ard.biesheuvel, nadavh, jinghua, jsd, jaz
I have only bikeshedding-level comments on this set, inline below.
(Applies to at lest 2-3.)
On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote:
> Add new board description file Armada80x0McBin.dsc,
> which uses common Armada7k8k.fdf file. By default
> build capsule components.
> Most of the interfaces are fully functional, except for:
> - USB ports - it requires merging GPIO support and VBUS
> power supply enabling
> - SdMmc ports - they are kept enabled, as no issues were
> observed on v1.3 board so far. However higher speed modes
> (HS200) and full stability will be gained after Xenon
> driver improvements merge.
>
> Contributed-under: TianoCore Contribution Agreement 1.1
> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> ---
> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
> 1 file changed, 149 insertions(+)
> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>
> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> new file mode 100644
> index 0000000..1a811d5
> --- /dev/null
> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> @@ -0,0 +1,149 @@
> +#Copyright (C) 2017 Marvell International Ltd.
> +#
> +#Marvell BSD License Option
> +#
> +#If you received this File from Marvell, you may opt to use, redistribute and/or
> +#modify this File under the following licensing terms.
> +#Redistribution and use in source and binary forms, with or without modification,
> +#are permitted provided that the following conditions are met:
> +#
> +# * Redistributions of source code must retain the above copyright notice,
> +# this list of conditions and the following disclaimer.
> +#
> +# * Redistributions in binary form must reproduce the above copyright
> +# notice, this list of conditions and the following disclaimer in the
> +# documentation and/or other materials provided with the distribution.
> +#
> +# * Neither the name of Marvell nor the names of its contributors may be
> +# used to endorse or promote products derived from this software without
> +# specific prior written permission.
> +#
> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> +#
> +################################################################################
> +#
> +# Defines Section - statements that will be processed to create a Makefile.
> +#
> +################################################################################
> +[Defines]
> + PLATFORM_NAME = Armada80x0McBin
> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
> + PLATFORM_VERSION = 0.1
> + DSC_SPECIFICATION = 0x00010019
Can be stepped to ...001A now.
> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
> + BUILD_TARGETS = DEBUG|RELEASE
Question for Ard as much as anything else - should we start
considering NOOPT to be something we want enabled in newly added
platforms?
/
Leif
> + SKUID_IDENTIFIER = DEFAULT
> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
> + CAPSULE_ENABLE = TRUE
> +
> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> +
> +################################################################################
> +#
> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> +#
> +################################################################################
> +[PcdsFixedAtBuild.common]
> + #MPP
> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
> +
> + # APN806-A0 MPP SET
> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
> +
> + # CP110 MPP SET - master
> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> +
> + # CP110 MPP SET - slave
> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> +
> + #SPI
> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
> +
> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
> +
> + #ComPhy
> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
> + # ComPhy0
> + # 0: PCIE0 5 Gbps
> + # 1: PCIE0 5 Gbps
> + # 2: PCIE0 5 Gbps
> + # 3: PCIE0 5 Gbps
> + # 4: SFI 10.31 Gbps
> + # 5: SATA1 5 Gbps
> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
> + # ComPhy1
> + # 0: SGMII1 1.25 Gbps
> + # 1: SATA0 5 Gbps
> + # 2: USB3_HOST0 5 Gbps
> + # 3: SATA1 5 Gbps
> + # 4: SFI 10.31 Gbps
> + # 5: SGMII2 3.125 Gbps
> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
> +
> + #UtmiPhy
> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> +
> + #MDIO
> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
> +
> + #PHY
> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> +
> + #NET
> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
> +
> + #PciEmulation
> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
> +
> + #RTC
> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:23 ` Leif Lindholm
@ 2018-06-12 14:27 ` Ard Biesheuvel
2018-06-12 14:33 ` Marcin Wojtas
2018-06-12 14:33 ` Leif Lindholm
0 siblings, 2 replies; 11+ messages in thread
From: Ard Biesheuvel @ 2018-06-12 14:27 UTC (permalink / raw)
To: Leif Lindholm
Cc: Marcin Wojtas, edk2-devel@lists.01.org, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
On 12 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> I have only bikeshedding-level comments on this set, inline below.
> (Applies to at lest 2-3.)
>
> On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote:
>> Add new board description file Armada80x0McBin.dsc,
>> which uses common Armada7k8k.fdf file. By default
>> build capsule components.
>> Most of the interfaces are fully functional, except for:
>> - USB ports - it requires merging GPIO support and VBUS
>> power supply enabling
>> - SdMmc ports - they are kept enabled, as no issues were
>> observed on v1.3 board so far. However higher speed modes
>> (HS200) and full stability will be gained after Xenon
>> driver improvements merge.
>>
>> Contributed-under: TianoCore Contribution Agreement 1.1
>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> ---
>> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
>> 1 file changed, 149 insertions(+)
>> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>>
>> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> new file mode 100644
>> index 0000000..1a811d5
>> --- /dev/null
>> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> @@ -0,0 +1,149 @@
>> +#Copyright (C) 2017 Marvell International Ltd.
>> +#
>> +#Marvell BSD License Option
>> +#
>> +#If you received this File from Marvell, you may opt to use, redistribute and/or
>> +#modify this File under the following licensing terms.
>> +#Redistribution and use in source and binary forms, with or without modification,
>> +#are permitted provided that the following conditions are met:
>> +#
>> +# * Redistributions of source code must retain the above copyright notice,
>> +# this list of conditions and the following disclaimer.
>> +#
>> +# * Redistributions in binary form must reproduce the above copyright
>> +# notice, this list of conditions and the following disclaimer in the
>> +# documentation and/or other materials provided with the distribution.
>> +#
>> +# * Neither the name of Marvell nor the names of its contributors may be
>> +# used to endorse or promote products derived from this software without
>> +# specific prior written permission.
>> +#
>> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
>> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
>> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
>> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
>> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
>> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
>> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> +#
>> +################################################################################
>> +#
>> +# Defines Section - statements that will be processed to create a Makefile.
>> +#
>> +################################################################################
>> +[Defines]
>> + PLATFORM_NAME = Armada80x0McBin
>> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
>> + PLATFORM_VERSION = 0.1
>> + DSC_SPECIFICATION = 0x00010019
>
> Can be stepped to ...001A now.
>
>> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
>> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
>> + BUILD_TARGETS = DEBUG|RELEASE
>
> Question for Ard as much as anything else - should we start
> considering NOOPT to be something we want enabled in newly added
> platforms?
>
Yes please. It is mainly useful when you have JTAG support so you can
single step through the code, but there is no reason anymore to leave
it out.
>> + SKUID_IDENTIFIER = DEFAULT
>> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
>> + CAPSULE_ENABLE = TRUE
>> +
>> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
>> +
>> +################################################################################
>> +#
>> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
>> +#
>> +################################################################################
>> +[PcdsFixedAtBuild.common]
>> + #MPP
>> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
>> +
>> + # APN806-A0 MPP SET
>> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
>> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
>> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
>> +
>> + # CP110 MPP SET - master
>> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
>> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
>> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> +
>> + # CP110 MPP SET - slave
>> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
>> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
>> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> +
>> + #SPI
>> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
>> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
>> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
>> +
>> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
>> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
>> +
>> + #ComPhy
>> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
>> + # ComPhy0
>> + # 0: PCIE0 5 Gbps
>> + # 1: PCIE0 5 Gbps
>> + # 2: PCIE0 5 Gbps
>> + # 3: PCIE0 5 Gbps
>> + # 4: SFI 10.31 Gbps
>> + # 5: SATA1 5 Gbps
>> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
>> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
>> + # ComPhy1
>> + # 0: SGMII1 1.25 Gbps
>> + # 1: SATA0 5 Gbps
>> + # 2: USB3_HOST0 5 Gbps
>> + # 3: SATA1 5 Gbps
>> + # 4: SFI 10.31 Gbps
>> + # 5: SGMII2 3.125 Gbps
>> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
>> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
>> +
>> + #UtmiPhy
>> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
>> +
>> + #MDIO
>> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
>> +
>> + #PHY
>> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
>> +
>> + #NET
>> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
>> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
>> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
>> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
>> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
>> +
>> + #PciEmulation
>> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
>> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
>> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>> +
>> + #RTC
>> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
>> --
>> 2.7.4
>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:27 ` Ard Biesheuvel
@ 2018-06-12 14:33 ` Marcin Wojtas
2018-06-12 14:33 ` Leif Lindholm
1 sibling, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:33 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Leif Lindholm, edk2-devel@lists.01.org, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
2018-06-12 16:27 GMT+02:00 Ard Biesheuvel <ard.biesheuvel@linaro.org>:
> On 12 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>> I have only bikeshedding-level comments on this set, inline below.
>> (Applies to at lest 2-3.)
>>
>> On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote:
>>> Add new board description file Armada80x0McBin.dsc,
>>> which uses common Armada7k8k.fdf file. By default
>>> build capsule components.
>>> Most of the interfaces are fully functional, except for:
>>> - USB ports - it requires merging GPIO support and VBUS
>>> power supply enabling
>>> - SdMmc ports - they are kept enabled, as no issues were
>>> observed on v1.3 board so far. However higher speed modes
>>> (HS200) and full stability will be gained after Xenon
>>> driver improvements merge.
>>>
>>> Contributed-under: TianoCore Contribution Agreement 1.1
>>> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>>> ---
>>> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
>>> 1 file changed, 149 insertions(+)
>>> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>>>
>>> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>>> new file mode 100644
>>> index 0000000..1a811d5
>>> --- /dev/null
>>> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>>> @@ -0,0 +1,149 @@
>>> +#Copyright (C) 2017 Marvell International Ltd.
>>> +#
>>> +#Marvell BSD License Option
>>> +#
>>> +#If you received this File from Marvell, you may opt to use, redistribute and/or
>>> +#modify this File under the following licensing terms.
>>> +#Redistribution and use in source and binary forms, with or without modification,
>>> +#are permitted provided that the following conditions are met:
>>> +#
>>> +# * Redistributions of source code must retain the above copyright notice,
>>> +# this list of conditions and the following disclaimer.
>>> +#
>>> +# * Redistributions in binary form must reproduce the above copyright
>>> +# notice, this list of conditions and the following disclaimer in the
>>> +# documentation and/or other materials provided with the distribution.
>>> +#
>>> +# * Neither the name of Marvell nor the names of its contributors may be
>>> +# used to endorse or promote products derived from this software without
>>> +# specific prior written permission.
>>> +#
>>> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
>>> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>>> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
>>> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
>>> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
>>> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
>>> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
>>> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>>> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>>> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>>> +#
>>> +################################################################################
>>> +#
>>> +# Defines Section - statements that will be processed to create a Makefile.
>>> +#
>>> +################################################################################
>>> +[Defines]
>>> + PLATFORM_NAME = Armada80x0McBin
>>> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
>>> + PLATFORM_VERSION = 0.1
>>> + DSC_SPECIFICATION = 0x00010019
>>
>> Can be stepped to ...001A now.
Of course, will change.
>>
>>> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
>>> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
>>> + BUILD_TARGETS = DEBUG|RELEASE
>>
>> Question for Ard as much as anything else - should we start
>> considering NOOPT to be something we want enabled in newly added
>> platforms?
>>
>
> Yes please. It is mainly useful when you have JTAG support so you can
> single step through the code, but there is no reason anymore to leave
> it out.
Will add NOOPT then.
Thanks,
Marcin
>
>
>>> + SKUID_IDENTIFIER = DEFAULT
>>> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
>>> + CAPSULE_ENABLE = TRUE
>>> +
>>> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
>>> +
>>> +################################################################################
>>> +#
>>> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
>>> +#
>>> +################################################################################
>>> +[PcdsFixedAtBuild.common]
>>> + #MPP
>>> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
>>> +
>>> + # APN806-A0 MPP SET
>>> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
>>> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
>>> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
>>> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
>>> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
>>> +
>>> + # CP110 MPP SET - master
>>> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
>>> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
>>> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
>>> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>>> +
>>> + # CP110 MPP SET - slave
>>> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
>>> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
>>> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>>> +
>>> + #SPI
>>> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
>>> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
>>> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
>>> +
>>> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
>>> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
>>> +
>>> + #ComPhy
>>> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
>>> + # ComPhy0
>>> + # 0: PCIE0 5 Gbps
>>> + # 1: PCIE0 5 Gbps
>>> + # 2: PCIE0 5 Gbps
>>> + # 3: PCIE0 5 Gbps
>>> + # 4: SFI 10.31 Gbps
>>> + # 5: SATA1 5 Gbps
>>> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
>>> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
>>> + # ComPhy1
>>> + # 0: SGMII1 1.25 Gbps
>>> + # 1: SATA0 5 Gbps
>>> + # 2: USB3_HOST0 5 Gbps
>>> + # 3: SATA1 5 Gbps
>>> + # 4: SFI 10.31 Gbps
>>> + # 5: SGMII2 3.125 Gbps
>>> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
>>> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
>>> +
>>> + #UtmiPhy
>>> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
>>> +
>>> + #MDIO
>>> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
>>> +
>>> + #PHY
>>> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
>>> +
>>> + #NET
>>> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
>>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
>>> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
>>> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
>>> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
>>> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
>>> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
>>> +
>>> + #PciEmulation
>>> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
>>> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
>>> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>>> +
>>> + #RTC
>>> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
>>> --
>>> 2.7.4
>>>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:27 ` Ard Biesheuvel
2018-06-12 14:33 ` Marcin Wojtas
@ 2018-06-12 14:33 ` Leif Lindholm
2018-06-12 14:36 ` Marcin Wojtas
1 sibling, 1 reply; 11+ messages in thread
From: Leif Lindholm @ 2018-06-12 14:33 UTC (permalink / raw)
To: Ard Biesheuvel
Cc: Marcin Wojtas, edk2-devel@lists.01.org, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
On Tue, Jun 12, 2018 at 04:27:18PM +0200, Ard Biesheuvel wrote:
> On 12 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
> > I have only bikeshedding-level comments on this set, inline below.
> > (Applies to at lest 2-3.)
> >
> > On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote:
> >> Add new board description file Armada80x0McBin.dsc,
> >> which uses common Armada7k8k.fdf file. By default
> >> build capsule components.
> >> Most of the interfaces are fully functional, except for:
> >> - USB ports - it requires merging GPIO support and VBUS
> >> power supply enabling
> >> - SdMmc ports - they are kept enabled, as no issues were
> >> observed on v1.3 board so far. However higher speed modes
> >> (HS200) and full stability will be gained after Xenon
> >> driver improvements merge.
> >>
> >> Contributed-under: TianoCore Contribution Agreement 1.1
> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
> >> ---
> >> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
> >> 1 file changed, 149 insertions(+)
> >> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> >>
> >> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> >> new file mode 100644
> >> index 0000000..1a811d5
> >> --- /dev/null
> >> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
> >> @@ -0,0 +1,149 @@
> >> +#Copyright (C) 2017 Marvell International Ltd.
> >> +#
> >> +#Marvell BSD License Option
> >> +#
> >> +#If you received this File from Marvell, you may opt to use, redistribute and/or
> >> +#modify this File under the following licensing terms.
> >> +#Redistribution and use in source and binary forms, with or without modification,
> >> +#are permitted provided that the following conditions are met:
> >> +#
> >> +# * Redistributions of source code must retain the above copyright notice,
> >> +# this list of conditions and the following disclaimer.
> >> +#
> >> +# * Redistributions in binary form must reproduce the above copyright
> >> +# notice, this list of conditions and the following disclaimer in the
> >> +# documentation and/or other materials provided with the distribution.
> >> +#
> >> +# * Neither the name of Marvell nor the names of its contributors may be
> >> +# used to endorse or promote products derived from this software without
> >> +# specific prior written permission.
> >> +#
> >> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
> >> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
> >> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
> >> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
> >> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
> >> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
> >> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
> >> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
> >> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
> >> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
> >> +#
> >> +################################################################################
> >> +#
> >> +# Defines Section - statements that will be processed to create a Makefile.
> >> +#
> >> +################################################################################
> >> +[Defines]
> >> + PLATFORM_NAME = Armada80x0McBin
> >> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
> >> + PLATFORM_VERSION = 0.1
> >> + DSC_SPECIFICATION = 0x00010019
> >
> > Can be stepped to ...001A now.
> >
> >> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
> >> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
> >> + BUILD_TARGETS = DEBUG|RELEASE
> >
> > Question for Ard as much as anything else - should we start
> > considering NOOPT to be something we want enabled in newly added
> > platforms?
> >
>
> Yes please. It is mainly useful when you have JTAG support so you can
> single step through the code, but there is no reason anymore to leave
> it out.
Yeah, that's what I figured.
In that case - Marcin: can you please add NOOPT to the new platforms,
and put a separate new patch (1/4?) to add it for the existing Armada?
/
Leif
> >> + SKUID_IDENTIFIER = DEFAULT
> >> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
> >> + CAPSULE_ENABLE = TRUE
> >> +
> >> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
> >> +
> >> +################################################################################
> >> +#
> >> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
> >> +#
> >> +################################################################################
> >> +[PcdsFixedAtBuild.common]
> >> + #MPP
> >> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
> >> +
> >> + # APN806-A0 MPP SET
> >> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
> >> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
> >> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
> >> +
> >> + # CP110 MPP SET - master
> >> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
> >> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
> >> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> >> +
> >> + # CP110 MPP SET - slave
> >> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
> >> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
> >> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
> >> +
> >> + #SPI
> >> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
> >> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
> >> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
> >> +
> >> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
> >> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
> >> +
> >> + #ComPhy
> >> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
> >> + # ComPhy0
> >> + # 0: PCIE0 5 Gbps
> >> + # 1: PCIE0 5 Gbps
> >> + # 2: PCIE0 5 Gbps
> >> + # 3: PCIE0 5 Gbps
> >> + # 4: SFI 10.31 Gbps
> >> + # 5: SATA1 5 Gbps
> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
> >> + # ComPhy1
> >> + # 0: SGMII1 1.25 Gbps
> >> + # 1: SATA0 5 Gbps
> >> + # 2: USB3_HOST0 5 Gbps
> >> + # 3: SATA1 5 Gbps
> >> + # 4: SFI 10.31 Gbps
> >> + # 5: SGMII2 3.125 Gbps
> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
> >> +
> >> + #UtmiPhy
> >> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
> >> +
> >> + #MDIO
> >> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
> >> +
> >> + #PHY
> >> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
> >> +
> >> + #NET
> >> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
> >> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
> >> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
> >> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
> >> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
> >> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
> >> +
> >> + #PciEmulation
> >> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
> >> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
> >> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
> >> +
> >> + #RTC
> >> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
> >> --
> >> 2.7.4
> >>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin
2018-06-12 14:33 ` Leif Lindholm
@ 2018-06-12 14:36 ` Marcin Wojtas
0 siblings, 0 replies; 11+ messages in thread
From: Marcin Wojtas @ 2018-06-12 14:36 UTC (permalink / raw)
To: Leif Lindholm
Cc: Ard Biesheuvel, edk2-devel@lists.01.org, Nadav Haklai, Hua Jing,
Jan Dąbroś, Grzegorz Jaszczyk
2018-06-12 16:33 GMT+02:00 Leif Lindholm <leif.lindholm@linaro.org>:
> On Tue, Jun 12, 2018 at 04:27:18PM +0200, Ard Biesheuvel wrote:
>> On 12 June 2018 at 16:23, Leif Lindholm <leif.lindholm@linaro.org> wrote:
>> > I have only bikeshedding-level comments on this set, inline below.
>> > (Applies to at lest 2-3.)
>> >
>> > On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote:
>> >> Add new board description file Armada80x0McBin.dsc,
>> >> which uses common Armada7k8k.fdf file. By default
>> >> build capsule components.
>> >> Most of the interfaces are fully functional, except for:
>> >> - USB ports - it requires merging GPIO support and VBUS
>> >> power supply enabling
>> >> - SdMmc ports - they are kept enabled, as no issues were
>> >> observed on v1.3 board so far. However higher speed modes
>> >> (HS200) and full stability will be gained after Xenon
>> >> driver improvements merge.
>> >>
>> >> Contributed-under: TianoCore Contribution Agreement 1.1
>> >> Signed-off-by: Marcin Wojtas <mw@semihalf.com>
>> >> ---
>> >> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++
>> >> 1 file changed, 149 insertions(+)
>> >> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> >>
>> >> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> >> new file mode 100644
>> >> index 0000000..1a811d5
>> >> --- /dev/null
>> >> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc
>> >> @@ -0,0 +1,149 @@
>> >> +#Copyright (C) 2017 Marvell International Ltd.
>> >> +#
>> >> +#Marvell BSD License Option
>> >> +#
>> >> +#If you received this File from Marvell, you may opt to use, redistribute and/or
>> >> +#modify this File under the following licensing terms.
>> >> +#Redistribution and use in source and binary forms, with or without modification,
>> >> +#are permitted provided that the following conditions are met:
>> >> +#
>> >> +# * Redistributions of source code must retain the above copyright notice,
>> >> +# this list of conditions and the following disclaimer.
>> >> +#
>> >> +# * Redistributions in binary form must reproduce the above copyright
>> >> +# notice, this list of conditions and the following disclaimer in the
>> >> +# documentation and/or other materials provided with the distribution.
>> >> +#
>> >> +# * Neither the name of Marvell nor the names of its contributors may be
>> >> +# used to endorse or promote products derived from this software without
>> >> +# specific prior written permission.
>> >> +#
>> >> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
>> >> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
>> >> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
>> >> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
>> >> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
>> >> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
>> >> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
>> >> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
>> >> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
>> >> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
>> >> +#
>> >> +################################################################################
>> >> +#
>> >> +# Defines Section - statements that will be processed to create a Makefile.
>> >> +#
>> >> +################################################################################
>> >> +[Defines]
>> >> + PLATFORM_NAME = Armada80x0McBin
>> >> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62
>> >> + PLATFORM_VERSION = 0.1
>> >> + DSC_SPECIFICATION = 0x00010019
>> >
>> > Can be stepped to ...001A now.
>> >
>> >> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH)
>> >> + SUPPORTED_ARCHITECTURES = AARCH64|ARM
>> >> + BUILD_TARGETS = DEBUG|RELEASE
>> >
>> > Question for Ard as much as anything else - should we start
>> > considering NOOPT to be something we want enabled in newly added
>> > platforms?
>> >
>>
>> Yes please. It is mainly useful when you have JTAG support so you can
>> single step through the code, but there is no reason anymore to leave
>> it out.
>
> Yeah, that's what I figured.
>
> In that case - Marcin: can you please add NOOPT to the new platforms,
> and put a separate new patch (1/4?) to add it for the existing Armada?
>
Sure!
Marcin
>
>> >> + SKUID_IDENTIFIER = DEFAULT
>> >> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf
>> >> + CAPSULE_ENABLE = TRUE
>> >> +
>> >> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
>> >> +
>> >> +################################################################################
>> >> +#
>> >> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform
>> >> +#
>> >> +################################################################################
>> >> +[PcdsFixedAtBuild.common]
>> >> + #MPP
>> >> + gMarvellTokenSpaceGuid.PcdMppChipCount|3
>> >> +
>> >> + # APN806-A0 MPP SET
>> >> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE
>> >> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000
>> >> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20
>> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 }
>> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 }
>> >> +
>> >> + # CP110 MPP SET - master
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE }
>> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> >> +
>> >> + # CP110 MPP SET - slave
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 }
>> >> +
>> >> + #SPI
>> >> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680
>> >> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000
>> >> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000
>> >> +
>> >> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3
>> >> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0
>> >> +
>> >> + #ComPhy
>> >> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }
>> >> + # ComPhy0
>> >> + # 0: PCIE0 5 Gbps
>> >> + # 1: PCIE0 5 Gbps
>> >> + # 2: PCIE0 5 Gbps
>> >> + # 3: PCIE0 5 Gbps
>> >> + # 4: SFI 10.31 Gbps
>> >> + # 5: SATA1 5 Gbps
>> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)}
>> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) }
>> >> + # ComPhy1
>> >> + # 0: SGMII1 1.25 Gbps
>> >> + # 1: SATA0 5 Gbps
>> >> + # 2: USB3_HOST0 5 Gbps
>> >> + # 3: SATA1 5 Gbps
>> >> + # 4: SFI 10.31 Gbps
>> >> + # 5: SGMII2 3.125 Gbps
>> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) }
>> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }
>> >> +
>> >> + #UtmiPhy
>> >> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }
>> >> +
>> >> + #MDIO
>> >> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 }
>> >> +
>> >> + #PHY
>> >> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE
>> >> +
>> >> + #NET
>> >> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 }
>> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) }
>> >> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) }
>> >> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF }
>> >> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 }
>> >> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 }
>> >> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }
>> >> +
>> >> + #PciEmulation
>> >> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 }
>> >> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 }
>> >> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }
>> >> +
>> >> + #RTC
>> >> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 }
>> >> --
>> >> 2.7.4
>> >>
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-06-12 14:36 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-06-12 14:06 [platforms: PATCH 0/3] Armada7k8k new boards support Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 1/3] Marvell/Armada7k8k: Use common .fdf file Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin Marcin Wojtas
2018-06-12 14:11 ` Ard Biesheuvel
2018-06-12 14:15 ` Marcin Wojtas
2018-06-12 14:23 ` Leif Lindholm
2018-06-12 14:27 ` Ard Biesheuvel
2018-06-12 14:33 ` Marcin Wojtas
2018-06-12 14:33 ` Leif Lindholm
2018-06-12 14:36 ` Marcin Wojtas
2018-06-12 14:06 ` [platforms: PATCH 3/3] Marvell/Armada7k8k: Introduce support for Armada-8040-Db Marcin Wojtas
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