From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c06::244; helo=mail-io0-x244.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io0-x244.google.com (mail-io0-x244.google.com [IPv6:2607:f8b0:4001:c06::244]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 506DB211CF343 for ; Tue, 12 Jun 2018 07:36:54 -0700 (PDT) Received: by mail-io0-x244.google.com with SMTP id t6-v6so28281711iob.10 for ; Tue, 12 Jun 2018 07:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=0AYGovgiWSzTV4YcMxSo+5mtcNdMtBOLgYnw1spJ2vk=; b=AQmFISxthtWM3X3BJx8tuG5GjBeM4BE44WbYrsu4cO7b/pQZeEnnBrzeZf09AUy+4A JzhNVbXf5G2bxzRbw+5CR46dvpHXTJrmDLFYeOBP+Ei7SktEZTfXDARSennnB35jcTMn SmqRoaIFonTlJK+gyRDJuDyfSHLETlZ0sKUphbUSfVT7zW7bMoh5UStpaAP8eYYZhbie N5QkHHayY28eHi0xbly+E+vn8vkfVRMyBRR5V/gnDfWrcWBpGsbI08aEOXfV0vq/IBc7 VEJGveaMF0wOcPk4NY9ncjcHmNH64Fhli3ERGWuuBk0vbSGPa4HFxEtvcJAOACubuZ6e DcvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=0AYGovgiWSzTV4YcMxSo+5mtcNdMtBOLgYnw1spJ2vk=; b=NTprIUql9oqCzD6sG18/MH2GINKiFFKgkFeH5EbHe7ad4JrkaF9JHOadnYJKZ8jwVJ iQnGOsovCrte64b4ugaqGGTkF0tjQ25j4W65KzIDdfA6tEUM0cuh1MsXuc3mRKN//Blw jcgig2FuCxm6xT8tGX7CWbnVmcJmdNrP7kE6DCXgNjtK/GyckzyMkkUK7t+HSiD727B5 lO1zjVLCBhyNzARBv57Cs7scPvn99ZRMjutXfEQrhjFkCdD0YtYTf+sEtals7rUDBZqu FCHdNzZ/WLjoTtxYFraxb2G5NIUswqWkguuA0GxbF3P84rFV93NKVqqGDdQSxgpvsfqz HCTA== X-Gm-Message-State: APt69E2pAZjKmrH484IM+oXbcyHUFObBM/4Mq3IUxOAfVr2kwthdLakq 3Lwl9VxWyNsRGF7PlqvO/8YJGDnUnTE6uzMQnqQkfA== X-Google-Smtp-Source: ADUXVKL+SSdaA08R0HaR2S4hkOkpIHoRWBIekEdpifXnVTN9Zt+T8XZWiDDNkO9V5H/wS710uhCAIPm1Tru2nZL3MLw= X-Received: by 2002:a6b:9403:: with SMTP id w3-v6mr774387iod.108.1528814213514; Tue, 12 Jun 2018 07:36:53 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:c6cc:0:0:0:0:0 with HTTP; Tue, 12 Jun 2018 07:36:53 -0700 (PDT) In-Reply-To: <20180612143340.76redxoaz7ks2xi3@bivouac.eciton.net> References: <1528812395-2716-1-git-send-email-mw@semihalf.com> <1528812395-2716-3-git-send-email-mw@semihalf.com> <20180612142349.jjf26c73suspq6jc@bivouac.eciton.net> <20180612143340.76redxoaz7ks2xi3@bivouac.eciton.net> From: Marcin Wojtas Date: Tue, 12 Jun 2018 16:36:53 +0200 Message-ID: To: Leif Lindholm Cc: Ard Biesheuvel , "edk2-devel@lists.01.org" , Nadav Haklai , Hua Jing , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk Subject: Re: [platforms: PATCH 2/3] Marvell/Armada7k8k: Introduce support for Armada-8040-McBin X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.26 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 12 Jun 2018 14:36:54 -0000 Content-Type: text/plain; charset="UTF-8" 2018-06-12 16:33 GMT+02:00 Leif Lindholm : > On Tue, Jun 12, 2018 at 04:27:18PM +0200, Ard Biesheuvel wrote: >> On 12 June 2018 at 16:23, Leif Lindholm wrote: >> > I have only bikeshedding-level comments on this set, inline below. >> > (Applies to at lest 2-3.) >> > >> > On Tue, Jun 12, 2018 at 04:06:34PM +0200, Marcin Wojtas wrote: >> >> Add new board description file Armada80x0McBin.dsc, >> >> which uses common Armada7k8k.fdf file. By default >> >> build capsule components. >> >> Most of the interfaces are fully functional, except for: >> >> - USB ports - it requires merging GPIO support and VBUS >> >> power supply enabling >> >> - SdMmc ports - they are kept enabled, as no issues were >> >> observed on v1.3 board so far. However higher speed modes >> >> (HS200) and full stability will be gained after Xenon >> >> driver improvements merge. >> >> >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> >> Signed-off-by: Marcin Wojtas >> >> --- >> >> Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc | 149 ++++++++++++++++++++ >> >> 1 file changed, 149 insertions(+) >> >> create mode 100644 Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc >> >> >> >> diff --git a/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc >> >> new file mode 100644 >> >> index 0000000..1a811d5 >> >> --- /dev/null >> >> +++ b/Platform/SolidRun/Armada80x0McBin/Armada80x0McBin.dsc >> >> @@ -0,0 +1,149 @@ >> >> +#Copyright (C) 2017 Marvell International Ltd. >> >> +# >> >> +#Marvell BSD License Option >> >> +# >> >> +#If you received this File from Marvell, you may opt to use, redistribute and/or >> >> +#modify this File under the following licensing terms. >> >> +#Redistribution and use in source and binary forms, with or without modification, >> >> +#are permitted provided that the following conditions are met: >> >> +# >> >> +# * Redistributions of source code must retain the above copyright notice, >> >> +# this list of conditions and the following disclaimer. >> >> +# >> >> +# * Redistributions in binary form must reproduce the above copyright >> >> +# notice, this list of conditions and the following disclaimer in the >> >> +# documentation and/or other materials provided with the distribution. >> >> +# >> >> +# * Neither the name of Marvell nor the names of its contributors may be >> >> +# used to endorse or promote products derived from this software without >> >> +# specific prior written permission. >> >> +# >> >> +#THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND >> >> +#ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED >> >> +#WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE >> >> +#DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR >> >> +#ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES >> >> +#(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; >> >> +#LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON >> >> +#ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT >> >> +#(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS >> >> +#SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. >> >> +# >> >> +################################################################################ >> >> +# >> >> +# Defines Section - statements that will be processed to create a Makefile. >> >> +# >> >> +################################################################################ >> >> +[Defines] >> >> + PLATFORM_NAME = Armada80x0McBin >> >> + PLATFORM_GUID = 256e46dc-bff2-4e83-8ab3-6d2a3bec3f62 >> >> + PLATFORM_VERSION = 0.1 >> >> + DSC_SPECIFICATION = 0x00010019 >> > >> > Can be stepped to ...001A now. >> > >> >> + OUTPUT_DIRECTORY = Build/$(PLATFORM_NAME)-$(ARCH) >> >> + SUPPORTED_ARCHITECTURES = AARCH64|ARM >> >> + BUILD_TARGETS = DEBUG|RELEASE >> > >> > Question for Ard as much as anything else - should we start >> > considering NOOPT to be something we want enabled in newly added >> > platforms? >> > >> >> Yes please. It is mainly useful when you have JTAG support so you can >> single step through the code, but there is no reason anymore to leave >> it out. > > Yeah, that's what I figured. > > In that case - Marcin: can you please add NOOPT to the new platforms, > and put a separate new patch (1/4?) to add it for the existing Armada? > Sure! Marcin > >> >> + SKUID_IDENTIFIER = DEFAULT >> >> + FLASH_DEFINITION = Silicon/Marvell/Armada7k8k/Armada7k8k.fdf >> >> + CAPSULE_ENABLE = TRUE >> >> + >> >> +!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc >> >> + >> >> +################################################################################ >> >> +# >> >> +# Pcd Section - list of all EDK II PCD Entries defined by this Platform >> >> +# >> >> +################################################################################ >> >> +[PcdsFixedAtBuild.common] >> >> + #MPP >> >> + gMarvellTokenSpaceGuid.PcdMppChipCount|3 >> >> + >> >> + # APN806-A0 MPP SET >> >> + gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE >> >> + gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000 >> >> + gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20 >> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0x1 } >> >> + gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x3 } >> >> + >> >> + # CP110 MPP SET - master >> >> + gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE >> >> + gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000 >> >> + gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64 >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0xFF, 0x0, 0x7, 0xA, 0x7, 0x2, 0x2, 0x2, 0x2, 0xA } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x7, 0x7, 0x8, 0x8, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x0, 0x0, 0x9, 0x0, 0x0, 0x0, 0xE, 0xE, 0xE, 0xE } >> >> + gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } >> >> + >> >> + # CP110 MPP SET - slave >> >> + gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE >> >> + gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000 >> >> + gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64 >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x4, 0x4, 0x4, 0x4, 0x4, 0x4, 0x8, 0x8, 0x0, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x3, 0x3, 0x3, 0x3, 0x3, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0x0, 0xFF, 0x0, 0x0, 0x0, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 } >> >> + >> >> + #SPI >> >> + gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF4700680 >> >> + gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000 >> >> + gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000 >> >> + >> >> + gMarvellTokenSpaceGuid.PcdSpiFlashMode|3 >> >> + gMarvellTokenSpaceGuid.PcdSpiFlashCs|0 >> >> + >> >> + #ComPhy >> >> + gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 } >> >> + # ComPhy0 >> >> + # 0: PCIE0 5 Gbps >> >> + # 1: PCIE0 5 Gbps >> >> + # 2: PCIE0 5 Gbps >> >> + # 3: PCIE0 5 Gbps >> >> + # 4: SFI 10.31 Gbps >> >> + # 5: SATA1 5 Gbps >> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SATA1)} >> >> + gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_5G) } >> >> + # ComPhy1 >> >> + # 0: SGMII1 1.25 Gbps >> >> + # 1: SATA0 5 Gbps >> >> + # 2: USB3_HOST0 5 Gbps >> >> + # 3: SATA1 5 Gbps >> >> + # 4: SFI 10.31 Gbps >> >> + # 5: SGMII2 3.125 Gbps >> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_SGMII1), $(CP_SATA2), $(CP_USB3_HOST0), $(CP_SATA3), $(CP_SFI), $(CP_SGMII2) } >> >> + gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_1_25G), $(CP_5G), $(CP_5G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) } >> >> + >> >> + #UtmiPhy >> >> + gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x1, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) } >> >> + >> >> + #MDIO >> >> + gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1, 0x0 } >> >> + >> >> + #PHY >> >> + gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE >> >> + >> >> + #NET >> >> + gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x0, 0x2, 0x3 } >> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x0, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_SPEED_10000), $(PHY_SPEED_1000), $(PHY_SPEED_2500) } >> >> + gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_SFI), $(PHY_SGMII), $(PHY_SGMII) } >> >> + gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0xFF, 0x0, 0xFF } >> >> + gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x1, 0x1, 0x1 } >> >> + gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x0, 0x1, 0x2 } >> >> + gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 } >> >> + >> >> + #PciEmulation >> >> + gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x1, 0x0 } >> >> + gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1, 0x1 } >> >> + gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 } >> >> + >> >> + #RTC >> >> + gMarvellTokenSpaceGuid.PcdRtcEnabled|{ 0x0, 0x1 } >> >> -- >> >> 2.7.4 >> >>