From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f195.google.com (mail-qk1-f195.google.com [209.85.222.195]) by mx.groups.io with SMTP id smtpd.web10.855.1589825522074618440 for ; Mon, 18 May 2020 11:12:02 -0700 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=1y0irdMz; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.195, mailfrom: mw@semihalf.com) Received: by mail-qk1-f195.google.com with SMTP id i5so11136470qkl.12 for ; Mon, 18 May 2020 11:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=dy/sgzh09xLXrAWr6TAFHBJPP8fixPsncGlUJtEFdjM=; b=1y0irdMzwexloBq7pr5HqyDmmQxvX71sa5k9dyR/KTmn2UhYUqzdzRyYhZ1gJVsJ5Q Jd6uFrzGp0iUour19L1mojEDIdpdbCXPJt5FCPdEuNwVuPCD3GxX1W9Gy0jb2xoVDh7H lYSrIK9Ypo91g337m6ScSop3Z+xez2XBdOniRsEvPpo5Xtizn1L/d6Zdmj7mZcOJ5W2v MUIdBFM+KJb7DxKovIyESjcfr564QpViAgHY+Q8LlIUZQ+c6OEgdy3mFUfsq0pXD+G7U l2QzGZ20f60U4Dkf23RBnl2KMtrLu+hRF4vDFMOrPSgSdRGKsR9jTGywzOxIHlvtx6kU v8yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=dy/sgzh09xLXrAWr6TAFHBJPP8fixPsncGlUJtEFdjM=; b=ZY9jlJ4Ep6jl+Cuz6sXA+uiLxqm7X/LtXBo7x9ceTVoaMWkEkocIzrdcijgUcd9Px2 VSTzlcY3R/e6Hy6p5JhVXmqmq60+vckJ0gk6TMqq+OBfy6mEySMM5SN+k+cDGPbzXMEZ wu/IOv7T13YgKKKKgnTVWfKMnyi0LIwlx5p4MsxPUY4xBMcJltvJElJI3KIUc6VGexDS QEgjBSu7Etlr1vTFxzstq97k55zBG9KmOUxNl/GEY+vqSM6k/9Uk1f1QYAmDKiXLfRSd KF09y1ISba07oXD4A8VoB8kH1CuEr+DSy96xcEgCn5/lSAKd2QAOLKkO115OoxsXWUei P/pg== X-Gm-Message-State: AOAM530JYhyhIRMVvKX4+RUv4HQVEpyW9hg+b9izvslcSmnvTZ2CpU0e shzcIgh6iAG9sQUiV1itUKpfo91cmbhSSUxl80Fh3HGt5HE= X-Google-Smtp-Source: ABdhPJyxPsPIOuB2Mop87m0PyVh7RMVKO+XYp2OuThrHrl/QeE7CQXQQUI2enbjA7kYpMWwgmm4rbyBwU4Uv0wu/UPQ= X-Received: by 2002:a37:5804:: with SMTP id m4mr16529391qkb.109.1589825521050; Mon, 18 May 2020 11:12:01 -0700 (PDT) MIME-Version: 1.0 References: <1589576758-28501-1-git-send-email-mw@semihalf.com> <1589576758-28501-2-git-send-email-mw@semihalf.com> <20200518171221.GC10467@vanye> In-Reply-To: <20200518171221.GC10467@vanye> From: "Marcin Wojtas" Date: Mon, 18 May 2020 20:11:49 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v2 1/3] Marvell/Library: UtmiLib: update USB2.0 analog settings To: Leif Lindholm Cc: edk2-devel-groups-io , ard.biesheuvel@arm.com, "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, pon., 18 maj 2020 o 19:12 Leif Lindholm napisa=C5=82(a)= : > > On Fri, May 15, 2020 at 23:05:56 +0200, Marcin Wojtas wrote: > > This patch introduce following modifications, allowing to > > overcome the instabilities observed with certain USB2.0 endpoints: > > * Add additional step which enables the Impedance and PLL calibration. > > * Enable old squelch detector instead of the new analog squelch detecto= r > > circuit and update host disconnect threshold value. > > * Update LS TX driver strength coarse and fine adjustment values. > > > > Signed-off-by: Grzegorz Jaszczyk > > Signed-off-by: Marcin Wojtas > > I'm OK with the current version of the code, but just noticed this. > No one can give Signed-off-by for another. > If Grzegorz is the author, that should be noted in a From: tag. Git > format-patch does this automatically if the commit's Author metadata > is set. > > This applies to all 3 patches. > The 3/3 has only only my signed-off tag (and my authorship). Regarding the first 2, I did the actual change, but it was based on the original U-Boot patch from Grzegorz. How about, instead of the tag, I give him a credit in a following way: Based on the original U-Boot patch from Grzegorz Jaszczyk Would that work for you? Best regards, Marcin > > > --- > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h | 10 +++++++++- > > Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c | 18 ++++++++++++++---= - > > 2 files changed, 23 insertions(+), 5 deletions(-) > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h b/Silicon/= Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > index 20e3133..8659110 100644 > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.h > > @@ -44,6 +44,10 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_CALIB_CTRL_REG 0x8 > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET 8 > > #define UTMI_CALIB_CTRL_IMPCAL_VTH_MASK (0x7 << UTMI_CALIB_C= TRL_IMPCAL_VTH_OFFSET) > > +#define UTMI_CALIB_CTRL_IMPCAL_START_OFFSET 13 > > +#define UTMI_CALIB_CTRL_IMPCAL_START_MASK (0x1 << UTMI_CALIB_C= TRL_IMPCAL_START_OFFSET) > > +#define UTMI_CALIB_CTRL_PLLCAL_START_OFFSET 22 > > +#define UTMI_CALIB_CTRL_PLLCAL_START_MASK (0x1 << UTMI_CALIB_C= TRL_PLLCAL_START_OFFSET) > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_OFFSET 23 > > #define UTMI_CALIB_CTRL_IMPCAL_DONE_MASK (0x1 << UTMI_CALIB_C= TRL_IMPCAL_DONE_OFFSET) > > #define UTMI_CALIB_CTRL_PLLCAL_DONE_OFFSET 31 > > @@ -54,8 +58,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > #define UTMI_TX_CH_CTRL_DRV_EN_LS_MASK (0xf << UTMI_TX_CH_C= TRL_DRV_EN_LS_OFFSET) > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET 16 > > #define UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK (0xf << UTMI_TX_CH_C= TRL_IMP_SEL_LS_OFFSET) > > +#define UTMI_TX_CH_CTRL_AMP_OFFSET 20 > > +#define UTMI_TX_CH_CTRL_AMP_MASK (0x7 << UTMI_TX_CH_C= TRL_AMP_OFFSET) > > > > #define UTMI_RX_CH_CTRL0_REG 0x14 > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET 8 > > +#define UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK (0x3 << UTMI_RX_CH_C= TRL0_DISCON_THRESH_OFFSET) > > #define UTMI_RX_CH_CTRL0_SQ_DET_OFFSET 15 > > #define UTMI_RX_CH_CTRL0_SQ_DET_MASK (0x1 << UTMI_RX_CH_C= TRL0_SQ_DET_OFFSET) > > #define UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET 28 > > @@ -63,7 +71,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent > > > > #define UTMI_RX_CH_CTRL1_REG 0x18 > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_OFFSET 0 > > -#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x3 << UTMI_RX_CH_C= TRL1_SQ_AMP_CAL_OFFSET) > > +#define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_MASK (0x7 << UTMI_RX_CH_C= TRL1_SQ_AMP_CAL_OFFSET) > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_OFFSET 3 > > #define UTMI_RX_CH_CTRL1_SQ_AMP_CAL_EN_MASK (0x1 << UTMI_RX_CH_C= TRL1_SQ_AMP_CAL_EN_OFFSET) > > > > diff --git a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c b/Silicon/= Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > index 3881ebd..42f38db 100644 > > --- a/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > +++ b/Silicon/Marvell/Library/UtmiPhyLib/UtmiPhyLib.c > > @@ -118,23 +118,33 @@ UtmiPhyConfig ( > > > > /* Impedance Calibration Threshold Setting */ > > RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, > > - 0x6 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > + 0x7 << UTMI_CALIB_CTRL_IMPCAL_VTH_OFFSET, > > UTMI_CALIB_CTRL_IMPCAL_VTH_MASK); > > > > + /* Start Impedance and PLL Calibration */ > > + Mask =3D UTMI_CALIB_CTRL_PLLCAL_START_MASK; > > + Data =3D (0x1 << UTMI_CALIB_CTRL_PLLCAL_START_OFFSET); > > + Mask |=3D UTMI_CALIB_CTRL_IMPCAL_START_MASK; > > + Data |=3D (0x1 << UTMI_CALIB_CTRL_IMPCAL_START_OFFSET); > > + RegSet (UtmiBaseAddr + UTMI_CALIB_CTRL_REG, Data, Mask); > > + > > /* Set LS TX driver strength coarse control */ > > Mask =3D UTMI_TX_CH_CTRL_DRV_EN_LS_MASK; > > Data =3D 0x3 << UTMI_TX_CH_CTRL_DRV_EN_LS_OFFSET; > > - /* Set LS TX driver fine adjustment */ > > + Mask |=3D UTMI_TX_CH_CTRL_AMP_MASK; > > + Data |=3D 0x4 << UTMI_TX_CH_CTRL_AMP_OFFSET; > > Mask |=3D UTMI_TX_CH_CTRL_IMP_SEL_LS_MASK; > > Data |=3D 0x3 << UTMI_TX_CH_CTRL_IMP_SEL_LS_OFFSET; > > RegSet (UtmiBaseAddr + UTMI_TX_CH_CTRL_REG, Data, Mask); > > > > /* Enable SQ */ > > Mask =3D UTMI_RX_CH_CTRL0_SQ_DET_MASK; > > - Data =3D 0x0 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > + Data =3D 0x1 << UTMI_RX_CH_CTRL0_SQ_DET_OFFSET; > > /* Enable analog squelch detect */ > > Mask |=3D UTMI_RX_CH_CTRL0_SQ_ANA_DTC_MASK; > > - Data |=3D 0x1 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > + Data |=3D 0x0 << UTMI_RX_CH_CTRL0_SQ_ANA_DTC_OFFSET; > > + Mask |=3D UTMI_RX_CH_CTRL0_DISCON_THRESH_MASK; > > + Data |=3D 0x0 << UTMI_RX_CH_CTRL0_DISCON_THRESH_OFFSET; > > RegSet (UtmiBaseAddr + UTMI_RX_CH_CTRL0_REG, Data, Mask); > > > > /* Set External squelch calibration number */ > > -- > > 2.7.4 > >