From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=wCwxP69y; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.160.195, mailfrom: mw@semihalf.com) Received: from mail-qt1-f195.google.com (mail-qt1-f195.google.com [209.85.160.195]) by groups.io with SMTP; Thu, 26 Sep 2019 00:25:09 -0700 Received: by mail-qt1-f195.google.com with SMTP id c3so1591348qtv.10 for ; Thu, 26 Sep 2019 00:25:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vN9jdnBRit5+gQ1fwA+jKyDYkmyhHICC39ylK9t6OY8=; b=wCwxP69yvnkkN70POAlIEfkFjfUzTD2PfdHIZdsvDHwTA6BFwufV33yC6od7OAUu12 dGboYKLgsUnQgXVcmBBD1zvRamvphU3V3fdXWxUktxxgGMOe1vqSRNTD+g1ToaFYRt0Q 60cg4TVQkQuu0EQ0KfNBIOsJx5zBqSKpiksIU5GtZpnVMSYPjQ+p7yt2+0L23NLFiRvX qQMyG+e493BBI0lICIV9oED+kAlB4AWm9/mx+B4fnytV3tHw1y5XvioVXu7r5nf5++fo 0vMxsv8bZ/BQ+nQiwbfdQYMzuR38WCT7HdQSsuce3tMAAVq3x4M3qQv8mp2mky7TAPJe tTHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vN9jdnBRit5+gQ1fwA+jKyDYkmyhHICC39ylK9t6OY8=; b=U2uTVBnXS7c292pbFUUYXjvyaVDC9u3x4rv2u1ruUTw8N6PEq0siIaSL7Ij1QjypWy hHsBk979TDDa2Zg6tbCJiAfNugvQYA5cO8ekXZ/uc2WQe0/1gkm6Qe6GWoaT0R8XfYSs Jb/2VfO++cvWAqbA8cnIfNlmo8C4g6o6KgovOw46JMs/ffWP+9zFirqJV7Jc1UivbOVs I0kEG/z3yopENgy21QAtQQMJgJPC0UB5jTL6UTvWf19z+fgjGAG6N5ZJPUOsbQ93Q/kS yU4cRSRet5fNuEL7AFSMyYdXTFHR9pM9fMTq1XAK2jBWlM3Ai1I4L6mF2VT/58N6dP/t wYgg== X-Gm-Message-State: APjAAAVJ4ZE8lw4pYKqOxXqyPraARg7hfsqzO0FI5cC5ljFanOhmmDWe 8OXSq/BG9LUGEo6L3nZVcvqjGoMRERB0E52O/VmgoQ== X-Google-Smtp-Source: APXvYqzpBaPk8CUuKwqnZDNaRV3pvRli/PE3T8VAY2O4pLa3UK5q25Ka2P5P4h0oSfE4WH2eFhj5/jD4T1ocuM4jIRM= X-Received: by 2002:ac8:1a2e:: with SMTP id v43mr2528648qtj.204.1569482708228; Thu, 26 Sep 2019 00:25:08 -0700 (PDT) MIME-Version: 1.0 References: <20190923083701.1496-1-mateusz.albecki@intel.com> In-Reply-To: <20190923083701.1496-1-mateusz.albecki@intel.com> From: "Marcin Wojtas" Date: Thu, 26 Sep 2019 09:24:57 +0200 Message-ID: Subject: Re: [PATCH 0/1] Fix eMMC bus timing switch issue To: "Albecki, Mateusz" Cc: edk2-devel-groups-io , Hao A Wu Content-Type: multipart/alternative; boundary="0000000000004e2f7405936fab20" --0000000000004e2f7405936fab20 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Mateusz, For the v2, could you please push the patches to some repo, so that it would be easy to fetch and test? Best regards, Marcin pon., 23 wrz 2019 o 10:37 Albecki, Mateusz napisa=C5=82(a): > SD host controller specification section 3.9 recommends that controller's > bus timing > should be switched after card's bus timing has been switched. In current > eMMC > driver implementation every host controller switch has been done before > call to > EmmcSwitchBusTiming which is causing issues on some eMMC controllers. > > In HS200 switch sequence we removed stopping and starting the SD clock wh= en > switching the host controller timing. Stopping the clock before bus timin= g > switch is only neccessary if preset value enable is set in host controlle= r. > Current code doesn't check if this field is enabled or doesn't support > this feature for any other bus timing change so it has been removed. > > Tests performed: > - eMMC enumeration and OS boot in HS400 > - eMMC enumeration and OS boot in HS200 > - eMMC enumeration and OS boot in high speed SDR 8bit @52MHz > > Tests have been performed on 2 eMMC host controllers. One that has been > failing > with old driver and one that has been passing with old driver. Both > controllers > pass all tests with multiple eMMC devices used. > > Note: We were unable to test DDR speed mode because on test machines both > new flow > and old flow was failing with this speed. I suspect it is a hardware > problem. > > Cc: Hao A Wu > Cc: Marcin Wojtas > > Albecki, Mateusz (1): > MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 > +++---------------------- > 1 file changed, 5 insertions(+), 49 deletions(-) > > -- > 2.14.1.windows.1 > > -------------------------------------------------------------------- > > Intel Technology Poland sp. z o.o. > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII > Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP > 957-07-52-316 | Kapital zakladowy 200.000 PLN. > > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego > adresata i moze zawierac informacje poufne. W razie przypadkowego > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale je= j > usuniecie; jakiekolwiek > przegladanie lub rozpowszechnianie jest zabronione. > This e-mail and any attachments may contain confidential material for the > sole use of the intended recipient(s). If you are not the intended > recipient, please contact the sender and delete all copies; any review or > distribution by > others is strictly prohibited. > > --0000000000004e2f7405936fab20 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
Hi Mateusz,

For the v2, could you pleas= e push the patches to some repo, so that it would be easy to fetch and test= ?

Best regards,
Marcin

pon., 23 wrz= 2019 o 10:37=C2=A0Albecki, Mateusz <mateusz.albecki@intel.com> napisa=C5=82(a):
SD host controller specificati= on section 3.9 recommends that controller's bus timing
should be switched after card's bus timing has been switched. In curren= t eMMC
driver implementation every host controller switch has been done before cal= l to
EmmcSwitchBusTiming which is causing issues on some eMMC controllers.

In HS200 switch sequence we removed stopping and starting the SD clock when=
switching the host controller timing. Stopping the clock before bus timing<= br> switch is only neccessary if preset value enable is set in host controller.=
Current code doesn't check if this field is enabled or doesn't supp= ort
this feature for any other bus timing change so it has been removed.

Tests performed:
- eMMC enumeration and OS boot in HS400
- eMMC enumeration and OS boot in HS200
- eMMC enumeration and OS boot in high speed SDR 8bit @52MHz

Tests have been performed on 2 eMMC host controllers. One that has been fai= ling
with old driver and one that has been passing with old driver. Both control= lers
pass all tests with multiple eMMC devices used.

Note: We were unable to test DDR speed mode because on test machines both n= ew flow
and old flow was failing with this speed. I suspect it is a hardware proble= m.

Cc: Hao A Wu <ha= o.a.wu@intel.com>
Cc: Marcin Wojtas <= mw@semihalf.com>

Albecki, Mateusz (1):
=C2=A0 MdeModulePkg/SdMmcPciHcDxe: Fix bus timing switch sequence

=C2=A0MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 54 +++-------------= ---------
=C2=A01 file changed, 5 insertions(+), 49 deletions(-)

--
2.14.1.windows.1

--------------------------------------------------------------------

Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydz= ial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-31= 6 | Kapital zakladowy 200.000 PLN.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata= i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wi= adomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiek= olwiek
przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by
others is strictly prohibited.

--0000000000004e2f7405936fab20--