From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=X7uJLn+x; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.222.196, mailfrom: mw@semihalf.com) Received: from mail-qk1-f196.google.com (mail-qk1-f196.google.com [209.85.222.196]) by groups.io with SMTP; Fri, 24 May 2019 07:28:14 -0700 Received: by mail-qk1-f196.google.com with SMTP id c15so7835425qkl.2 for ; Fri, 24 May 2019 07:28:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=x+9PNQq/z8IR9C7GJO8RI/qWY1XvJmlc9cSVUFn/56c=; b=X7uJLn+xMILb5e+x4GdiCM5rhQ3kHJBgzNdLuq1hogXBjQ4x+U5aIZPqUpKwn1BlDt 581XDq9VIjBxNSrE+wRwbEkld9/yEkZ1MCqboTSzTXIHa3C0FiSouUwAezBDFfmuERHs 01awD60dPrW1fNoAYJKzvvFg+455muVt7r2tarzsZAQUAikeYRW3TmPDRBd08W3Qbsfo fwBO+M+6/fCkuemHs0vBmKBKhnVNkTHuEFhYIn64UfIjYBlt43oKu0jUQIhppNbaHdiD wG4H/Jymwn57OBJN/vYIaHjxf2Dg4gkHZep4JtPoPwrA6RJ0OaFyPfkzzsHGo6RjiR5E vvbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=x+9PNQq/z8IR9C7GJO8RI/qWY1XvJmlc9cSVUFn/56c=; b=nsSfKjfWxrbHtT0r3xeiSPRWauAp1esE2LM49ARZ2vAP2WhXoOZPj5+1l7uToZFpnk tw8CCnkRU4cJXecGRn8PE/1VDPn/BdDtnJmNIURfUSD2XCPhaQptGx8x+j2QqlGBCsG+ 4r9HTXyKYtb+e1Dvq9I/zUd+WqV94gK04l+xy1IbxEzUapQKqdXWyh53lEaUKe0vpQKZ 2KZ78vcTte99UPlIeW/RCdprh4gWgUzuRneWKx9Vq3duOJdmaqFy0qA3CRMvXfuFsmsW Ji7+ShYhL+Ek2OHpiLjhUiHPiOCnFizrvsywX9BRWn/9rLwWK3AH+4yRCLAVvtKdhyQz Rgsg== X-Gm-Message-State: APjAAAV7YWinA2BAwh2qgq3NMW8QT8Mnuuf6krhaS0fZ2X131fDQHEA/ LLRVNmfS1dLos1TTo/hGkzBVrMEGK86lpI+pG42P6A== X-Google-Smtp-Source: APXvYqwmVFFP4sdPz9IPXpGRzg+23YJJmgg3Vt0YSwzevc0ywpHx3A58Y60TLrzIa38VLXQgLpM3yxSlA49Tc0pHX+c= X-Received: by 2002:ac8:2a4e:: with SMTP id l14mr68319349qtl.313.1558708093266; Fri, 24 May 2019 07:28:13 -0700 (PDT) MIME-Version: 1.0 References: <1558366047-15994-1-git-send-email-mw@semihalf.com> <1558366047-15994-7-git-send-email-mw@semihalf.com> In-Reply-To: From: "Marcin Wojtas" Date: Fri, 24 May 2019 16:28:01 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH v2 06/14] Marvell/Armada7k8k: Add PciExpressLib implementation To: Ard Biesheuvel Cc: edk2-devel-groups-io , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= , Grzegorz Jaszczyk , Kostya Porotchkin , Jici Gao , Rebecca Cran , Mark Kettenis Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pt., 24 maj 2019 o 15:08 Ard Biesheuvel napisa= =C5=82(a): > > On Fri, 24 May 2019 at 15:03, Marcin Wojtas wrote: > > > > pt., 24 maj 2019 o 14:50 Ard Biesheuvel nap= isa=C5=82(a): > > > > > > On Mon, 20 May 2019 at 17:27, Marcin Wojtas wrote: > > > > > > > > From: Ard Biesheuvel > > > > > > > > Implement a special version of PciExpressLib that takes the quirky > > > > nature of the Synopsys Designware PCIe IP into account. In particul= ar, > > > > we need to ignore config space accesses to all devices on the first > > > > bus except device 0, because the broadcast nature of type 0 configu= ration > > > > cycles will result in whatever device is in the slot to appear at e= ach > > > > of the 32 device positions. > > > > > > > > > > I never bothered to implement multisegment support for this SoC, sinc= e > > > MacchiatoBin has only one segment wired up, but since your interest i= s > > > in generic support, it might make sense to drop this patch and > > > implement PciSegmentLib instead (without depending on any of the othe= r > > > library classes that the generic PciExpressLib depends on) > > > > > > > This was (and still is) my plan, but I've been having some serious > > time shortages for extra development. In order not to postpone this > > support any longer I prefer to get merged, what I have and possibly > > rework on top. > > > > About depending on a generic PciExpressLib - do you mean I can filter > > out devices from bus0 in PciSegmentLib? > > > > Yes, please look at Silicon/Socionext/SynQuacer/Library/SynQuacerPciSegme= ntLib > > If you follow the same approach, you no longer need PciLib or > PciExpressLib, it is all flattened into PciSegmentLib. For PciLib I use MdePkg implementation, but if that could be dropped that's good. I saw your library and it would be perfect for reusing on Armada, with one difference: PciSegmentLibGetConfigBase. 1. As a first step I could reuse Synquacer library using single base in PciSegmentLibGetConfigBase (PcdPciExpressBaseAddress) as a stub, for extending later. 2. Afterwards (i.e. in some next patchset) I'd like to use my board description infrastructure for obtaining config space base addresses. How about following solution: - add PciSegmentLib constructor routine, where I'd create a global array with config space addesses - add dispatching for it in PciSegmentLibGetConfigBase? Looking forward to your feedback. Other than that - do you have any remarks to the rest of the patches in v2? Thanks, Marcin