From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::136; helo=mail-it1-x136.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x136.google.com (mail-it1-x136.google.com [IPv6:2607:f8b0:4864:20::136]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B8A6421163DF2 for ; Tue, 9 Oct 2018 04:51:34 -0700 (PDT) Received: by mail-it1-x136.google.com with SMTP id c85-v6so2159495itd.1 for ; Tue, 09 Oct 2018 04:51:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=HnTG87CacSt3jtXt6K0t0gd6yCDkgxbY35IEMq9HePE=; b=Fa2UZZzHFa79qarAAXwafgEgaybaskgylu7YcWMoRNPY8detP58OPfGSCH6oYkJDKF VycTUqXJlMVjL/M1+pI2Ur9JKz8+XPI1PwUtlFFR1Hk40FyyGbHxVnfVp4EJ1+t3K/Cm EsAzib9KM/E1GrS35+oRwMFUcIrV/dES+++C2Sn9qYvwkOA9V2oij0SU8vM9+dVwrBjy tAwfTcz/nQXYrReKwwNjC4qWcxre0VPzNf6ODh7ncXyL4E/Xn8gKL68Z+iNQgHERt+oR /YyVUSm5CkYQlNZV/bIJd5CRx0yBwnfcgY/mO8Sw6pQsHBT8SiKhMKdj6yhIROhIJmoF 9new== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=HnTG87CacSt3jtXt6K0t0gd6yCDkgxbY35IEMq9HePE=; b=uPrnigTqt4pDBMxs2f8jykur7PBtS3Q+NofUOl6FV7lE8uvpJjoTBkYwQ41Z4V9KR0 f/aew4VX6g1LfzrDvUDy0WyDuoafOb17TknZw2FKAcJ17NVk4OZkEH4g5DeRRoQlWRHI uEaLWIUQ5KXSH5zT1ll9Muw9lote8/L9vUO3DM6q1Unf9h1KkNooymR/o0d7FOlG2R95 nkrth/Cvcw5ob2ciuwlyUvYje89LdhX3Lp5t9RtfyaLpVQ0W7VcxR13MeXmg9otOPsLT 9sdM3F1HQChqUhMro6irDzqdWXVpqHaZ6F2tOlryjBX233m/krHP0l88jOO9X7TuzeA4 2b8w== X-Gm-Message-State: ABuFfojoie5zKL0KRZlwvQLqK9Jk913LgrNHyqwf5lkaZR/Z0qlo2WC6 GzqsOMoexhYsYdENH2JsT3+A5w0s54J0429pRiQVvw== X-Google-Smtp-Source: ACcGV62jP5YDu9HslwYNlWIt1KMadaTe2NECAZpk8P8yYbYsLMY6+HMfs7JAkd3OCHHopo28yAEJNCQ5dI/6tcIvecQ= X-Received: by 2002:a24:c543:: with SMTP id f64-v6mr1434922itg.138.1539085893864; Tue, 09 Oct 2018 04:51:33 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Tue, 9 Oct 2018 13:51:21 +0200 Message-ID: To: Ard Biesheuvel , hao.a.wu@intel.com Cc: "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , eric.dong@intel.com, edk2-devel-01 , "Gao, Liming" , nadavh@marvell.com, "Kinney, Michael D" , "Zeng, Star" Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 09 Oct 2018 11:51:35 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel nap= isa=C5=82(a): > > On 9 October 2018 at 13:32, Marcin Wojtas wrote: > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napisa=C5= =82(a): > >> > >> > -----Original Message----- > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On Behalf = Of Ard > >> > Biesheuvel > >> > Sent: Monday, October 08, 2018 11:10 PM > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Gao, Lim= ing; > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add > >> > UhsSignaling to SdMmcOverride protocol > >> > > ... > >> > > >> > I suppose this is defined by the eMMC spec. > >> > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register value= s > >> > for HS200/HS400 defined by the eMMC spec? > >> > >> Hi Ard and Marcin, > >> > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest) does = not > >> mention on how to set the "UHS Mode Select" field of the Host Control = 2 > >> Register when switching to HS200/HS400. (Actually, the EMMC spec does = not > >> mention Host Control 2 Register at all) > >> > >> When it comes to setting the bus mode for EMMC devices, the current > >> implementation of the SdMmcPciHcDxe driver does a mapping when setting= the > >> Host Control 2 Register: > >> > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single > >> matches > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single > >> > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual > >> matches > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual > >> > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single > >> matches > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single > >> > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual > >> matches > >> SD None > >> > >> And there is no obvious counterpart for the EMMC HS400 mode in the SD > >> spec. The driver currently sets the "UHS Mode Select" field to a reser= ved > >> value 0x5. > >> > > > > Thank you Hao, above is on par with what the default UhsSignaling > > routine does in this patch. IMO especially in case the EMMC standard > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accept > > some way of updating HostControl2 register, depending on the > > implementation. What is your opinion Ard? > > > > I would like to know where the current values in SdMmcPciHcDxe come > from if they are not defined in any spec. > > How do we know which ones are the correct ones? Hao, can you justify used values? Thanks, Marcin