From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 80B8CD811A6 for ; Fri, 12 Jan 2024 11:14:18 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=+XZx/P/P+QiI7HsjyBg2eeKP6/7SP0YjtExJ7+1u0Nc=; c=relaxed/simple; d=groups.io; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject:To:Cc:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Type:Content-Transfer-Encoding; s=20140610; t=1705058057; v=1; b=Cw11btdqHcwkbOoeMfK85n4xKnF7DeYh9N+VZlR83NSpuUly5cjwJ7cjPtzaOD8Nm0m9/sfl sy4TLLH+uZahNb8nSrXSKdYSldw4R/9w+2MzeQotlmJqzwN+pjiFveCBvck7FIaFqAZgHrRbS44 ZpCLBkvM+QjKqpORjclBhTEI= X-Received: by 127.0.0.2 with SMTP id skzGYY7687511xVv6JrgrL1X; Fri, 12 Jan 2024 03:14:17 -0800 X-Received: from mail-ot1-f44.google.com (mail-ot1-f44.google.com [209.85.210.44]) by mx.groups.io with SMTP id smtpd.web10.4887.1705058056399784019 for ; Fri, 12 Jan 2024 03:14:16 -0800 X-Received: by mail-ot1-f44.google.com with SMTP id 46e09a7af769-6dde1f23060so2375175a34.2 for ; Fri, 12 Jan 2024 03:14:16 -0800 (PST) X-Gm-Message-State: ds5ExlEwyMRoKBfsL2e6WBR5x7686176AA= X-Google-Smtp-Source: AGHT+IFQ5QWWb/mltYyw5IxB/WCLNE95Hkbtv+FqF3l1NCU2nqJTWWMCfQcQBrW3N2z13fsw9EHMwiqlNWD8lRDk38c= X-Received: by 2002:a05:6830:1c8:b0:6dd:e518:e44 with SMTP id r8-20020a05683001c800b006dde5180e44mr1279972ota.9.1705058055476; Fri, 12 Jan 2024 03:14:15 -0800 (PST) MIME-Version: 1.0 References: <20231221005427.13932-1-ndhillon@marvell.com> <20231221005427.13932-2-ndhillon@marvell.com> In-Reply-To: <20231221005427.13932-2-ndhillon@marvell.com> From: "Marcin Wojtas via groups.io" Date: Fri, 12 Jan 2024 12:14:05 +0100 Message-ID: Subject: Re: [edk2-devel] [edk2-platforms PATCH v2 1/8] Silicon/Marvell: New Marvell Odyssey processor To: ndhillon@marvell.com Cc: devel@edk2.groups.io, quic_llindhol@quicinc.com, sbalcerak@marvell.com, marcin.s.wojtas@gmail.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,mw@semihalf.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=Cw11btdq; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=none +marcin.s.wojtas@gmail.com Hi Narinder, czw., 21 gru 2023 o 01:54 napisa=C5=82(a): > > From: Narinder Dhillon > > This patch creates ArmPlatformPkg for Odyssey SoC by overriding some of > the files in original ArmPlatformPkg. Differences from standard > ArmPlatformPkg are marked with "--- MRVL Override" comment. > > Signed-off-by: Narinder Dhillon > --- > .../PrePi/AArch64/ModuleEntryPoint.S | 136 ++++++++++ > .../ArmPlatformPkg/PrePi/PeiMPCore.inf | 110 ++++++++ > .../Override/ArmPlatformPkg/PrePi/PrePi.c | 238 ++++++++++++++++++ > 3 files changed, 484 insertions(+) > create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64= /ModuleEntryPoint.S > create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCo= re.inf > create mode 100644 Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c > > diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/Module= EntryPoint.S b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/Module= EntryPoint.S > new file mode 100644 > index 0000000000..481d794154 > --- /dev/null > +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/AArch64/ModuleEntryPo= int.S > @@ -0,0 +1,136 @@ > +// > +// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.
> +// > +// SPDX-License-Identifier: BSD-2-Clause-Patent > +// > +// > + > +#include > +GCC_ASM_IMPORT(mDeviceTreeBaseAddress) // --- MRVL Override: defined in= PrePi.c > +GCC_ASM_IMPORT(mSystemMemoryEnd) // --- MRVL Override > +ASM_FUNC(_ModuleEntryPoint) > + > + // --- MRVL Override start > + // Save the boot parameter to a global variable > + adr x10, mDeviceTreeBaseAddress > + str x1, [x10] > + // --- MRVL Override end > + > + // Do early platform specific actions > + bl ASM_PFX(ArmPlatformPeiBootAction) > + > + // Get ID of this CPU in multi-core system > + bl ASM_PFX(ArmReadMpidr) > + // Keep a copy of the MpId register value > + mov x10, x0 > + > +_SetSVCMode: > +// Check if we can install the stack at the top of the System Memory or = if we need > +// to install the stacks at the bottom of the Firmware Device (case the = FD is located > +// at the top of the DRAM) > +_SystemMemoryEndInit: > + ldr x1, mSystemMemoryEnd > + > + // --- MRVL Override start > + // mSystemMemoryEnd shall be set by SMC call within ArmPlatformPeiBoot= Action > + cmp x1, #0xffffffffffffffff > + bne _SetupStackPosition > + // if mSystemMemoryEnd wasn't gethered from SMC call, get it from PCDs > + MOV64 (x1, FixedPcdGet64(PcdSystemMemoryBase) + FixedPcdGet64(PcdSyste= mMemorySize) - 1) > + > + // Update the global variable > + adr x2, mSystemMemoryEnd > + str x1, [x2] > + // --- MRVL Override end > + > +_SetupStackPosition: > + // x1 =3D SystemMemoryTop > + > + // Calculate Top of the Firmware Device > + MOV64 (x2, FixedPcdGet64(PcdFdBaseAddress)) > + MOV32 (x3, FixedPcdGet32(PcdFdSize) - 1) > + sub x3, x3, #1 > + add x3, x3, x2 // x3 =3D FdTop =3D PcdFdBaseAddress + PcdFdSize > + > + // UEFI Memory Size (stacks are allocated in this region) > + MOV32 (x4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize)) > + > + // > + // Reserve the memory for the UEFI region (contain stacks on its top) > + // > + > + // Calculate how much space there is between the top of the Firmware a= nd the Top of the System Memory > + subs x0, x1, x3 // x0 =3D SystemMemoryTop - FdTop > + b.mi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case= when the PrePi is in XIP memory outside of the DRAM > + cmp x0, x4 > + b.ge _SetupStack > + > + // Case the top of stacks is the FdBaseAddress > + mov x1, x2 > + > +_SetupStack: > + // x1 contains the top of the stack (and the UEFI Memory) > + > + // Because the 'push' instruction is equivalent to 'stmdb' (decrement = before), we need to increment > + // one to the top of the stack. We check if incrementing one does not = overflow (case of DRAM at the > + // top of the memory space) > + adds x11, x1, #1 > + b.cs _SetupOverflowStack > + > +_SetupAlignedStack: > + mov x1, x11 > + b _GetBaseUefiMemory > + > +_SetupOverflowStack: > + // Case memory at the top of the address space. Ensure the top of the = stack is EFI_PAGE_SIZE > + // aligned (4KB) > + and x1, x1, ~EFI_PAGE_MASK > + > +_GetBaseUefiMemory: > + // Calculate the Base of the UEFI Memory > + sub x11, x1, x4 > + > +_GetStackBase: > + // r1 =3D The top of the Mpcore Stacks > + // Stack for the primary core =3D PrimaryCoreStack > + MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)) > + sub x12, x1, x2 > + > + // Stack for the secondary core =3D Number of Cores - 1 > + MOV32 (x1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCor= eSecondaryStackSize)) > + sub x12, x12, x1 > + > + // x12 =3D The base of the MpCore Stacks (primary stack & secondary st= acks) > + mov x0, x12 > + mov x1, x10 > + //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStac= kSize) > + MOV32 (x2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)) > + MOV32 (x3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)) > + bl ASM_PFX(ArmPlatformStackSet) > + > + // Is it the Primary Core ? > + mov x0, x10 > + bl ASM_PFX(ArmPlatformIsPrimaryCore) > + cmp x0, #1 > + bne _PrepareArguments > + > +_PrepareArguments: > + mov x0, x10 > + mov x1, x11 > + mov x2, x12 > + > + // Move sec startup address into a data register > + // Ensure we're jumping to FV version of the code (not boot remapped a= lias) > + ldr x4, =3DASM_PFX(CEntryPoint) > + > + // Set the frame pointer to NULL so any backtraces terminate here > + mov x29, xzr > + > + // Jump to PrePiCore C code > + // x0 =3D MpId > + // x1 =3D UefiMemoryBase > + // x2 =3D StacksBase > + blr x4 > + > +_NeverReturn: > + b _NeverReturn > diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf = b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf > new file mode 100644 > index 0000000000..49d9e406d7 > --- /dev/null > +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PeiMPCore.inf > @@ -0,0 +1,110 @@ > +#/** @file > +# > +# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.
> +# Copyright (c) 2011-2017, ARM Ltd. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#**/ > + > +[Defines] > + INF_VERSION =3D 0x00010005 > + BASE_NAME =3D ArmPlatformPrePiMPCore > + FILE_GUID =3D d959e387-7b91-452c-90e0-a1dbac90ddb= 8 > + MODULE_TYPE =3D SEC > + VERSION_STRING =3D 1.0 > + DEFINE ORG_SOURCES_PATH =3D ArmPlatformPkg/PrePi # --- MRVL Ove= rride > + > +[Sources] > + $(ORG_SOURCES_PATH)/PrePi.h # --- MRVL Override > + PrePi.c > + $(ORG_SOURCES_PATH)/MainMPCore.c # --- MRVL Override > + > +[Sources.ARM] > + $(ORG_SOURCES_PATH)/Arm/ArchPrePi.c # --- MRVL Overr= ide > + $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.S | GCC # --- MRVL Overr= ide > + $(ORG_SOURCES_PATH)/Arm/ModuleEntryPoint.asm | RVCT # --- MRVL Overr= ide > + > +[Sources.AArch64] > + $(ORG_SOURCES_PATH)/AArch64/ArchPrePi.c # --- MRVL Overr= ide > + AArch64/ModuleEntryPoint.S > + > +[Packages] > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + EmbeddedPkg/EmbeddedPkg.dec > + ArmPkg/ArmPkg.dec > + ArmPlatformPkg/ArmPlatformPkg.dec > + > +[LibraryClasses] > + BaseLib > + CacheMaintenanceLib > + DebugLib > + DebugAgentLib > + ArmLib > + ArmGicLib > + IoLib > + TimerLib > + SerialPortLib > + ExtractGuidedSectionLib > + LzmaDecompressLib > + DebugAgentLib > + PrePiLib > + ArmPlatformLib > + ArmPlatformStackLib > + MemoryAllocationLib > + HobLib > + PrePiHobListPointerLib > + PlatformPeiLib > + MemoryInitPeiLib > + FdtLib # --- MRVL Override > + > +[Ppis] > + gArmMpCoreInfoPpiGuid > + > +[Guids] > + gArmMpCoreInfoGuid > + gEfiFirmwarePerformanceGuid > + gFdtHobGuid # --- MRVL Override > + > +[FeaturePcd] > + gEmbeddedTokenSpaceGuid.PcdPrePiProduceMemoryTypeInformationHob > + gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores > + > +[Pcd] > + gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdVFPEnabled > + > + gArmTokenSpaceGuid.PcdFdBaseAddress > + gArmTokenSpaceGuid.PcdFdSize > + > + gArmTokenSpaceGuid.PcdFvBaseAddress > + gArmTokenSpaceGuid.PcdFvSize > + > + gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize > + gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize > + > + gArmTokenSpaceGuid.PcdGicDistributorBase > + gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase > + gArmTokenSpaceGuid.PcdGicSgiIntId > + > + gArmTokenSpaceGuid.PcdSystemMemoryBase > + gArmTokenSpaceGuid.PcdSystemMemorySize > + gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize > + > + gArmPlatformTokenSpaceGuid.PcdCoreCount > + > + gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize > + > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesData > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiRuntimeServicesCode > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesCode > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiBootServicesData > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderCode > + gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiLoaderData > + > diff --git a/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c b/Sili= con/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c > new file mode 100644 > index 0000000000..5168881b18 > --- /dev/null > +++ b/Silicon/Marvell/Override/ArmPlatformPkg/PrePi/PrePi.c > @@ -0,0 +1,238 @@ > +/** @file > + > + Copyright (c) 2011-2017, ARM Limited. All rights reserved. > + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include "PrePi.h" > +#include // fdt_totalsize // --- MRVL Override > + > +#define IS_XIP() (((UINT64)FixedPcdGet64 (PcdFdBaseAddress) > mSystemMe= moryEnd) ||\ > + ((FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (Pc= dFdSize)) <=3D FixedPcdGet64 (PcdSystemMemoryBase))) > + > +UINT64 mSystemMemoryEnd =3D FixedPcdGet64 (PcdSystemMemoryBase) + > + FixedPcdGet64 (PcdSystemMemorySize) - 1; > + > +UINT64 mDeviceTreeBaseAddress =3D 0; // --- MRVL Override > +int fdt_check_header(const void *fdt); > + > +EFI_STATUS > +GetPlatformPpi ( > + IN EFI_GUID *PpiGuid, > + OUT VOID **Ppi > + ) > +{ > + UINTN PpiListSize; > + UINTN PpiListCount; > + EFI_PEI_PPI_DESCRIPTOR *PpiList; > + UINTN Index; > + > + PpiListSize =3D 0; > + ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList); > + PpiListCount =3D PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR); > + for (Index =3D 0; Index < PpiListCount; Index++, PpiList++) { > + if (CompareGuid (PpiList->Guid, PpiGuid) =3D=3D TRUE) { > + *Ppi =3D PpiList->Ppi; > + return EFI_SUCCESS; > + } > + } > + > + return EFI_NOT_FOUND; > +} > + > +VOID > +PrePiMain ( > + IN UINTN UefiMemoryBase, > + IN UINTN StacksBase, > + IN UINT64 StartTimeStamp > + ) > +{ > + EFI_HOB_HANDOFF_INFO_TABLE *HobList; > + ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi; > + UINTN ArmCoreCount; > + ARM_CORE_INFO *ArmCoreInfoTable; > + EFI_STATUS Status; > + CHAR8 Buffer[500]; // --- MRVL Override > + UINTN CharCount; > + UINTN StacksSize; > + FIRMWARE_SEC_PERFORMANCE Performance; > + > + // If ensure the FD is either part of the System Memory or totally out= side of the System Memory (XIP) > + ASSERT ( > + IS_XIP () || > + ((FixedPcdGet64 (PcdFdBaseAddress) >=3D FixedPcdGet64 (PcdSystemMemo= ryBase)) && > + ((UINT64)(FixedPcdGet64 (PcdFdBaseAddress) + FixedPcdGet32 (PcdFdSi= ze)) <=3D (UINT64)mSystemMemoryEnd)) > + ); > + > + // Initialize the architecture specific bits > + ArchInitialize (); > + > + // Initialize the Serial Port > + SerialPortInitialize (); > + CharCount =3D AsciiSPrint ( > + Buffer, > + sizeof (Buffer), > + "UEFI firmware (version %s built at %a on %a)\n\r", > + (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString), > + __TIME__, > + __DATE__ > + ); > + SerialPortWrite ((UINT8 *)Buffer, CharCount); > + > + // Initialize the Debug Agent for Source Level Debugging > + InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL); > + SaveAndSetDebugTimerInterrupt (TRUE); > + > + // Declare the PI/UEFI memory region > + HobList =3D HobConstructor ( > + (VOID *)UefiMemoryBase, > + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize), > + (VOID *)UefiMemoryBase, > + (VOID *)StacksBase // The top of the UEFI Memory is reserv= ed for the stacks > + ); > + PrePeiSetHobList (HobList); > + > + // --- MRVL Override start > + // Build the FDT HOB > + ASSERT(fdt_check_header ((VOID *)mDeviceTreeBaseAddress) =3D=3D 0); > + DEBUG((DEBUG_INFO, "FDT address: %lx, size: %d\n", > + mDeviceTreeBaseAddress, > + fdt_totalsize((VOID *)mDeviceTreeBaseAddress))); > + > + BuildGuidDataHob (&gFdtHobGuid, &mDeviceTreeBaseAddress, sizeof(mDevic= eTreeBaseAddress)); > + // --- MRVL Override end > + > + // Initialize MMU and Memory HOBs (Resource Descriptor HOBs) > + Status =3D MemoryPeim (UefiMemoryBase, FixedPcdGet32 (PcdSystemMemoryU= efiRegionSize)); > + ASSERT_EFI_ERROR (Status); > + > + // Create the Stacks HOB (reserve the memory for all stacks) > + if (ArmIsMpCore ()) { > + StacksSize =3D PcdGet32 (PcdCPUCorePrimaryStackSize) + > + ((FixedPcdGet32 (PcdCoreCount) - 1) * FixedPcdGet32 (Pc= dCPUCoreSecondaryStackSize)); > + } else { > + StacksSize =3D PcdGet32 (PcdCPUCorePrimaryStackSize); > + } > + > + BuildStackHob (StacksBase, StacksSize); > + > + // TODO: Call CpuPei as a library > + BuildCpuHob (ArmGetPhysicalAddressBits (), PcdGet8 (PcdPrePiCpuIoSize)= ); > + > + if (ArmIsMpCore ()) { > + // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid > + Status =3D GetPlatformPpi (&gArmMpCoreInfoPpiGuid, (VOID **)&ArmMpCo= reInfoPpi); > + > + // On MP Core Platform we must implement the ARM MP Core Info PPI (g= ArmMpCoreInfoPpiGuid) > + ASSERT_EFI_ERROR (Status); > + > + // Build the MP Core Info Table > + ArmCoreCount =3D 0; > + Status =3D ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &Ar= mCoreInfoTable); > + if (!EFI_ERROR (Status) && (ArmCoreCount > 0)) { > + // Build MPCore Info HOB > + BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (A= RM_CORE_INFO) * ArmCoreCount); > + } > + } > + > + // Store timer value logged at the beginning of firmware image executi= on > + Performance.ResetEnd =3D GetTimeInNanoSecond (StartTimeStamp); > + > + // Build SEC Performance Data Hob > + BuildGuidDataHob (&gEfiFirmwarePerformanceGuid, &Performance, sizeof (= Performance)); > + > + // Set the Boot Mode > + SetBootMode (ArmPlatformGetBootMode ()); > + > + // Initialize Platform HOBs (CpuHob and FvHob) > + Status =3D PlatformPeim (); > + ASSERT_EFI_ERROR (Status); > + > + // Now, the HOB List has been initialized, we can register performance= information > + PERF_START (NULL, "PEI", NULL, StartTimeStamp); > + > + // SEC phase needs to run library constructors by hand. > + ProcessLibraryConstructorList (); > + > + // Assume the FV that contains the SEC (our code) also contains a comp= ressed FV. > + Status =3D DecompressFirstFv (); > + ASSERT_EFI_ERROR (Status); > + > + // Load the DXE Core and transfer control to it > + Status =3D LoadDxeCoreFromFv (NULL, 0); > + ASSERT_EFI_ERROR (Status); > +} > + > +VOID > +CEntryPoint ( > + IN UINTN MpId, > + IN UINTN UefiMemoryBase, > + IN UINTN StacksBase > + ) > +{ > + UINT64 StartTimeStamp; > + > + // Initialize the platform specific controllers > + ArmPlatformInitialize (MpId); > + > + if (ArmPlatformIsPrimaryCore (MpId) && PerformanceMeasurementEnabled (= )) { > + // Initialize the Timer Library to setup the Timer HW controller > + TimerConstructor (); > + // We cannot call yet the PerformanceLib because the HOB List has no= t been initialized > + StartTimeStamp =3D GetPerformanceCounter (); > + } else { > + StartTimeStamp =3D 0; > + } > + > + // Data Cache enabled on Primary core when MMU is enabled. > + ArmDisableDataCache (); > + // Invalidate instruction cache > + ArmInvalidateInstructionCache (); > + // Enable Instruction Caches on all cores. > + ArmEnableInstructionCache (); > + > + // Define the Global Variable region when we are not running in XIP > + if (!IS_XIP ()) { > + if (ArmPlatformIsPrimaryCore (MpId)) { > + if (ArmIsMpCore ()) { > + // Signal the Global Variable Region is defined (event: ARM_CPU_= EVENT_DEFAULT) > + ArmCallSEV (); > + } > + } else { > + // Wait the Primary core has defined the address of the Global Var= iable region (event: ARM_CPU_EVENT_DEFAULT) > + ArmCallWFE (); > + } > + } > + > + // If not primary Jump to Secondary Main > + if (ArmPlatformIsPrimaryCore (MpId)) { > + InvalidateDataCacheRange ( > + (VOID *)UefiMemoryBase, > + FixedPcdGet32 (PcdSystemMemoryUefiRegionSize) > + ); > + > + // Goto primary Main. > + PrimaryMain (UefiMemoryBase, StacksBase, StartTimeStamp); > + } else { > + SecondaryMain (MpId); > + } > + > + // DXE Core should always load and never return > + ASSERT (FALSE); > +} > -- > 2.34.1 > If I read this patch correctly, you are updating the SystemMemoryMap and building HoB to accomodate the FDT blob from early firmware, with the data obtained via SMC (or a fallback to PCDs). IMO you should be able to do all of these using ArmPlatformPkg/Include/Library/ArmPlatformLib.h routines, in this case: ArmPlatformGetVirtualMemoryMap(). You can check Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLi= bMem.c for reference, there's a lot of SMC/PCD/HoB magic involved there. Best regards, Marcin -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#113710): https://edk2.groups.io/g/devel/message/113710 Mute This Topic: https://groups.io/mt/103292509/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-