From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::12a; helo=mail-it1-x12a.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x12a.google.com (mail-it1-x12a.google.com [IPv6:2607:f8b0:4864:20::12a]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 216DA21167467 for ; Thu, 11 Oct 2018 22:06:56 -0700 (PDT) Received: by mail-it1-x12a.google.com with SMTP id e74-v6so16578601ita.2 for ; Thu, 11 Oct 2018 22:06:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=kvodU/DuX+cnAzotn8cQtoDwhLA8KdkIt0nACKAlYEo=; b=qjek60bDy6YFOZ3U2WeN7JraCM/4k/AaaCzzRLqWCc5UqQcDWsODoDWHuHI3QYJQT6 mC+NARZ7Gh281In4xSnTucGe/jpg5mHOBruITC3IDCk9tbqdQ40cRF3Jh6G6rB050+Xv vKOcTZWCcwYvKKj23SLDZ8Prr9oJEgUVIdjlUupAFuiIKQCMb4ZwoxUvGyPgv4P+NJrt /zzCCxNNYYso4bWnqZ23w3JjxVVhw4oPhns9aM4QjE65v4utHL4UDmkw6Zq7n+LzoJ2S 0bqQRMmyPR7+s7qhROEgwiuIfOJ9Ke7KfEtMxRJaQpBDsXJ+jTxHgEv/+090PBAZt1i5 0qnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=kvodU/DuX+cnAzotn8cQtoDwhLA8KdkIt0nACKAlYEo=; b=iesXvvDkghhOsk4fDlHvDP0hdRjMqxAn5/GLzMIpJKlGBMLWdTqV6ngOTAMdD8Plsq 72S6Hj/MzWyUFyek1IfGKz+WVoHidBhDJbOW6kTBm8iSkv3AvVt38nAK+FnPDwoZSnk3 Buqpxju6XI7R1bUS2S8BKcmA2nBgrtpxwQtcdovyIR0JAICnG7iPgwsNMGWIN+eK0DOJ SPBzOHWNgCPr9lPTcvbYFyeVLS6UnhbA/HCfkzUnMohuRPuk4FZ3s7zWnKHQcYWW3KzU VTUWqzJmNw/TPsAuWrhQTa8AuHmSJMgcQxRDfApEvXYvSOx0J66f6JHthu4bhEe5aZ7d YbXg== X-Gm-Message-State: ABuFfog1NHrSRRGQ+MKmL28Wpn/mEH1J9KBbs+jjqyHVEyCn8wowkAD4 xVb7iWEvgjDIXBvSzCO8aoKmKG9rdHieXBE7mortsA== X-Google-Smtp-Source: ACcGV62zkyAR7Hd+MwuEdlJPhBZeadKj61WLxT6I0MSisMzbtrjEvSjVtWxCM7bNREpSi0aYuIlRBFUfNVQRkKiOzPA= X-Received: by 2002:a24:a0c:: with SMTP id 12-v6mr2951214itw.145.1539320816101; Thu, 11 Oct 2018 22:06:56 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> <1538745911-22484-3-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Fri, 12 Oct 2018 07:06:44 +0200 Message-ID: To: hao.a.wu@intel.com, Ard Biesheuvel Cc: "Ni, Ruiyu" , "Tian, Feng" , Tomasz Michalec , eric.dong@intel.com, edk2-devel-01 , "Gao, Liming" , nadavh@marvell.com, "Kinney, Michael D" , "Zeng, Star" Subject: Re: [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride protocol X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 05:06:57 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pt., 12 pa=C5=BA 2018 o 03:41 Wu, Hao A napisa=C5=82(a= ): > > > -----Original Message----- > > From: Marcin Wojtas [mailto:mw@semihalf.com] > > Sent: Thursday, October 11, 2018 11:43 PM > > To: Wu, Hao A > > Cc: Ni, Ruiyu; Ard Biesheuvel; Tian, Feng; Tomasz Michalec; Dong, Eric;= edk2- > > devel-01; Gao, Liming; nadavh@marvell.com; Kinney, Michael D; Zeng, Sta= r > > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: Add > > UhsSignaling to SdMmcOverride protocol > > > > wt., 9 pa=C5=BA 2018 o 13:51 Marcin Wojtas napisa=C5= =82(a): > > > > > > wt., 9 pa=C5=BA 2018 o 13:45 Ard Biesheuvel > > napisa=C5=82(a): > > > > > > > > On 9 October 2018 at 13:32, Marcin Wojtas wrote: > > > > > wt., 9 pa=C5=BA 2018 o 13:28 Wu, Hao A napis= a=C5=82(a): > > > > >> > > > > >> > -----Original Message----- > > > > >> > From: edk2-devel [mailto:edk2-devel-bounces@lists.01.org] On > > Behalf Of Ard > > > > >> > Biesheuvel > > > > >> > Sent: Monday, October 08, 2018 11:10 PM > > > > >> > To: Marcin Wojtas; Ni, Ruiyu; Wu, Hao A > > > > >> > Cc: Tian, Feng; Tomasz Michalec; Dong, Eric; edk2-devel-01; Ga= o, > > Liming; > > > > >> > Nadav Haklai; Kinney, Michael D; Zeng, Star > > > > >> > Subject: Re: [edk2] [PATCH v2 2/4] MdeModulePkg/SdMmcPciHcDxe: > > Add > > > > >> > UhsSignaling to SdMmcOverride protocol > > > > >> > > > > > ... > > > > >> > > > > > >> > I suppose this is defined by the eMMC spec. > > > > >> > > > > > >> > Ruiyu, Hao, could you clarify? Are the host control 2 register= values > > > > >> > for HS200/HS400 defined by the eMMC spec? > > > > >> > > > > >> Hi Ard and Marcin, > > > > >> > > > > >> As far as I know, the EMMC Electrical Standard Spec 5.1 (latest)= does > > not > > > > >> mention on how to set the "UHS Mode Select" field of the Host > > Control 2 > > > > >> Register when switching to HS200/HS400. (Actually, the EMMC spec > > does not > > > > >> mention Host Control 2 Register at all) > > > > >> > > > > >> When it comes to setting the bus mode for EMMC devices, the curr= ent > > > > >> implementation of the SdMmcPciHcDxe driver does a mapping when > > setting the > > > > >> Host Control 2 Register: > > > > >> > > > > >> EMMC High Speed SDR - Freq: 0-52 MHz, Data Rate: Single > > > > >> matches > > > > >> SD SDR25 - Freq: 0-50 MHz, Data Rate: Single > > > > >> > > > > >> EMMC High Speed DDR - Freq: 0-52 MHz, Data Rate: Dual > > > > >> matches > > > > >> SD DDR50 - Freq: 0-50 MHz, Data Rate: Dual > > > > >> > > > > >> EMMC HS200 - Freq: 0-200 MHz, Data Rate: Single > > > > >> matches > > > > >> SD SDR104 - Freq: 0-208 MHz, Data Rate: Single > > > > >> > > > > >> EMMC HS400 - Freq: 0-200 MHz, Data Rate: Dual > > > > >> matches > > > > >> SD None > > > > >> > > > > >> And there is no obvious counterpart for the EMMC HS400 mode in t= he > > SD > > > > >> spec. The driver currently sets the "UHS Mode Select" field to a > > reserved > > > > >> value 0x5. > > > > >> > > > > > > > > > > Thank you Hao, above is on par with what the default UhsSignaling > > > > > routine does in this patch. IMO especially in case the EMMC stand= ard > > > > > is not unequivocal regarding UHS_MODE_SEL, I'd encourage to accep= t > > > > > some way of updating HostControl2 register, depending on the > > > > > implementation. What is your opinion Ard? > > > > > > > > > > > > > I would like to know where the current values in SdMmcPciHcDxe come > > > > from if they are not defined in any spec. > > > > > > > > How do we know which ones are the correct ones? > > > > > > Hao, can you justify used values? > > > > > > > Hi Hao, > > > > Can you please take a look at the UHS_MODE_SEL values source for eMMC? > > Hi Marcin, > > Sorry for the delayed response. > > For the current implementation of the SdMmcPciHcDxe driver, the selecting > of "UHS Mode Select" field value of the Host Control 2 Register is based > on a Max Clock Frequency & Data Rate (Single or Dual) matching > relationship between the: > > A. Table 3-6 of the SD Specifications Part 1 Physical Layer Simplified > Specification Version 4.10 > > and > > B. Table 4 of the EMMC Electrical Standard Spec 5.1 > > The matching details was included in my previous reply. The only missing > part is there seems no matching for the EMMC HS400 mode in the SD > specifications. For this case, we are currently using the same approach > with the Linux implementation, that is to set the "UHS Mode Select" to a > value of 0x5 (not standard). > Hao, Thanks a lot for the clarification. Ard, Knowing the numbers details, what is your view of the UhsSignaling handling= ? Best regards, Marcin