From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4001:c06::243; helo=mail-io0-x243.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-io0-x243.google.com (mail-io0-x243.google.com [IPv6:2607:f8b0:4001:c06::243]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id 84CFB203525F5 for ; Thu, 26 Oct 2017 07:25:54 -0700 (PDT) Received: by mail-io0-x243.google.com with SMTP id p186so5754594ioe.12 for ; Thu, 26 Oct 2017 07:29:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=+XMISAVhMv0W4w9TMpByQtuTmAY1El0SJ8Fy7vI0QbQ=; b=ZnOerM2d7dolWPxy8aVq13R8DGQqFK94RD4i7GDo+4VicgxgQtgmnK9EupzocJTKo8 GrR9xy0sUO7mo+179X74G0YMxaVc0hApfch4S9zV7gJmKh+t3x4m4LelR2c2ShAAdmJN POv4Dm4eQI954HLyX3tALjSv5Nd/A6GOpp0AQp3L/l+EQ7eTYyfd+OfT2dOdBoG7lwlQ JNamnzHwl1VONv6ydn//R/iSesPbHF3PHhBjrkqodtnp1vEHZ2uV7jxxoGt/jvYatR+I lu4RRiqIccno945lgig+KNv+jBhrP2nLYYN5KeeVz0D4/9yVmsCRjKHXJ3De0vtUM+Me 9CZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=+XMISAVhMv0W4w9TMpByQtuTmAY1El0SJ8Fy7vI0QbQ=; b=Eve9IYacGVMNFYr5fcc4dfDlcILknq6l24lNOT5mXuoRXOZ93yZ5TXC5iyPQFZ4PB6 RgHK4qwsKvl+N2Y6wJnvv/xrGT1tdRyQFpQoIBUDC5OmdFYZtWugvZaTnByRPgJYU3ki maJudprBMU1l2KuVns6lANiJIwmlfqoO4PrNBgTn5FrbHNLZlekxMDyODT2DqDht+itA 2XqteI9DTS4fVJ+c8+fa3sibJq7TxLDQ+HwZF0bxC9HGGibUZp/otbYvBpXOJquCRbAr 8u6fghI/Juq8+2xacdg9sLNeGR2KwjirVy27Yr0n5cQdTkaZmIMVUaSi1JAL45uk/Al8 XcUQ== X-Gm-Message-State: AMCzsaVK8dD8Mez5mw1km4cbhDAQvaYVBc9X6bcymFpk4VA/QHkXrrC6 eyDWlxZVdWaaZ7gID6DSqGKqfkyssnprMMb+eeEK2Q== X-Google-Smtp-Source: ABhQp+Q8yTsN2gx8DPZTq0cAksyVSqjN9bftLPUcMPbXV0EyPS0z6QJTBNWZjMPGwCCCwypKtKgXHSwc4L4EUeGu4ec= X-Received: by 10.107.68.10 with SMTP id r10mr30896687ioa.202.1509028179986; Thu, 26 Oct 2017 07:29:39 -0700 (PDT) MIME-Version: 1.0 Received: by 10.107.167.208 with HTTP; Thu, 26 Oct 2017 07:29:39 -0700 (PDT) In-Reply-To: <20171026140200.v33dpi54ri2e3fuu@bivouac.eciton.net> References: <1508980777-29006-1-git-send-email-mw@semihalf.com> <1508980777-29006-10-git-send-email-mw@semihalf.com> <20171026134612.nro2lhy2l3qvm7pq@bivouac.eciton.net> <20171026140200.v33dpi54ri2e3fuu@bivouac.eciton.net> From: Marcin Wojtas Date: Thu, 26 Oct 2017 16:29:39 +0200 Message-ID: To: Leif Lindholm Cc: edk2-devel-01 , Ard Biesheuvel , nadavh@marvell.com, Neta Zur Hershkovits , Kostya Porotchkin , Hua Jing , semihalf-dabros-jan Subject: Re: [platforms: PATCH 09/10] Marvell/Drivers: XenonDxe: Fix base clock frequency X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.22 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 26 Oct 2017 14:25:54 -0000 Content-Type: text/plain; charset="UTF-8" 2017-10-26 16:02 GMT+02:00 Leif Lindholm : > On Thu, Oct 26, 2017 at 03:54:41PM +0200, Marcin Wojtas wrote: >> 2017-10-26 15:46 GMT+02:00 Leif Lindholm : >> > On Thu, Oct 26, 2017 at 03:19:36AM +0200, Marcin Wojtas wrote: >> >> Incorrectly the clock divisor was calculated relatively >> >> to 255MHz instead of actual 400MHz. >> > >> > This describes the specific symptom, not the problem with the existing >> > code. >> > >> >> Fix this. >> >> >> >> Contributed-under: TianoCore Contribution Agreement 1.1 >> >> Signed-off-by: Marcin Wojtas >> >> --- >> >> Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c | 4 ++-- >> >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> >> >> diff --git a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> >> index ccbf355..0b9328b 100644 >> >> --- a/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> >> +++ b/Platform/Marvell/Drivers/SdMmc/XenonDxe/SdMmcPciHci.c >> >> @@ -16,6 +16,7 @@ >> >> **/ >> >> >> >> #include "SdMmcPciHcDxe.h" >> >> +#include "XenonSdhci.h" >> >> >> >> /** >> >> Dump the content of SD/MMC host controller's Capability Register. >> >> @@ -703,9 +704,8 @@ SdMmcHcClockSupply ( >> >> // >> >> // Calculate a divisor for SD clock frequency >> >> // >> >> - ASSERT (Capability.BaseClkFreq != 0); >> >> >> >> - BaseClkFreq = Capability.BaseClkFreq; >> > >> > Why is Capability.BaseClkFreq the wrong frequency to use? >> >> The Capability.BaseClkFreq is UINT8 and can hold up to 0xff -> 255MHz. >> An alternative would be change this generic type to UINT16 and update >> field properly during initialization - do you prefer that? > > No, I'm still dreaming we might be able to reintegrate this into the > MdeModulePkg driver in some glorious future. Yes, that would be great. I imagine some SDMMC_HOST_PROTOCOL exposing callbacks to set UHS, custom clock handling, etc (like it's done in the Linux). > > So what you are basically saying is that this controller is running at > a higher frequency than is permitted (or even describable) by the > specification? If so, _that_ needs to be in the commit message (and > really, a comment by the code as well). Yes, this clock value is Xenon controller's quirk. I will mention it in commit log/comment, but please let know if you wish me to: a. extend BaseClkFreq to UINT16 and configure it properly during init b. leave as is with better description only I lean towards a., it's a very low-cost quirk to be applied. Best regards, Marcin