From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received-SPF: None (no SPF record) identity=mailfrom; client-ip=2607:f8b0:4864:20::129; helo=mail-it1-x129.google.com; envelope-from=mw@semihalf.com; receiver=edk2-devel@lists.01.org Received: from mail-it1-x129.google.com (mail-it1-x129.google.com [IPv6:2607:f8b0:4864:20::129]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id F068121B02822 for ; Fri, 12 Oct 2018 05:50:47 -0700 (PDT) Received: by mail-it1-x129.google.com with SMTP id i76-v6so18006879ita.3 for ; Fri, 12 Oct 2018 05:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=y9EKYbMyETRddn/RxNCidgSspD+XnRz5EEydJGOlTao=; b=dIm8W+9bk1lvnWAuat3ReHxKLYPCbnLl0EmJbsaUqpmQSVnz34UnnQr4+uU1ycMU+o Xee+BvKc7VwR37EbaM5OO6TEAm437kzC3l2J/2xvdOG8WNbWcvEDifd94rZQt/c8qL0O E1Z67cUd5/dQH8Caw9WjaPNRqrwtQHyNu493sQ1SmARRRwymGpptAXkDRxVjDkM10ltz 1g+C5eRH5yAKBjU2xYwL18OJiXgCz8bHYoWxhCzJlAAuXEYzgElme1qPPd2TXHfs0Nat cka0b5uKpMcbBt7WC4za630SiLcXpk6Xsgxv68x2+bLALqKvdsmLZeL8G/qS+/X2adw+ 9Kcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=y9EKYbMyETRddn/RxNCidgSspD+XnRz5EEydJGOlTao=; b=lvTyaayob+956okcZUB9jA8DKN8ZO4XWYtFYTOW4d0fN2TacuLa4D2DaMJ+znuM1xM 3DGKmj2VyLWpVO02JXdTapST8nIDnVhYpQUOniIri0wwtjjFURnbK8BW7WYEg4vKCwHJ FRA0rZ9Q8iaxDqcOB7vOYdEkluUO79AXgYiAthNyyQ55l84VT11xd56loQoMlFT/Y/n9 NMgX9FCv0ViC9Y8uUm+AUk1KJt8PHbhQLT/DonyLZpm66hwSSvWcpeGThY60oIU0eJk9 BD1FSGuOrPRDgwfpqrg6dxH47lbhe+ajC7eaYFXk85Lb13Z9nY3lw53ggX0etNTM6D+I mC8Q== X-Gm-Message-State: ABuFfohWfEWCjoZmdg3D2ZpWjxOHRD3c/w40ftb3lK/n/e5Jai8FpyqO 3EgeQzQh1s54yWu1EZzq4npMMokD3OzBsCiwyqVTWg== X-Google-Smtp-Source: ACcGV60bHIcmD0AZ0W8Ikd36wRfvFfqJYYpssZVEbMY2CW3V3gaOiOcZLtVY9bl5YQHZNpwP50vQt210seZMaUlGDe4= X-Received: by 2002:a02:508a:: with SMTP id m132-v6mr4634072jab.102.1539348646694; Fri, 12 Oct 2018 05:50:46 -0700 (PDT) MIME-Version: 1.0 References: <1538745911-22484-1-git-send-email-mw@semihalf.com> In-Reply-To: From: Marcin Wojtas Date: Fri, 12 Oct 2018 14:50:34 +0200 Message-ID: To: hao.a.wu@intel.com Cc: edk2-devel-01 , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , Ard Biesheuvel , nadavh@marvell.com, "jsd@semihalf.com" , Tomasz Michalec Subject: Re: [PATCH v2 0/4] SdMmcOverride extension X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 12 Oct 2018 12:50:48 -0000 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable pt., 12 pa=C5=BA 2018 o 14:48 Wu, Hao A napisa=C5=82(a= ): > > > -----Original Message----- > > From: Marcin Wojtas [mailto:mw@semihalf.com] > > Sent: Friday, October 12, 2018 1:33 PM > > To: Wu, Hao A > > Cc: edk2-devel-01; Tian, Feng; Kinney, Michael D; Gao, Liming; Leif Lin= dholm; > > Ard Biesheuvel; nadavh@marvell.com; jsd@semihalf.com; Tomasz Michalec > > Subject: Re: [PATCH v2 0/4] SdMmcOverride extension > > > > Hi Hao, > > > > pt., 12 pa=C5=BA 2018 o 07:25 Wu, Hao A napisa=C5= =82(a): > > > > > > Hi Marcin, > > > > > > Please grant me some time for this series. > > > > > > Since I found that the extension of the SdMmc override protocol (main= ly > > > the 3rd and 4th patch of the series) may have something overlaps with= a > > > (internal) request to configure the driver strength parameter and ope= rating > > > clock frequency of the SD/EMMC devices. > > > > > > For the (driver strength/operating freq) customize, we already have a > > > proposal on the way. So I am wondering if you could grant me some tim= e > > to > > > investigate whether both the cases can be addressed together based on > > your > > > proposed patch. > > > > > > > Sure. I'm only wondering if it's not best to collect all remarks and > > maybe update to v3 both edk2 and edk2-platforms sides (so far the > > issues have been not critical, such as typos, parameters' names, > > etc.). In the meantime you would be able to validate if the solution > > is sufficient for you as well. What do you think? When do you expect > > to be able to look at it vs your internal requirements more deeply? > > > > Best regards, > > Marcin > > I think you can hold the new version of the patch if the feedbacks do not > lead to considerable changes. At this moment, I can barely take time for > the evaluation. I think I will be able to fully shift to this in about 2 > weeks. Does it sound acceptable to you with regard to the urgency level > for the series? > > I will try my best to move up the process. Sorry again for the possible > delay. I will proceed with other remaining items for my platforms and allow myself to ping you about status around end of October :) Best regards, Marcin > > > > > > > > Thanks in advance. > > > > > > Best Regards, > > > Hao Wu > > > > > > > > > > -----Original Message----- > > > > From: Marcin Wojtas [mailto:mw@semihalf.com] > > > > Sent: Friday, October 05, 2018 9:25 PM > > > > To: edk2-devel@lists.01.org > > > > Cc: Tian, Feng; Kinney, Michael D; Gao, Liming; leif.lindholm@linar= o.org; > > Wu, > > > > Hao A; ard.biesheuvel@linaro.org; nadavh@marvell.com; > > > > mw@semihalf.com; jsd@semihalf.com; tm@semihalf.com > > > > Subject: [PATCH v2 0/4] SdMmcOverride extension > > > > > > > > Hi, > > > > > > > > This is the second version of the patchset. Initial one was > > > > interleaved with the fixes, which after split got already merged. > > > > The biggest change is - resigning from the new callbacks > > > > and extending parameter lists of both NotifyPhase and Capability > > > > routines. > > > > > > > > Patches are available in the github: > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open- > > > > platform/commits/sdmmc-override-upstream-r20181005 > > > > > > > > Please note that extending SdMmcOverride protocol was impacting > > > > so far the only user of it (Synquacer controller). In paralel > > > > edk2-platforms patchset, a patch can be found: > > > > ("Silicon/SynQuacer/PlatformDxe: adjust to updated SdMmcOverride") > > > > which immunizes for above and future extensions of the protocol: > > > > https://github.com/MarvellEmbeddedProcessors/edk2-open- > > > > platform/commits/xenon-upstream-r20181005 > > > > > > > > I'm looking forward to the comments and remarks. > > > > > > > > Best regards, > > > > Marcin > > > > > > > > Changelog: > > > > v1 -> v2 > > > > * Rebase onto newest master > > > > * 1/4 [new patch] - preparation for extending NotifyPhase > > > > * 2/4 - UhsSignaling as a part of NotifyPhase > > > > * 3/4 - SwitchClockFreqPost as a part of NotifyPhase > > > > * 4/4 - Allow updating BaseClkFreq via Capability instead of the > > > > independent callback. > > > > > > > > Marcin Wojtas (2): > > > > MdeModulePkg/SdMmcPciHcDxe: Add an optional parameter in > > > > NotifyPhase > > > > MdeModulePkg/SdMmcPciHcDxe: Allow overriding base clock frequency > > > > > > > > Tomasz Michalec (2): > > > > MdeModulePkg/SdMmcPciHcDxe: Add UhsSignaling to SdMmcOverride > > > > protocol > > > > MdeModulePkg/SdMmcPciHcDxe: Add SwitchClockFreqPost to > > > > SdMmcOverride > > > > > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.h | 6 + > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.h | 62 +++++- > > > > MdeModulePkg/Include/Protocol/SdMmcOverride.h | 12 +- > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/EmmcDevice.c | 215 > > > > ++++++++++++++------ > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdDevice.c | 57 +++++- > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHcDxe.c | 18 +- > > > > MdeModulePkg/Bus/Pci/SdMmcPciHcDxe/SdMmcPciHci.c | 108 > > ++++++++- > > > > - > > > > 7 files changed, 383 insertions(+), 95 deletions(-) > > > > > > > > -- > > > > 2.7.4 > > >