From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: mx.groups.io; dkim=pass header.i=@semihalf-com.20150623.gappssmtp.com header.s=20150623 header.b=t36Goy0/; spf=none, err=SPF record not found (domain: semihalf.com, ip: 209.85.161.67, mailfrom: mw@semihalf.com) Received: from mail-yw1-f67.google.com (mail-yw1-f67.google.com [209.85.161.67]) by groups.io with SMTP; Thu, 11 Jul 2019 01:07:39 -0700 Received: by mail-yw1-f67.google.com with SMTP id g19so1645945ywe.2 for ; Thu, 11 Jul 2019 01:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc:content-transfer-encoding; bh=D+/146ctoEY8PCsMVmdrXDzLwYh09huEGSf+MgyrGM4=; b=t36Goy0/l5oztowYBFbJauphK4wg5/jiZ7NA1QcTcOHmCSYgEKr0qUL0wqo3yQArxW i3t7XNzPX7mCxlBnk6AHNta9UCiZSXU6mUb5JOIdGacSD3Lz7tdEtv1BI4bGb0fLwzc7 49NGos1t2klWtm5lc99ebK5UzyCdSLyhnPrE+J4PCMR3JEvhuHxcuu1N9fh25iLV5J/j m4hehsu+4R8uGKyff+9qYfpqPsvwTK4HsPoiW6RMAofX4ignd9yNtDS4Yzjx+xit92pg csjfhxiM5Qt9wK4/YEtL2bSNXmnqoISx+14t4yj6s86WGwLwuEdIr3OYdok8a5qFYzNt pdig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc:content-transfer-encoding; bh=D+/146ctoEY8PCsMVmdrXDzLwYh09huEGSf+MgyrGM4=; b=g3N+PhMAUyGYomZ2z0bCqquyBadh0GLwfJKbaJO9UIfLYCq99hkWYxiTMyF9VgKsBD 3WHJyqd2aywjOa5tpgebkA3MqeIzyQqeOSu0nSbqOJ0419pSCOMEvDtywTh1odKFT1rp XKGBUPRFMwhuVG8uMkqQE4ZpB702vHOgvJ9/zCrJ7mAnqqnVMlTs9f/2VltHDgrVAe4h ZWjaOdIhfnS02XhBk8CxtfPX/l9AWR/Z3MsI6cUoVTahIm2fHJP5XSgeh+A/ui3iCZMp TJWqxV3g4k1l2gAaTfqXUJq/hSxX0eGQRfM7ocuAzEGrEUghfT8eNodxdhbIDb+rbL3t EgVA== X-Gm-Message-State: APjAAAU4DImfjKAhWeJM/IK80n1HVxavJFX6cfhuT+kEcWR+okX+Wqrl dw+68WOnTNRFTKPz0Y+AQrETroNWuz3056MFFh8= X-Google-Smtp-Source: APXvYqwBYmwxHBbQfIZUCrWP+NiaEFmZ03NWQUTckfhNxRk6H4v/uqaGHCj7F7R/quZaG6iHrM+/VI/83Eo6jUV9wTA= X-Received: by 2002:ae9:d610:: with SMTP id r16mr1598125qkk.16.1562832458819; Thu, 11 Jul 2019 01:07:38 -0700 (PDT) MIME-Version: 1.0 References: <1561532654-6277-1-git-send-email-mw@semihalf.com> <20190626093155.bjetr56imew7q74v@bivouac.eciton.net> In-Reply-To: From: "Marcin Wojtas" Date: Thu, 11 Jul 2019 10:07:27 +0200 Message-ID: Subject: Re: [edk2-platforms: PATCH] Marvell/Drivers: XenonDxe: Explicitly disable HS400 To: Leif Lindholm Cc: edk2-devel-groups-io , Ard Biesheuvel , "jsd@semihalf.com" , Grzegorz Jaszczyk , Kostya Porotchkin Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Leif, =C5=9Br., 26 cze 2019 o 11:58 Marcin Wojtas napisa=C5=82(= a): > > Hi Leif, > > =C5=9Br., 26 cze 2019 o 11:31 Leif Lindholm na= pisa=C5=82(a): > > > > On Wed, Jun 26, 2019 at 09:04:14AM +0200, Marcin Wojtas wrote: > > > Ensure that in case of SlowMode or 3.3V operation, > > > also the HS400 capability will be disabled in the > > > SdMmc driver. > > > > > > Contributed-under: TianoCore Contribution Agreement 1.1 > > > > Well done on keeping this tag. But I'm thinking we need to do that > > relicensing sooner rather than later, and drop the tag. > > I left it, as this file is still not 2-clause SPDX tagged. > > > > > > > However, can you clarify what problem this solves? > > > > On another SoC revision, the capability register marks HS400 support > as enabled. However the interface itself is powered with 3.3V and it > turned out that my flags in SdMmcOverride driver did not cover this > case, which resulted in an unsuccessful EmmcSwitchToHS400 () execution > - it shouldn't be done at all. > Did you have a chance to see my explanation? Should I repost? Best regards, Marcin > > / > > Leif > > > > > Signed-off-by: Marcin Wojtas > > > --- > > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h | 1 + > > > Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c | 5 +++-= - > > > 2 files changed, 4 insertions(+), 2 deletions(-) > > > > > > diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h b/Si= licon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > > index 8bf1835..2d7c7f0 100644 > > > --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > > +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdhci.h > > > @@ -82,6 +82,7 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUC= H DAMAGE. > > > #define SDHC_CAP_SDR50 BIT32 > > > #define SDHC_CAP_SDR104 BIT33 > > > #define SDHC_CAP_DDR50 BIT34 > > > +#define SDHC_CAP_HS400 BIT63 > > > #define SDHC_MAX_CURRENT_CAP 0x0048 > > > #define SDHC_FORCE_EVT_AUTO_CMD 0x0050 > > > #define SDHC_FORCE_EVT_ERR_INT 0x0052 > > > diff --git a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverrid= e.c b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > > index 7a9266e..55ebcf8 100644 > > > --- a/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > > +++ b/Silicon/Marvell/Drivers/SdMmc/XenonDxe/XenonSdMmcOverride.c > > > @@ -357,7 +357,8 @@ XenonSdMmcCapability ( > > > Capability &=3D ~(UINT64)(SDHC_CAP_VOLTAGE_33 | SDHC_CAP_VOLTAGE= _30); > > > } else { > > > Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | > > > - SDHC_CAP_SDR50 | SDHC_CAP_VOLTAGE_18); > > > + SDHC_CAP_SDR50 | SDHC_CAP_HS400 | > > > + SDHC_CAP_VOLTAGE_18); > > > } > > > > > > if (!SdMmcDesc.Xenon8BitBusEnabled) { > > > @@ -365,7 +366,7 @@ XenonSdMmcCapability ( > > > } > > > > > > if (SdMmcDesc.XenonSlowModeEnabled) { > > > - Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50); > > > + Capability &=3D ~(UINT64)(SDHC_CAP_SDR104 | SDHC_CAP_DDR50 | SDH= C_CAP_HS400); > > > } > > > > > > Capability &=3D ~(UINT64)(SDHC_CAP_SLOT_TYPE_MASK); > > > -- > > > 2.7.4 > > >