From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-x234.google.com (mail-io0-x234.google.com [IPv6:2607:f8b0:4001:c06::234]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by ml01.01.org (Postfix) with ESMTPS id B0D0A81EEC for ; Thu, 24 Nov 2016 00:01:07 -0800 (PST) Received: by mail-io0-x234.google.com with SMTP id j65so66996421iof.0 for ; Thu, 24 Nov 2016 00:01:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=o36w6Bsg8JdujbdtB9Pw+Xwgxf/cfMnKihzInU7cILQ=; b=AQzm+j5fbj/HtT1aIhTuETgxSV2l12x/L4agh7r7JOiHJP6trC6EuvCQxH9pi6GxZ8 oVViyaiu2yiv/cS95Zg1kOeKpxYHMjq6YL8fdighGL9zRMwPuPEVG/0ZB4dsCzFn1FPb kV3uIlCCOl8k/6fGq5yvcDgXJ9HxAWooxXT67o5p1PEAQJqlh+3UWZf56y371Mc31WZP mr1zuwOpryoA/7eB0yJH87yd4fb73CcX+qHbcwsYZwr2cJYR8F0T5ja65UWSHPpIWdN0 jCRd97eQ1eoYMwQeSpesfGgbYh+ZQFZ6/YRu7NiiNAsJYziby0Yh+ICne3hMktnpH+Sl H+9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=o36w6Bsg8JdujbdtB9Pw+Xwgxf/cfMnKihzInU7cILQ=; b=OMJ/QPa4qVtMDZd9s5MFkZ55rfj1MQQ/R2XoBeMBP9CC0J6xWZczD8ZPL3iSgBD6ra 7ov1gIEO73DhIFrgJUk7CsjtZupm7k3q8FShIZnbD44463AqC48PShizFhUrd7YDTGbt UfdbcLQopmWfOmTgfabgX3XoYR9aQ3e6/eicUto1C47ccy2rX77+WpH35vd+LVeSMITd pZAiKbjqOH3RKBItJ34JwFu2e1xhjAE6oz1mmf4yOozyWp2ACs/q2XTaNCO9qasUJcyW g+maf78skbYJC9D24f7RV3IQawiVrSG/GoCQKVOlWLv8UFi50xbu+cUm4LdGrBstzJHV biEQ== X-Gm-Message-State: AKaTC03i03wavdMrevxRxhRhBzWhLUKyjJHbgsclckEYThM6Gp7KokE2bkfOzzBgULqLLpv09ncwQyRvAaGTYA== X-Received: by 10.36.190.206 with SMTP id i197mr794101itf.70.1479974466848; Thu, 24 Nov 2016 00:01:06 -0800 (PST) MIME-Version: 1.0 Received: by 10.107.25.140 with HTTP; Thu, 24 Nov 2016 00:01:06 -0800 (PST) In-Reply-To: References: <1479974073-29154-1-git-send-email-mw@semihalf.com> From: Marcin Wojtas Date: Thu, 24 Nov 2016 09:01:06 +0100 Message-ID: To: Ard Biesheuvel Cc: edk2-devel-01 , "Tian, Feng" , "Kinney, Michael D" , "Gao, Liming" , Leif Lindholm , =?UTF-8?B?SmFuIETEhWJyb8Wb?= Subject: Re: [PATCH v2] MdeModulePkg/AtaAtapiPassThru: Ensure GHC.AE bit is always set in Ahci X-BeenThere: edk2-devel@lists.01.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: EDK II Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 24 Nov 2016 08:01:07 -0000 Content-Type: text/plain; charset=UTF-8 Hi Ard, 2016-11-24 8:56 GMT+01:00 Ard Biesheuvel : > On 24 November 2016 at 07:54, Marcin Wojtas wrote: >> According to AHCI Spec 1.3 GHC.AE bit description: >> "The implementation of this bit is dependent upon the value of the >> CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and shall >> have a reset value of '0'. If CAP.SAM is '1', then AE shall be read-only >> and shall have a reset value of '1'." >> >> Being in AhciMode, for proper operation it is required, that GHC.AE bit >> is always set, before any other AHCI registers are written to. Current >> AhciMode implementation, both in AhciReset() and AhciModeInitialization() >> functions, set GHC.AE bit only depending on 'CAP.SAM == 0' condition, >> assuming (according to the AHCI spec), that otherwise it has to be set >> anyway. It may however happen, that even if 'CAP.SAM == 1', GHC.AE >> requires updating by software. >> >> This patch enables in AhciMode setting GHC.AE in case its initial value >> is '0'. It fixes AHCI support for Marvell Armada 70x0 and 80x0 SoC >> families. The change is transparent to all other platforms. >> >> Contributed-under: TianoCore Contribution Agreement 1.0 >> Signed-off-by: Marcin Wojtas >> Signed-off-by: Jan Dabros >> >> --- >> Changelog: >> v1 -> v2 >> >> * Instead of doing it uncoditionally, enable setting GHC.AE bit only in >> case its initial value is '0' >> >> --- >> MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c | 21 ++++++++++----------- >> 1 file changed, 10 insertions(+), 11 deletions(-) >> >> diff --git a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c >> index 533d201..4d01c1d 100644 >> --- a/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c >> +++ b/MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AhciMode.c >> @@ -1451,17 +1451,13 @@ AhciReset ( >> { >> UINT64 Delay; >> UINT32 Value; >> - UINT32 Capability; >> >> // >> - // Collect AHCI controller information >> - // >> - Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); >> - >> - // >> - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set >> + // Make sure that GHC.AE bit is set before accessing any AHCI registers. >> // >> - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { >> + Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); >> + >> + if ((Value & EFI_AHCI_GHC_ENABLE) == 0) { >> AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); >> } >> > > If we are ignoring the capability bits now, do we still need to read them? In the context above (AhciReset() function) reading capability is removed. In AhciModeInitialization() however, it has to remain, because of following lines: // // Enable 64-bit DMA support in the PCI layer if this controller // supports it. // if ((Capability & EFI_AHCI_CAP_S64A) != 0) { Which, I can see, were added by you:) Best regards, Marcin > >> @@ -2252,6 +2248,7 @@ AhciModeInitialization ( >> EFI_ATA_COLLECTIVE_MODE *SupportedModes; >> EFI_ATA_TRANSFER_MODE TransferMode; >> UINT32 PhyDetectDelay; >> + UINT32 Value; >> >> if (Instance == NULL) { >> return EFI_INVALID_PARAMETER; >> @@ -2270,11 +2267,13 @@ AhciModeInitialization ( >> // Collect AHCI controller information >> // >> Capability = AhciReadReg (PciIo, EFI_AHCI_CAPABILITY_OFFSET); >> - >> + >> // >> - // Enable AE before accessing any AHCI registers if Supports AHCI Mode Only is not set >> + // Make sure that GHC.AE bit is set before accessing any AHCI registers. >> // >> - if ((Capability & EFI_AHCI_CAP_SAM) == 0) { >> + Value = AhciReadReg(PciIo, EFI_AHCI_GHC_OFFSET); >> + >> + if ((Value & EFI_AHCI_GHC_ENABLE) == 0) { >> AhciOrReg (PciIo, EFI_AHCI_GHC_OFFSET, EFI_AHCI_GHC_ENABLE); >> } >> >> -- >> 1.8.3.1 >>