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Hi Ashish,

This bug was already reported by Ming (who also submitted a patch).

Tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=3236, should
make it into the tree tomorrow.

Thank you for your contribution!

/
    Leif

On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote:
> Incorrect register is being set for configuring interrupt
> priority. Correct register is located in SGI space and not
> in RD space.
>
> Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
> ---
>  ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> index 8ef32b3..3c0bee6 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (
>      }
>
>      MmioAndThenOr32 (
> -      GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
> +      GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * RegOffset),
>        ~(0xff << RegShift),
>        Priority << RegShift
>        );
> --
> 2.7.4
>