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From: "Ashish Singhal" <ashishsingha@nvidia.com>
To: Leif Lindholm <leif@nuviainc.com>
CC: "ardb+tianocore@kernel.org" <ardb+tianocore@kernel.org>,
	"devel@edk2.groups.io" <devel@edk2.groups.io>
Subject: Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority
Thread-Topic: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority
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Date: Mon, 1 Mar 2021 14:48:58 +0000
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References: <0284001c888f058e59853e725d4f02a00840506a.1614273201.git.ashishsingha@nvidia.com>,<20210225200723.GQ1664@vanye>
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I have picked up the patches this morning and they are working as expected.=
 Thanks, Leif.

Thanks
Ashish
________________________________
From: Leif Lindholm <leif@nuviainc.com>
Sent: Thursday, February 25, 2021 1:07 PM
To: Ashish Singhal <ashishsingha@nvidia.com>
Cc: ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; devel@edk2.group=
s.io <devel@edk2.groups.io>
Subject: Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt Priority

External email: Use caution opening links or attachments


Hi Ashish,

This bug was already reported by Ming (who also submitted a patch).

Tracked in https://bugzilla.tianocore.org/show_bug.cgi?id=3D3236, should
make it into the tree tomorrow.

Thank you for your contribution!

/
    Leif

On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote:
> Incorrect register is being set for configuring interrupt
> priority. Correct register is located in SGI space and not
> in RD space.
>
> Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
> ---
>  ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic/Ar=
mGicLib.c
> index 8ef32b3..3c0bee6 100644
> --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c
> @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (
>      }
>
>      MmioAndThenOr32 (
> -      GicCpuRedistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
> +      GicCpuRedistributorBase + ARM_GICR_CTLR_FRAME_SIZE + ARM_GIC_ICDIP=
R + (4 * RegOffset),
>        ~(0xff << RegShift),
>        Priority << RegShift
>        );
> --
> 2.7.4
>

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<div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size=
: 12pt; color: rgb(0, 0, 0);">
I have picked up the patches this morning and they are working as expected.=
 Thanks, Leif.</div>
<div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size=
: 12pt; color: rgb(0, 0, 0);">
<br>
</div>
<div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size=
: 12pt; color: rgb(0, 0, 0);">
Thanks</div>
<div style=3D"font-family: Calibri, Arial, Helvetica, sans-serif; font-size=
: 12pt; color: rgb(0, 0, 0);">
Ashish</div>
<div id=3D"appendonsend"></div>
<hr style=3D"display:inline-block;width:98%" tabindex=3D"-1">
<div id=3D"divRplyFwdMsg" dir=3D"ltr"><font face=3D"Calibri, sans-serif" st=
yle=3D"font-size:11pt" color=3D"#000000"><b>From:</b> Leif Lindholm &lt;lei=
f@nuviainc.com&gt;<br>
<b>Sent:</b> Thursday, February 25, 2021 1:07 PM<br>
<b>To:</b> Ashish Singhal &lt;ashishsingha@nvidia.com&gt;<br>
<b>Cc:</b> ardb+tianocore@kernel.org &lt;ardb+tianocore@kernel.org&gt;; dev=
el@edk2.groups.io &lt;devel@edk2.groups.io&gt;<br>
<b>Subject:</b> Re: [PATCH] ArmPkg/ArmGicLib: Fix setting GICv3 Interrupt P=
riority</font>
<div>&nbsp;</div>
</div>
<div class=3D"BodyFragment"><font size=3D"2"><span style=3D"font-size:11pt;=
">
<div class=3D"PlainText">External email: Use caution opening links or attac=
hments<br>
<br>
<br>
Hi Ashish,<br>
<br>
This bug was already reported by Ming (who also submitted a patch).<br>
<br>
Tracked in <a href=3D"https://bugzilla.tianocore.org/show_bug.cgi?id=3D3236=
">https://bugzilla.tianocore.org/show_bug.cgi?id=3D3236</a>, should<br>
make it into the tree tomorrow.<br>
<br>
Thank you for your contribution!<br>
<br>
/<br>
&nbsp;&nbsp;&nbsp; Leif<br>
<br>
On Thu, Feb 25, 2021 at 10:19:46 -0700, Ashish Singhal wrote:<br>
&gt; Incorrect register is being set for configuring interrupt<br>
&gt; priority. Correct register is located in SGI space and not<br>
&gt; in RD space.<br>
&gt;<br>
&gt; Signed-off-by: Ashish Singhal &lt;ashishsingha@nvidia.com&gt;<br>
&gt; ---<br>
&gt;&nbsp; ArmPkg/Drivers/ArmGic/ArmGicLib.c | 2 +-<br>
&gt;&nbsp; 1 file changed, 1 insertion(+), 1 deletion(-)<br>
&gt;<br>
&gt; diff --git a/ArmPkg/Drivers/ArmGic/ArmGicLib.c b/ArmPkg/Drivers/ArmGic=
/ArmGicLib.c<br>
&gt; index 8ef32b3..3c0bee6 100644<br>
&gt; --- a/ArmPkg/Drivers/ArmGic/ArmGicLib.c<br>
&gt; +++ b/ArmPkg/Drivers/ArmGic/ArmGicLib.c<br>
&gt; @@ -236,7 +236,7 @@ ArmGicSetInterruptPriority (<br>
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; }<br>
&gt;<br>
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; MmioAndThenOr32 (<br>
&gt; -&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GicCpuRedistributorBase + ARM_GIC_ICDI=
PR + (4 * RegOffset),<br>
&gt; +&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; GicCpuRedistributorBase + ARM_GICR_CTL=
R_FRAME_SIZE + ARM_GIC_ICDIPR + (4 * RegOffset),<br>
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; ~(0xff &lt;&lt; RegShift),<b=
r>
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Priority &lt;&lt; RegShift<b=
r>
&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; );<br>
&gt; --<br>
&gt; 2.7.4<br>
&gt;<br>
</div>
</span></font></div>
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