From: Ashish Singhal <ashishsingha@nvidia.com>
Sent: Monday, February 21, 2022 7:42 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; sami.mujawar@arm.com <sami.mujawar@arm.com>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; quic_llindhol@quicinc.com <quic_llindhol@quicinc.com>
Cc: Ashish Singhal <ashishsingha@nvidia.com>
Subject: [PATCH] ArmPkg: Invalidate Instruction Cache On MMU Enable

Even with MMU turned off, instruction cache can speculate
and fetch instructions. This can cause a crash if region
being executed has been modified recently. With this patch,
we ensure that instruction cache is invalidated right after
MMU has been enabled and any potentially stale instruction
fetched earlier has been discarded.

This is specially helpful when the memory attributes of a
region in MMU are being changed and some instructions
operating on the region are prefetched in the instruction
cache.

Signed-off-by: Ashish Singhal <ashishsingha@nvidia.com>
---
ArmPkg/Library/ArmLib/AArch64/AArch64Support.S           | 4 +++-
ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index d3cc1e8671..9648245182 100644
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -89,7 +89,9 @@ ASM_FUNC(ArmEnableMmu)
    dsb     nsh
    isb
    msr     sctlr_el3, x0       // Write back
-4: isb
+4: ic      iallu
+   dsb     sy
+   isb
    ret

diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
index 66ebca571e..56cc2dd73f 100644
--- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
+++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibReplaceEntry.S
@@ -37,6 +37,8 @@

   // re-enable the MMU
   msr   sctlr_el\el, x8
+ ic    iallu
+ dsb   sy
   isb
   .endm

--
2.17.1