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contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: 9m4Vm7BrmATCW4d5azItxfySx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=VZMNeTc1; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Reviewed-by: Michael D Kinney > -----Original Message----- > From: devel@edk2.groups.io On Behalf Of Gerd > Hoffmann > Sent: Tuesday, January 30, 2024 5:05 AM > To: devel@edk2.groups.io > Cc: Michael Roth ; Oliver Steffen > ; Yao, Jiewen ; Gerd Hoffmann > ; Tom Lendacky ; Laszlo > Ersek ; Xu, Min M ; Ard > Biesheuvel ; Aktas, Erdem > > Subject: [edk2-devel] [PATCH v3 3/4] UefiCpuPkg/MtrrLib.h: use cache > type #defines from ArchitecturalMsr.h >=20 > Signed-off-by: Gerd Hoffmann > --- > UefiCpuPkg/Include/Library/MtrrLib.h | 26 ++++++++++++++------------ > 1 file changed, 14 insertions(+), 12 deletions(-) >=20 > diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h > b/UefiCpuPkg/Include/Library/MtrrLib.h > index 86cc1aab3b8e..9d715d50dfb0 100644 > --- a/UefiCpuPkg/Include/Library/MtrrLib.h > +++ b/UefiCpuPkg/Include/Library/MtrrLib.h > @@ -9,6 +9,8 @@ > #ifndef _MTRR_LIB_H_ > #define _MTRR_LIB_H_ >=20 > +#include > + > // > // According to IA32 SDM, MTRRs number and MSR offset are always > consistent > // for IA32 processor family > @@ -82,20 +84,20 @@ typedef struct _MTRR_SETTINGS_ { > // Memory cache types > // > typedef enum { > - CacheUncacheable =3D 0, > - CacheWriteCombining =3D 1, > - CacheWriteThrough =3D 4, > - CacheWriteProtected =3D 5, > - CacheWriteBack =3D 6, > - CacheInvalid =3D 7 > + CacheUncacheable =3D MSR_IA32_MTRR_CACHE_UNCACHEABLE, > + CacheWriteCombining =3D MSR_IA32_MTRR_CACHE_WRITE_COMBINING, > + CacheWriteThrough =3D MSR_IA32_MTRR_CACHE_WRITE_THROUGH, > + CacheWriteProtected =3D MSR_IA32_MTRR_CACHE_WRITE_PROTECTED, > + CacheWriteBack =3D MSR_IA32_MTRR_CACHE_WRITE_BACK, > + CacheInvalid =3D MSR_IA32_MTRR_CACHE_INVALID_TYPE, > } MTRR_MEMORY_CACHE_TYPE; >=20 > -#define MTRR_CACHE_UNCACHEABLE 0 > -#define MTRR_CACHE_WRITE_COMBINING 1 > -#define MTRR_CACHE_WRITE_THROUGH 4 > -#define MTRR_CACHE_WRITE_PROTECTED 5 > -#define MTRR_CACHE_WRITE_BACK 6 > -#define MTRR_CACHE_INVALID_TYPE 7 > +#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE > +#define MTRR_CACHE_WRITE_COMBINING > MSR_IA32_MTRR_CACHE_WRITE_COMBINING > +#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH > +#define MTRR_CACHE_WRITE_PROTECTED > MSR_IA32_MTRR_CACHE_WRITE_PROTECTED > +#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK > +#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE >=20 > typedef struct { > UINT64 BaseAddress; > -- > 2.43.0 >=20 >=20 >=20 >=20 >=20 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. 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