Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT

["Michael D Kinney" <michael.d.kinney@intel.com>]

Acked-by: Michael D Kinney <michael.d.kinney@intel.com>


> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Heng Luo
> Sent: Monday, June 6, 2022 6:07 PM
> To: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; devel@edk2.groups.io
> Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit <ankit.sinha@intel.com>; Kubacki, Michael
> <michael.kubacki@microsoft.com>
> Subject: Re: [edk2-devel] [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate width of CLK duty cycle in FADT
> 
> Reviewed-by: Heng Luo <heng.luo@intel.com>
> 
> > -----Original Message-----
> > From: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>
> > Sent: Tuesday, June 7, 2022 6:51 AM
> > To: devel@edk2.groups.io
> > Cc: Chaganty, Rangasai V <rangasai.v.chaganty@intel.com>; Sinha, Ankit
> > <ankit.sinha@intel.com>; Kubacki, Michael <michael.kubacki@microsoft.com>;
> > Luo, Heng <heng.luo@intel.com>
> > Subject: [edk2-platforms] [PATCH V1 4/4] TigerlakeOpenBoardPkg: Indicate
> > width of CLK duty cycle in FADT
> >
> > Set the location of the DUTY_CYCLE field in the P_CNT register and indicate the
> > width of the clock duty cycle to OS power management
> >
> > Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
> > Cc: Ankit Sinha <ankit.sinha@intel.com>
> > Cc: Michael Kubacki <michael.kubacki@microsoft.com>
> > Cc: Heng Luo <heng.luo@intel.com>
> > Signed-off-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
> > ---
> >  .../TigerlakeURvp/OpenBoardPkgPcd.dsc                  | 10 +++++++++-
> >  1 file changed, 9 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > index ebbbc7b9f9..aba3c8d6d0 100644
> > ---
> > a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc
> > +++
> > b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd
> > +++ .dsc
> > @@ -1,7 +1,7 @@
> >  ## @file
> >  #  PCD configuration build description file for the TigerlakeURvp board.
> >  #
> > -#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
> > +#  Copyright (c) 2021 - 2022, Intel Corporation. All rights
> > +reserved.<BR>
> >  #  SPDX-License-Identifier: BSD-2-Clause-Patent  #  ## @@ -118,6 +118,14 @@
> >    gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000
> >  #!endif
> >    gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000
> > +
> > +  #
> > +  # Set the location of the DUTY_CYCLE field in the P_CNT register  #
> > + and indicate the width of the clock duty cycle to OS power management
> > + #
> > +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyOffset|0x1
> > +  gMinPlatformPkgTokenSpaceGuid.PcdFadtDutyWidth|0x3
> > +
> >  [PcdsFeatureFlag.common]
> >    ######################################
> >    # Edk2 Configuration
> > --
> > 2.27.0.windows.1
> 
> 
> 
> 
>