* Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test [not found] <170A8E16F0EB447C.15571@groups.io> @ 2022-08-12 9:19 ` Zhiguang Liu 2022-08-12 18:12 ` Michael D Kinney 0 siblings, 1 reply; 3+ messages in thread From: Zhiguang Liu @ 2022-08-12 9:19 UTC (permalink / raw) To: devel@edk2.groups.io, Liu, Zhiguang; +Cc: Dong, Eric, Ni, Ray, Kumar, Rahul R Hi all, This patch contains a big C file, containing random number to make it possible to reproduce issue in fuzzy test. If the mail is hard to review, please review from https://github.com/tianocore/edk2/pull/3201 Thanks Zhiguang > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > Zhiguang Liu > Sent: Friday, August 12, 2022 5:14 PM > To: devel@edk2.groups.io > Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric > <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R > <rahul.r.kumar@intel.com> > Subject: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add > host based unit test > > Add host based unit tests for the CpuPageTableLib services. > > Unit test focuses on PageTableMap function, containing two kinds of test > cases: manual test case and fuzzy test case. > Manual test case creates some corner case to test function PageTableMap. > Fuzzy test case generates multiple random memory entries (with random > attribute) as the input of function PageTableMap to get the output > pagetable. Output pagetable will be validated and be parsed to get output > memory entries, and then the input and output memory entries will be > compared to verify the functionality. > > The unit test is not perfect yet. There are options for fuzzy test, and > some of them control the test coverage, and some option are not ready. > Will enhance in the future. > > Cc: Eric Dong <eric.dong@intel.com> > Cc: Ray Ni <ray.ni@intel.com> > Cc: Rahul Kumar <rahul1.kumar@intel.com> > Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> > --- > > diff --git > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > h > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > h > new file mode 100644 > index 0000000000..01d281f9c8 > --- /dev/null > +++ > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > h > @@ -0,0 +1,117 @@ > +/** @file > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef CPU_PAGE_TABLE_SUPPORT_H_ > +#define CPU_PAGE_TABLE_SUPPORT_H_ > + > +#include <stdio.h> > +#include <stdlib.h> > +#include <string.h> > +#include <stdarg.h> > +#include <stddef.h> > +#include <setjmp.h> > +#include <cmocka.h> > +#include <time.h> > + > +#include <Uefi.h> > +#include <Library/BaseLib.h> > +#include <Library/BaseMemoryLib.h> > +#include <Library/DebugLib.h> > +#include <Library/UnitTestLib.h> > +#include <Library/CpuPageTableLib.h> > +#include <Library/MemoryAllocationLib.h> > +#include <Library/UnitTestHostBaseLib.h> > +#include <Library/BaseCryptLib.h> > +#include "../CpuPageTable.h" > + > +#define UNIT_TEST_APP_NAME "Cpu Page Table Lib Unit Tests" > +#define UNIT_TEST_APP_VERSION "1.0" > + > +// > +// Fuzz Options > +// > + > +// > +// Only test one-one mapping case > +// > +#define ONLY_ONE_ONE_MAPPING 0x00000001 > + > +// > +// Change page table without using function PageTableMap, and use the > modified page table as input > +// > +#define MANUAL_CHANGE_PAGE_TABLE 0x00000002 > + > +// > +// Use pre-generated random number array to generate random number > +// > +#define USE_RANDOM_ARRAY 0x00000004 > + > +typedef struct { > + PAGING_MODE PagingMode; > + UINTN TestCount; > + UINTN TestRangeCount; > + UINTN FuzzOption; > +} CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT; > + > +/** > + Fuzzy Test > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseforFuzzyTest ( > + IN UNIT_TEST_CONTEXT Context > + ); > + > +/** > + Init global data > + > + @param[in] MemorySpace Memory space > +**/ > +VOID > +InitGlobalData ( > + UINTN MemorySpace > + ); > + > +/** > + Check if the Page table is valid > + > + @param[in] PageTable The pointer to the page table. > + @param[in] PagingMode The paging mode. > + > + @retval UNIT_TEST_PASSED It is a valid Page Table > +**/ > +UNIT_TEST_STATUS > +IsPageTableValid ( > + IN UINTN PageTable, > + IN PAGING_MODE PagingMode > + ); > + > +/** > + Get max physical adrress supported by specific page mode > + > + @param[in] Mode The paging mode. > + > + @retval max address. > +**/ > +UINT64 > +GetMaxAddress ( > + IN PAGING_MODE Mode > + ); > + > +#endif > diff --git > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > new file mode 100644 > index 0000000000..a0409bc318 > --- /dev/null > +++ > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.c > @@ -0,0 +1,794 @@ > +/** @file > + Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "CpuPageTableLibUnitTest.h" > + > +// ----------------------------------------------------------------------- PageMode-- > TestCount-TestRangeCount---FuzzOptions > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > mTestContextPaging4Level = { Paging4Level, 100, 20, > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > mTestContextPaging4Level1GB = { Paging4Level1GB, 100, 20, > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > mTestContextPaging5Level = { Paging5Level, 100, 20, > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > mTestContextPaging5Level1GB = { Paging5Level1GB, 100, 20, > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > + > +/** > + Check if the input parameters are not supported. > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseForParameter ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + UINTN Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = 0; > + PagingMode = Paging5Level1GB; > + PageTableBufferSize = 0; > + PageTable = 0; > + > + // > + // If the input linear address is not 4K align, it should return invalid > parameter > + // > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_INVALID_PARAMETER); > + > + // > + // If the input PageTableBufferSize is not 4K align, it should return invalid > parameter > + // > + PageTableBufferSize = 10; > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_INVALID_PARAMETER); > + > + // > + // If the input PagingMode is Paging32bit, it should return invalid > parameter > + // > + PageTableBufferSize = 0; > + PagingMode = Paging32bit; > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > RETURN_UNSUPPORTED); > + > + // > + // If the input MapMask is NULL, it should return invalid parameter > + // > + PagingMode = Paging5Level1GB; > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), > RETURN_INVALID_PARAMETER); > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check the case that modifying page table doesn't need extra buffe > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseWhichNoNeedExtraSize ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + UNIT_TEST_STATUS TestStatus; > + > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = 0; > + PagingMode = Paging4Level1GB; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Bits.Present = 1; > + MapAttribute.Bits.Nx = 1; > + MapMask.Bits.Present = 1; > + MapMask.Uint64 = MAX_UINT64; > + > + // > + // Create page table to cover [0, 10M], it should have 5 PTE > + // > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + // > + // call library to cover [0, 4K], because the page table is already cover [0, > 10M], and no attribute change, > + // We assume the fucntion doesn't need to change page table, return > success and output BufferSize is 0 > + // > + Buffer = NULL; > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + // > + // Same range and same attribute, only clear one mask attribute bit > + // We assume the fucntion doesn't need to change page table, return > success and output BufferSize is 0 > + // > + MapMask.Bits.Nx = 0; > + PageTableBufferSize = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + // > + // call library to cover [2M, 4M], while the page table is already cover [0, > 10M], > + // only change one attribute bit, we assume the page table change be > modified even if the > + // input Buffer is NULL, and BufferSize is 0 > + // > + MapAttribute.Bits.Accessed = 1; > + MapMask.Bits.Accessed = 1; > + PageTableBufferSize = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, > &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Test Case that check the case to map [0, 1G] to [8K, 1G+8K] > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCase1Gmapto4K ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + UNIT_TEST_STATUS TestStatus; > + > + // > + // Create Page table to map [0,1G] to [8K, 1G+8K] > + // > + PagingMode = Paging4Level1GB; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Uint64 = (UINT64)SIZE_4KB * 2; > + MapMask.Uint64 = (UINT64)SIZE_4KB * 2; > + MapAttribute.Bits.Present = 1; > + MapMask.Bits.Present = 1; > + MapMask.Uint64 = MAX_UINT64; > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + > + // > + // Page table should be valid. (All reserved bits are zero) > + // > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check if the parent entry has different R/W attribute > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseManualChangeReadWrite ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + IA32_MAP_ENTRY *Map; > + UINTN MapCount; > + IA32_PAGING_ENTRY *PagingEntry; > + VOID *BackupBuffer; > + UINTN BackupPageTableBufferSize; > + > + PagingMode = Paging4Level; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = MAX_UINT64; > + MapAttribute.Bits.Present = 1; > + MapAttribute.Bits.ReadWrite = 1; > + > + // > + // Create Page table to cover [0,2G], with ReadWrite = 1 > + // > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + BackupPageTableBufferSize = PageTableBufferSize; > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES > (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + IsPageTableValid (PageTable, PagingMode); > + > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + IsPageTableValid (PageTable, PagingMode); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Manually change ReadWrite to 0 for non-leaf entry, which covers [0,2G] > + // > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + ExpectedMapAttribute.Bits.ReadWrite = 0; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Copy the page entry structure memory for future compare > + // > + BackupBuffer = AllocateCopyPool (BackupPageTableBufferSize, Buffer); > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > BackupPageTableBufferSize); > + > + // > + // Call library to change ReadWrite to 0 for [0,2M] > + // > + MapAttribute.Bits.ReadWrite = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + IsPageTableValid (PageTable, PagingMode); > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + // > + // There should be 1 range [0, 2G] with ReadWrite = 0 > + // > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // The latest PageTableMap call should change nothing. > + // The memory should be identical before and after the funtion is called. > + // > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > BackupPageTableBufferSize); > + > + // > + // Call library to change ReadWrite to 1 for [0, 2M] > + // > + MapAttribute.Bits.ReadWrite = 1; > + PageTableBufferSize = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + IsPageTableValid (PageTable, PagingMode); > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + // > + // There should be 2 range [0, 2M] with ReadWrite = 1 and [2M, 2G] with > ReadWrite = 0 > + // > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 2); > + > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2MB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2GB - SIZE_2MB); > + ExpectedMapAttribute.Uint64 = SIZE_2MB; > + ExpectedMapAttribute.Bits.ReadWrite = 0; > + ExpectedMapAttribute.Bits.Present = 1; > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check if the needed size is expected > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseManualSizeNotMatch ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + IA32_MAP_ENTRY *Map; > + UINTN MapCount; > + IA32_PAGING_ENTRY *PagingEntry; > + > + PagingMode = Paging4Level; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = MAX_UINT64; > + MapAttribute.Bits.Present = 1; > + MapAttribute.Bits.ReadWrite = 1; > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12; > + // > + // Create Page table to cover [2M-4K, 4M], with ReadWrite = 1 > + // > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > &MapAttribute, &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + IsPageTableValid (PageTable, PagingMode); > + > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + IsPageTableValid (PageTable, PagingMode); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB + SIZE_2MB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Manually change ReadWrite to 0 for 3 level non-leaf entry, which covers > [0,2M] > + // Then the map is: > + // [2M-4K,2M], R/W = 0 > + // [2M ,4M], R/W = 1 > + // > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > // Get 4 level entry > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > >Pnle.Bits.PageTableBaseAddress << 12); // Get 3 level entry > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > >Pnle.Bits.PageTableBaseAddress << 12); // Get 2 level entry > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 2); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + ExpectedMapAttribute.Bits.ReadWrite = 0; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + ExpectedMapAttribute.Bits.ReadWrite = 1; > + ExpectedMapAttribute.Bits.PageTableBaseAddress = SIZE_2MB >> 12; > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s > ReadWrite is already 1 > + // Just need to set [2M-4K,2M], won't need extra size, so the status should > be success > + // > + MapAttribute.Bits.Present = 1; > + MapAttribute.Bits.ReadWrite = 1; > + PageTableBufferSize = 0; > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12; > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check that won't merge entries > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseManualNotMergeEntry ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + UNIT_TEST_STATUS TestStatus; > + > + PagingMode = Paging4Level1GB; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = MAX_UINT64; > + MapAttribute.Bits.Present = 1; > + MapMask.Bits.Present = 1; > + > + // > + // Create Page table to cover [0,4M], and [4M, 1G] is not present > + // > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + // > + // Let Page table to cover [0,1G], we assume it won't use a big 1G entry to > cover whole range > + // It looks like the chioce is not bad, but sometime, we need to keep some > small entry > + // > + PageTableBufferSize = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + MapAttribute.Bits.Accessed = 1; > + PageTableBufferSize = 0; > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, > &MapMask); > + // > + // If it didn't use a big 1G entry to cover whole range, only change [0,2M] > for some attribute won't need extra memory > + // > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check if the parent entry has different Nx attribute > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseManualChangeNx ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UINTN PageTable; > + PAGING_MODE PagingMode; > + VOID *Buffer; > + UINTN PageTableBufferSize; > + IA32_MAP_ATTRIBUTE MapAttribute; > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > + IA32_MAP_ATTRIBUTE MapMask; > + RETURN_STATUS Status; > + IA32_MAP_ENTRY *Map; > + UINTN MapCount; > + IA32_PAGING_ENTRY *PagingEntry; > + UNIT_TEST_STATUS TestStatus; > + > + PagingMode = Paging4Level1GB; > + PageTableBufferSize = 0; > + PageTable = 0; > + Buffer = NULL; > + MapAttribute.Uint64 = 0; > + MapMask.Uint64 = MAX_UINT64; > + MapAttribute.Bits.Present = 1; > + MapAttribute.Bits.Nx = 0; > + > + // > + // Create Page table to cover [0,2G], with Nx = 0 > + // > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > (IA32_MAP_ENTRY))); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Manually change Nx to 1 for non-leaf entry, which covers [0,2G] > + // > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > + PagingEntry->Uint64 = PagingEntry->Uint64 | BIT63; > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > (IA32_MAP_ENTRY))); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + UT_ASSERT_EQUAL (MapCount, 1); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > + ExpectedMapAttribute.Bits.Nx = 1; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + > + // > + // Call library to change Nx to 0 for [0,1G] > + // > + Status = PageTableMap (&PageTable, PagingMode, NULL, > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > &MapMask); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + MapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > (IA32_MAP_ENTRY))); > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + > + // > + // There should be two ranges [0, 1G] with Nx = 0 and [1G, 2G] with Nx = 1 > + // > + UT_ASSERT_EQUAL (MapCount, 2); > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_1GB); > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_1GB); > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_1GB); > + ExpectedMapAttribute.Uint64 = SIZE_1GB; > + ExpectedMapAttribute.Bits.Present = 1; > + ExpectedMapAttribute.Bits.Nx = 1; > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > ExpectedMapAttribute.Uint64); > + return UNIT_TEST_PASSED; > +} > + > +/** > + Initialize the unit test framework, suite, and unit tests for the > + sample unit tests and run the unit tests. > + > + @retval EFI_SUCCESS All test cases were dispatched. > + @retval EFI_OUT_OF_RESOURCES There are not enough resources > available to > + initialize the unit tests. > +**/ > +EFI_STATUS > +EFIAPI > +UefiTestMain ( > + VOID > + ) > +{ > + EFI_STATUS Status; > + UNIT_TEST_FRAMEWORK_HANDLE Framework; > + UNIT_TEST_SUITE_HANDLE ManualTestCase; > + UNIT_TEST_SUITE_HANDLE FuzzyTestCase; > + > + Framework = NULL; > + > + DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, > UNIT_TEST_APP_VERSION)); > + > + // > + // Start setting up the test framework for running the tests. > + // > + Status = InitUnitTestFramework (&Framework, UNIT_TEST_APP_NAME, > gEfiCallerBaseName, UNIT_TEST_APP_VERSION); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status > = %r\n", Status)); > + goto EXIT; > + } > + > + // > + // Populate the Manual Test Cases. > + // > + Status = CreateUnitTestSuite (&ManualTestCase, Framework, "Manual > Test Cases", "CpuPageTableLib.Manual", NULL, NULL); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Manual Test > Cases\n")); > + Status = EFI_OUT_OF_RESOURCES; > + goto EXIT; > + } > + > + AddTestCase (ManualTestCase, "Check if the input parameters are not > supported.", "Manual Test Case1", TestCaseForParameter, NULL, NULL, > NULL); > + AddTestCase (ManualTestCase, "Check the case that modifying page table > doesn't need extra buffer", "Manual Test Case2", > TestCaseWhichNoNeedExtraSize, NULL, NULL, NULL); > + AddTestCase (ManualTestCase, "Check the case to map [0, 1G] to [8K, > 1G+8K]", "Manual Test Case3", TestCase1Gmapto4K, NULL, NULL, NULL); > + AddTestCase (ManualTestCase, "Check won't merge entries", "Manual > Test Case4", TestCaseManualNotMergeEntry, NULL, NULL, NULL); > + AddTestCase (ManualTestCase, "Check if the parent entry has different > ReadWrite attribute", "Manual Test Case5", > TestCaseManualChangeReadWrite, NULL, NULL, NULL); > + AddTestCase (ManualTestCase, "Check if the parent entry has different Nx > attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, > NULL); > + AddTestCase (ManualTestCase, "Check if the needed size is expected", > "Manual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); > + > + // > + // Populate the Fuzzy Test Cases. > + // > + Status = CreateUnitTestSuite (&FuzzyTestCase, Framework, "Fuzzy Test > Cases", "CpuPageTableLib.Fuzzy", NULL, NULL); > + if (EFI_ERROR (Status)) { > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Fuzzy Test > Cases\n")); > + Status = EFI_OUT_OF_RESOURCES; > + goto EXIT; > + } > + > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level", "Fuzzy Test > Case1", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging4Level); > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level1G", "Fuzzy Test > Case2", TestCaseforFuzzyTest, NULL, NULL, > &mTestContextPaging4Level1GB); > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level", "Fuzzy Test > Case3", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging5Level); > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level1G", "Fuzzy Test > Case4", TestCaseforFuzzyTest, NULL, NULL, > &mTestContextPaging5Level1GB); > + > + // > + // Execute the tests. > + // > + Status = RunAllTestSuites (Framework); > + > +EXIT: > + if (Framework) { > + FreeUnitTestFramework (Framework); > + } > + > + return Status; > +} > + > +/** > + Standard POSIX C entry point for host based unit test execution. > + > + @param Argc Number of arguments. > + @param Argv Array of arguments. > + > + @return Test application exit code. > +**/ > +INT32 > +main ( > + INT32 Argc, > + CHAR8 *Argv[] > + ) > +{ > + InitGlobalData (52); > + return UefiTestMain (); > +} > diff --git > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.inf > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.inf > new file mode 100644 > index 0000000000..2854df46d3 > --- /dev/null > +++ > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > Host.inf > @@ -0,0 +1,42 @@ > +## @file > +# Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class > +# > +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +## > + > +[Defines] > + INF_VERSION = 0x00010006 > + BASE_NAME = CpuPageTableLibUnitTestHost > + FILE_GUID = D8DC32C2-7272-43A8-B145-1723BED8E119 > + MODULE_TYPE = HOST_APPLICATION > + VERSION_STRING = 1.0 > + > +# > +# The following information is for reference only and not required by the > build tools. > +# > +# VALID_ARCHITECTURES = IA32 X64 > +# > + > +[Sources] > + CpuPageTableLibUnitTestHost.c > + FuzzyTest.c > + TestHelper.c > + RandomNumber.c > + FuzzyTest.h > + CpuPageTableLibUnitTest.h > + > +[Packages] > + MdePkg/MdePkg.dec > + UefiCpuPkg/UefiCpuPkg.dec > + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec > + CryptoPkg/CryptoPkg.dec > + > +[LibraryClasses] > + BaseLib > + BaseMemoryLib > + DebugLib > + CpuPageTableLib > + UnitTestLib > + MemoryAllocationLib > + BaseCryptLib > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > new file mode 100644 > index 0000000000..05ab66d406 > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > @@ -0,0 +1,926 @@ > +/** @file > + Fuzzy test case for Unit tests of the CpuPageTableLib instance of the > CpuPageTableLib class > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "CpuPageTableLibUnitTest.h" > +#include "FuzzyTest.h" > + > +UINTN RandomNumber = 0; > +extern IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > +extern IA32_PAGING_ENTRY mValidMaskLeaf[6]; > +extern IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > +UINTN mFuzzOption; > +IA32_MAP_ATTRIBUTE mSupportedBit; > +extern UINTN mNumberCount; > +extern UINT8 mNumbers[]; > +UINTN mNumberIndex; > +UINT64 AlignedTable[] = { > + ~((UINT64)SIZE_4KB - 1), > + ~((UINT64)SIZE_2MB - 1), > + ~((UINT64)SIZE_1GB - 1) > +}; > + > +/** > + Generates a pseudorandom byte stream of the specified size. > + > + Return FALSE to indicate this interface is not supported. > + > + @param[out] Output Pointer to buffer to receive random value. > + @param[in] Size Size of random bytes to generate. > + > + @retval TRUE Always return TRUE > + > +**/ > +BOOLEAN > +EFIAPI > +RandomBytesUsingArray ( > + OUT UINT8 *Output, > + IN UINTN Size > + ) > +{ > + UINTN Index; > + > + for (Index = 0; Index < Size; Index++) { > + if (mNumberIndex >= mNumberCount) { > + mNumberIndex = 0; > + } > + > + Output[Index] = mNumbers[mNumberIndex]; > + mNumberIndex++; > + } > + > + return TRUE; > +} > + > +/** > + Generates a pseudorandom byte stream of the specified size. > + > + Return FALSE to indicate this interface is not supported. > + > + @param[out] Output Pointer to buffer to receive random value. > + @param[in] Size Size of random bytes to generate. > + > + @retval TRUE Pseudorandom byte stream generated successfully. > + @retval FALSE Pseudorandom number generator fails > +**/ > +BOOLEAN > +EFIAPI > +LocalRandomBytes ( > + OUT UINT8 *Output, > + IN UINTN Size > + ) > +{ > + if (mFuzzOption & USE_RANDOM_ARRAY) { > + return RandomBytesUsingArray (Output, Size); > + } else { > + return RandomBytes (Output, Size); > + } > +} > + > +/** > + Return a random boolean. > + > + @return boolean > +**/ > +BOOLEAN > +RandomBoolean ( > + VOID > + ) > +{ > + BOOLEAN Value; > + > + LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); > + return Value%2; > +} > + > +/** > + Return a 32bit random number. > + > + @param Start Start of the random number range. > + @param Limit Limit of the random number range, and return value can be > Limit. > + @return 32bit random number > +**/ > +UINT32 > +Random32 ( > + UINT32 Start, > + UINT32 Limit > + ) > +{ > + UINT64 Value; > + > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > + return (UINT32)(Value % (Limit - Start + 1)) + Start; > +} > + > +/** > + Return a 64bit random number. > + > + @param Start Start of the random number range. > + @param Limit Limit of the random number range, and return value can be > Limit. > + @return 64bit random number > +**/ > +UINT64 > +Random64 ( > + UINT64 Start, > + UINT64 Limit > + ) > +{ > + UINT64 Value; > + > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > + if (Limit - Start == MAX_UINT64) { > + return (UINT64)(Value); > + } > + > + return (UINT64)(Value % (Limit - Start + 1)) + Start; > +} > + > +/** > + Check if the Page table entry is valid > + > + @param[in] PagingEntry The entry in page table to verify > + @param[in] Level the level of PagingEntry. > + @param[in] MaxLeafLevel Max leaf entry level. > + @param[in] LinearAddress The linear address verified. > + > + @retval Leaf entry. > +**/ > +UNIT_TEST_STATUS > +ValidateAndRandomeModifyPageTablePageTableEntry ( > + IN IA32_PAGING_ENTRY *PagingEntry, > + IN UINTN Level, > + IN UINTN MaxLeafLevel, > + IN UINT64 Address > + ) > +{ > + UINT64 Index; > + UINT64 TempPhysicalBase; > + IA32_PAGING_ENTRY *ChildPageEntry; > + UNIT_TEST_STATUS Status; > + > + if (PagingEntry->Pce.Present == 0) { > + return UNIT_TEST_PASSED; > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > mValidMaskLeafFlag[Level].Uint64) { > + // > + // It is a Leaf > + // > + if (Level > MaxLeafLevel) { > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry- > >Uint64) { > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > + } > + > + if ((RandomNumber < 100) && RandomBoolean ()) { > + RandomNumber++; > + if (Level == 1) { > + TempPhysicalBase = PagingEntry->Pte4K.Bits.PageTableBaseAddress; > + } else { > + TempPhysicalBase = PagingEntry->PleB.Bits.PageTableBaseAddress; > + } > + > + PagingEntry->Uint64 = (Random64 (0, MAX_UINT64) & > mValidMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; > + PagingEntry->Pte4K.Bits.Present = 1; > + if (Level == 1) { > + PagingEntry->Pte4K.Bits.PageTableBaseAddress = TempPhysicalBase; > + } else { > + PagingEntry->PleB.Bits.PageTableBaseAddress = TempPhysicalBase; > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != > PagingEntry->Uint64) { > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > + } > + } > + > + return UNIT_TEST_PASSED; > + } > + > + // > + // Not a leaf > + // > + UT_ASSERT_NOT_EQUAL (Level, 1); > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > PagingEntry->Uint64) { > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, which > reserved bit is set \n", Level, PagingEntry->Uint64)); > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > + } > + > + if ((RandomNumber < 100) && RandomBoolean ()) { > + RandomNumber++; > + TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress; > + > + PagingEntry->Uint64 = Random64 (0, MAX_UINT64) & > mValidMaskNoLeaf[Level].Uint64; > + PagingEntry->Pnle.Bits.Present = 1; > + PagingEntry->Pnle.Bits.PageTableBaseAddress = TempPhysicalBase; > + ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) != > mValidMaskLeafFlag[Level].Uint64); > + } > + > + ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry- > >Pnle.Bits.PageTableBaseAddress) << 12); > + for (Index = 0; Index < 512; Index++) { > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + > (Index<<(9*(Level-1) + 3))); > + if (Status != UNIT_TEST_PASSED) { > + return Status; > + } > + } > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check if the Page table is valid > + > + @param[in] PageTable The pointer to the page table. > + @param[in] PagingMode The paging mode. > + > + @retval UNIT_TEST_PASSED It is a valid Page Table > +**/ > +UNIT_TEST_STATUS > +ValidateAndRandomeModifyPageTable ( > + IN UINTN PageTable, > + IN PAGING_MODE PagingMode > + ) > +{ > + UINTN MaxLevel; > + UINTN MaxLeafLevel; > + UINT64 Index; > + UNIT_TEST_STATUS Status; > + IA32_PAGING_ENTRY *PagingEntry; > + > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > (PagingMode >= PagingModeMax)) { > + // > + // 32bit paging is never supported. > + // PAE paging will be supported later. > + // > + return UNIT_TEST_ERROR_TEST_FAILED; > + } > + > + MaxLeafLevel = (UINT8)PagingMode; > + MaxLevel = (UINT8)(PagingMode >> 8); > + > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > + for (Index = 0; Index < 512; Index++) { > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3)); > + if (Status != UNIT_TEST_PASSED) { > + return Status; > + } > + } > + > + return Status; > +} > + > +/** > + Generate single random map entry. > + The map entry can be the input of function PageTableMap > + the LinearAddress and length is aligned to aligned table. > + > + @param MaxAddress Max Address. > + @param MapEntrys Output MapEntrys contains all parameter as input of > function PageTableMap > +**/ > +VOID > +GenerateSingleRandomMapEntry ( > + IN UINT64 MaxAddress, > + IN OUT MAP_ENTRYS *MapEntrys > + ) > +{ > + UINTN MapsIndex; > + UINT64 FormerLinearAddress; > + UINT64 FormerLinearAddressBottom; > + UINT64 FormerLinearAddressTop; > + > + MapsIndex = MapEntrys->Count; > + > + ASSERT (MapsIndex < MapEntrys->MaxCount); > + // > + // use AlignedTable to avoid that a random number can be very hard to be > 1G or 2M aligned > + // > + if ((MapsIndex != 0) && (RandomBoolean ())) { > + FormerLinearAddress = MapEntrys->Maps[Random32 (0, > (UINT32)MapsIndex-1)].LinearAddress; > + if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { > + FormerLinearAddressBottom = 0; > + } else { > + FormerLinearAddressBottom = FormerLinearAddress - 2 * > (UINT64)SIZE_1GB; > + } > + > + if (FormerLinearAddress + 2 * (UINT64)SIZE_1GB > MaxAddress) { > + FormerLinearAddressTop = MaxAddress; > + } else { > + FormerLinearAddressTop = FormerLinearAddress + 2 * > (UINT64)SIZE_1GB; > + } > + > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 > (FormerLinearAddressBottom, FormerLinearAddressTop) & > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > + } else { > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 (0, > MaxAddress) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > + } > + > + // > + // To have better performance, limit the size less than 10G > + // > + MapEntrys->Maps[MapsIndex].Length = Random64 (0, MIN (MaxAddress > - MapEntrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > + > + if ((MapsIndex != 0) && (RandomBoolean ())) { > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = MapEntrys- > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = MapEntrys- > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; > + } else { > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = Random64 (0, > MAX_UINT64) & mSupportedBit.Uint64; > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = Random64 (0, > MAX_UINT64) & mSupportedBit.Uint64; > + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey != 0) { > + MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey = 0xF; > + } > + } > + > + if (mFuzzOption & ONLY_ONE_ONE_MAPPING) { > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = > MapEntrys->Maps[MapsIndex].LinearAddress >> 12; > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = > 0xFFFFFFFFFF; > + } else { > + // > + // Todo: If the mask bit for base address is zero, when dump the > pagetable, every entry mapping to physical address zeor. > + // This means the map count will be a large number, and impossible to > finish in proper time. > + // Need to avoid such case when remove the fuzzy option > ONLY_ONE_ONE_MAPPING > + // > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = > (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, > ARRAY_SIZE (AlignedTable) -1)])>> 12; > + if (RandomBoolean ()) { > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0; > + } > + } > + > + MapEntrys->Count += 1; > +} > + > +/** > + Compare the attribute for one point. > + MapEntrys records every memory ranges that is used as input > + Map and MapCount are gotten from Page table > + Compare if this point have same attribute. > + > + @param[in] Address Address of one Point. > + @param[in] MapEntrys Record every memory ranges that is used as > input > + @param[in] Map Pointer to an array that describes multiple linear > address ranges. > + @param[in] MapCount Pointer to a UINTN that hold the number of > entries in the Map. > + @param[in] InitMap Pointer to an array that describes init map entries. > + @param[in] InitMapCount Pointer to a UINTN that hold the number of init > map entries. > + > + @retval TRUE At least one byte of data is available to be read > + @retval FALSE No data is available to be read > +**/ > +BOOLEAN > +CompareEntrysforOnePoint ( > + IN UINT64 Address, > + IN MAP_ENTRYS *MapEntrys, > + IN IA32_MAP_ENTRY *Map, > + IN UINTN MapCount, > + IN IA32_MAP_ENTRY *InitMap, > + IN UINTN InitMapCount > + ) > +{ > + UINTN Index; > + IA32_MAP_ATTRIBUTE AttributeInInitMap; > + IA32_MAP_ATTRIBUTE AttributeInMap; > + IA32_MAP_ATTRIBUTE AttributeInMapEntrys; > + IA32_MAP_ATTRIBUTE MaskInMapEntrys; > + > + AttributeInMap.Uint64 = 0; > + AttributeInMapEntrys.Uint64 = 0; > + AttributeInInitMap.Uint64 = 0; > + MaskInMapEntrys.Uint64 = 0; > + // > + // Assume every entry in maps does not overlap with each other > + // > + for (Index = 0; Index < MapCount; Index++) { > + if ((Address >= Map[Index].LinearAddress) && (Address < > (Map[Index].LinearAddress + Map[Index].Length))) { > + AttributeInMap.Uint64 = (Map[Index].Attribute.Uint64 & > mSupportedBit.Uint64); > + AttributeInMap.Bits.PageTableBaseAddress = ((Address - > Map[Index].LinearAddress) >> 12) + > Map[Index].Attribute.Bits.PageTableBaseAddress; > + break; > + } > + } > + > + // > + // Assume every entry in maps does not overlap with each other > + // > + for (Index = 0; Index < InitMapCount; Index++) { > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > + AttributeInInitMap.Uint64 = (InitMap[Index].Attribute.Uint64 > & mSupportedBit.Uint64); > + AttributeInInitMap.Bits.PageTableBaseAddress = ((Address - > InitMap[Index].LinearAddress) >> 12) + > InitMap[Index].Attribute.Bits.PageTableBaseAddress; > + break; > + } > + } > + > + AttributeInMapEntrys.Uint64 = AttributeInInitMap.Uint64; > + > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; Index++) { > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && (Address < > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > >Maps[Index].Length))) { > + if (AttributeInMapEntrys.Bits.Present == 0) { > + AttributeInMapEntrys.Uint64 = 0; > + MaskInMapEntrys.Uint64 = 0; > + } > + > + MaskInMapEntrys.Uint64 |= MapEntrys->Maps[Index].Mask.Uint64; > + AttributeInMapEntrys.Uint64 &= (~MapEntrys- > >Maps[Index].Mask.Uint64); > + AttributeInMapEntrys.Uint64 |= (MapEntrys- > >Maps[Index].Attribute.Uint64 & MapEntrys->Maps[Index].Mask.Uint64); > + if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress != 0) { > + AttributeInMapEntrys.Bits.PageTableBaseAddress = ((Address - > MapEntrys->Maps[Index].LinearAddress) >> 12) + MapEntrys- > >Maps[Index].Attribute.Bits.PageTableBaseAddress; > + } > + } > + } > + > + if (AttributeInMap.Bits.Present == 0) { > + if (AttributeInMapEntrys.Bits.Present == 0) { > + return TRUE; > + } > + } > + > + if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) != > (AttributeInMapEntrys.Uint64 & MaskInMapEntrys.Uint64)) { > + DEBUG ((DEBUG_INFO, "======detailed information begin=====\n")); > + DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point > with linear address: 0x%lx\n", Address)); > + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute > 0x%lx, and map to physical address 0x%lx\n", > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMap) & > MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBaseAddress)); > + DEBUG ((DEBUG_INFO, "While according to inputs, the point should > Attribute 0x%lx, and should map to physical address 0x%lx\n", > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMapEntrys) & > MaskInMapEntrys.Uint64, > AttributeInMapEntrys.Bits.PageTableBaseAddress)); > + DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", > MaskInMapEntrys.Uint64)); > + > + if (MapEntrys->InitCount != 0) { > + DEBUG ((DEBUG_INFO, "Below is the initialization status:\n")); > + for (Index = 0; Index < InitMapCount; Index++) { > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > + DEBUG ((DEBUG_INFO, " *")); > + } else { > + DEBUG ((DEBUG_INFO, " ")); > + } > + > + DEBUG ((DEBUG_INFO, " %02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > InitMap[Index].LinearAddress, InitMap[Index].LinearAddress + > InitMap[Index].Length, InitMap[Index].Attribute.Uint64)); > + } > + } > + > + DEBUG ((DEBUG_INFO, "Below is the inputs:\n")); > + DEBUG ((DEBUG_INFO, " Index: {LinearAddress, LinearLimit, Mask, > Attribute}\n")); > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; Index++) > { > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && (Address < > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > >Maps[Index].Length))) { > + DEBUG ((DEBUG_INFO, " *")); > + } else { > + DEBUG ((DEBUG_INFO, " ")); > + } > + > + DEBUG (( > + DEBUG_INFO, > + " %02d: {0x%lx, 0x%lx, 0x%lx,0x%lx}\n", > + Index, > + MapEntrys->Maps[Index].LinearAddress, > + MapEntrys->Maps[Index].LinearAddress + MapEntrys- > >Maps[Index].Length, > + MapEntrys->Maps[Index].Mask.Uint64, > + MapEntrys->Maps[Index].Attribute.Uint64 > + )); > + } > + > + DEBUG ((DEBUG_INFO, "Below is the dumped from pagetable:\n")); > + for (Index = 0; Index < MapCount; Index++) { > + if ((Address >= Map[Index].LinearAddress) && (Address < > (Map[Index].LinearAddress + Map[Index].Length))) { > + DEBUG ((DEBUG_INFO, " *")); > + } else { > + DEBUG ((DEBUG_INFO, " ")); > + } > + > + DEBUG ((DEBUG_INFO, "%02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > Map[Index].LinearAddress, Map[Index].LinearAddress + Map[Index].Length, > Map[Index].Attribute.Uint64)); > + } > + > + DEBUG ((DEBUG_INFO, "======detailed information done=====\n")); > + return FALSE; > + } > + > + return TRUE; > +} > + > +/** > + Append key point of a given address to Buffer > + if buffer is NULL, only count needed count > + > + @param[in, out] Buffer Buffer to contains all key point. > + @param[in, out] Count Count of the key point. > + @param[in] Address given address > +**/ > +VOID > +AppendKeyPointToBuffer ( > + IN OUT UINT64 *Buffer, > + IN OUT UINTN *Count, > + IN UINT64 Address > + ) > +{ > + if ( Buffer != NULL) { > + Buffer[*Count] = Address; > + (*Count)++; > + Buffer[*Count] = Address+1; > + (*Count)++; > + Buffer[*Count] = Address-1; > + (*Count)++; > + } else { > + (*Count) = (*Count) +3; > + } > +} > + > +/** > + Get all key points from a buffer > + if buffer is NULL, only count needed count > + > + @param[in] MapEntrys Record every memory ranges that is used as > input > + @param[in] Map Pointer to an array that describes multiple linear > address ranges. > + @param[in] MapCount Pointer to a UINTN that hold the actual number > of entries in the Map. > + @param[in, out] Buffer Buffer to contains all key point. > + @param[in, out] Count Count of the key point. > +**/ > +VOID > +GetKeyPointList ( > + IN MAP_ENTRYS *MapEntrys, > + IN IA32_MAP_ENTRY *Map, > + IN UINTN MapCount, > + IN OUT UINT64 *Buffer, > + IN OUT UINTN *Count > + ) > +{ > + UINTN TemCount; > + UINTN Index1; > + UINTN Index2; > + > + TemCount = 0; > + > + for (Index1 = 0; Index1 < MapEntrys->Count; Index1++) { > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > >Maps[Index1].LinearAddress); > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > >Maps[Index1].LinearAddress + MapEntrys->Maps[Index1].Length); > + } > + > + for (Index2 = 0; Index2 < MapCount; Index2++) { > + if (Buffer != NULL) { > + for (Index1 = 0; Index1 < TemCount; Index1++) { > + if (Buffer[Index1] == Map[Index2].LinearAddress) { > + break; > + } > + } > + > + if (Index1 < TemCount) { > + continue; > + } > + } > + > + AppendKeyPointToBuffer (Buffer, &TemCount, > Map[Index2].LinearAddress); > + } > + > + for (Index2 = 0; Index2 < MapCount; Index2++) { > + if (Buffer != NULL) { > + for (Index1 = 0; Index1 < TemCount; Index1++) { > + if (Buffer[Index1] == (Map[Index2].LinearAddress + > Map[Index2].Length)) { > + break; > + } > + } > + > + if (Index1 < TemCount) { > + continue; > + } > + } > + > + AppendKeyPointToBuffer (Buffer, &TemCount, > Map[Index2].LinearAddress + Map[Index2].Length); > + } > + > + *Count = TemCount; > +} > + > +/** > + Generate random one range with randome attribute, and add it into > pagetable > + Compare the key point has same attribute > + > + @param[in, out] PageTable The pointer to the page table to update, or > pointer to NULL if a new page table is to be created. > + @param[in] PagingMode The paging mode. > + @param[in] MaxAddress Max Address. > + @param[in] MapEntrys Record every memory ranges that is used as > input > + @param[in] PagesRecord Used to record memory usage for page table. > + @param[in] InitMap Pointer to an array that describes init map > entries. > + @param[in] InitMapCount Pointer to a UINTN that hold the number of > init map entries. > + > + @retval UNIT_TEST_PASSED The test is successful. > +**/ > +UNIT_TEST_STATUS > +SingleMapEntryTest ( > + IN OUT UINTN *PageTable, > + IN PAGING_MODE PagingMode, > + IN UINT64 MaxAddress, > + IN MAP_ENTRYS *MapEntrys, > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > + IN IA32_MAP_ENTRY *InitMap, > + IN UINTN InitMapCount > + ) > +{ > + UINTN MapsIndex; > + RETURN_STATUS Status; > + UINTN PageTableBufferSize; > + VOID *Buffer; > + IA32_MAP_ENTRY *Map; > + UINTN MapCount; > + UINTN Index; > + UINTN KeyPointCount; > + UINTN NewKeyPointCount; > + UINT64 *KeyPointBuffer; > + UINTN Level; > + UINT64 Value; > + UNIT_TEST_STATUS TestStatus; > + > + MapsIndex = MapEntrys->Count; > + > + GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); > + > + PageTableBufferSize = 0; > + Status = PageTableMap ( > + PageTable, > + PagingMode, > + NULL, > + &PageTableBufferSize, > + MapEntrys->Maps[MapsIndex].LinearAddress, > + MapEntrys->Maps[MapsIndex].Length, > + &MapEntrys->Maps[MapsIndex].Attribute, > + &MapEntrys->Maps[MapsIndex].Mask > + ); > + if (PageTableBufferSize != 0) { > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + > + // > + // Allocate memory for Page table > + // Note the memory is used in one complete fuzzy test. > + // > + Buffer = PagesRecord->AllocatePagesForPageTable (PagesRecord, > EFI_SIZE_TO_PAGES (PageTableBufferSize)); > + UT_ASSERT_NOT_EQUAL (Buffer, NULL); > + Status = PageTableMap ( > + PageTable, > + PagingMode, > + Buffer, > + &PageTableBufferSize, > + MapEntrys->Maps[MapsIndex].LinearAddress, > + MapEntrys->Maps[MapsIndex].Length, > + &MapEntrys->Maps[MapsIndex].Attribute, > + &MapEntrys->Maps[MapsIndex].Mask > + ); > + } > + > + if (Status != RETURN_SUCCESS ) { > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + } > + > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + TestStatus = IsPageTableValid (*PageTable, PagingMode); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + MapCount = 0; > + Status = PageTableParse (*PageTable, PagingMode, NULL, &MapCount); > + if (MapCount != 0) { > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + > + // > + // Allocate memory for Maps > + // Note the memory is only used in this one Single MapEntry Test > + // > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof > (IA32_MAP_ENTRY))); > + ASSERT (Map != NULL); > + Status = PageTableParse (*PageTable, PagingMode, Map, &MapCount); > + } > + > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + > + // > + // Allocate memory to record all key point > + // Note the memory is only used in this one Single MapEntry Test > + // > + KeyPointCount = 0; > + GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); > + KeyPointBuffer = AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * > sizeof (UINT64))); > + ASSERT (KeyPointBuffer != NULL); > + NewKeyPointCount = 0; > + GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, > &NewKeyPointCount); > + > + // > + // Compare all key point's attribute > + // > + for (Index = 0; Index < NewKeyPointCount; Index++) { > + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, > MapCount, InitMap, InitMapCount)) { > + DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); > + DEBUG ((DEBUG_INFO, "Index = %d KeyPointBuffer[Index] = 0x%lx\n", > Index, KeyPointBuffer[Index])); > + Value = GetEntryFromPageTable (*PageTable, PagingMode, > KeyPointBuffer[Index], &Level); > + DEBUG ((DEBUG_INFO, "From Page table, this key point is in level %d > entry, with entry value is 0x%lx\n", Level, Value)); > + UT_ASSERT_TRUE (FALSE); > + } > + } > + > + FreePages (KeyPointBuffer, EFI_SIZE_TO_PAGES (KeyPointCount * sizeof > (UINT64))); > + if (MapCount != 0) { > + FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof > (IA32_MAP_ENTRY))); > + } > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Allocate page and record the information in PagesRecord > + > + @param[in] PagesRecord Point to a struct to record memory usage > + @param[in] Pages Page count needed to allocate > + > + @return A pointer to the allocated buffer or NULL if allocation fails. > +**/ > +VOID * > +EFIAPI > +RecordAllocatePages ( > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > + IN UINTN Pages > + ) > +{ > + VOID *Buffer; > + > + Buffer = NULL; > + if (PagesRecord->Count < PagesRecord->MaxCount) { > + Buffer = AllocatePages (Pages); > + PagesRecord->Records[PagesRecord->Count].Buffer = Buffer; > + PagesRecord->Records[PagesRecord->Count].Pages = Pages; > + PagesRecord->Count++; > + } > + > + ASSERT (Buffer != NULL); > + > + return Buffer; > +} > + > +/** > + The function is a whole fuzzy test, it will call SingleMapEntryTest for > ExpctedEntryNumber times > + > + @param[in] ExpctedEntryNumber The count of random entry > + @param[in] PagingMode The paging mode. > + > + @retval UNIT_TEST_PASSED The test is successful. > +**/ > +UNIT_TEST_STATUS > +MultipleMapEntryTest ( > + IN UINTN ExpctedEntryNumber, > + IN PAGING_MODE PagingMode > + ) > +{ > + UINTN PageTable; > + UINT64 MaxAddress; > + MAP_ENTRYS *MapEntrys; > + ALLOCATE_PAGE_RECORDS *PagesRecord; > + UINTN Index; > + UNIT_TEST_STATUS TestStatus; > + RETURN_STATUS Status; > + IA32_MAP_ENTRY *InitMap; > + UINTN InitMapCount; > + > + MaxAddress = GetMaxAddress (PagingMode); > + PageTable = 0; > + MapEntrys = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > (MAP_ENTRY) + sizeof (MAP_ENTRYS))); > + ASSERT (MapEntrys != NULL); > + MapEntrys->Count = 0; > + MapEntrys->InitCount = 0; > + MapEntrys->MaxCount = 1000; > + PagesRecord = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > + ASSERT (PagesRecord != NULL); > + PagesRecord->Count = 0; > + PagesRecord->MaxCount = 1000; > + PagesRecord->AllocatePagesForPageTable = RecordAllocatePages; > + > + if (mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) { > + ExpctedEntryNumber = ExpctedEntryNumber/2; > + } > + > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > + TestStatus = SingleMapEntryTest ( > + &PageTable, > + PagingMode, > + MaxAddress, > + MapEntrys, > + PagesRecord, > + NULL, > + 0 > + ); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + } > + > + if ((mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) != 0) { > + MapEntrys->InitCount = ExpctedEntryNumber; > + TestStatus = ValidateAndRandomeModifyPageTable (PageTable, > PagingMode); > + RandomNumber = 0; > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + > + InitMapCount = 0; > + Status = PageTableParse (PageTable, PagingMode, NULL, > &InitMapCount); > + if (InitMapCount != 0) { > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > + > + // > + // Allocate memory for Maps > + // Note the memory is only used in this one Single MapEntry Test > + // > + InitMap = AllocatePages (EFI_SIZE_TO_PAGES (InitMapCount * sizeof > (IA32_MAP_ENTRY))); > + ASSERT (InitMap != NULL); > + Status = PageTableParse (PageTable, PagingMode, InitMap, > &InitMapCount); > + } > + > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > + TestStatus = SingleMapEntryTest ( > + &PageTable, > + PagingMode, > + MaxAddress, > + MapEntrys, > + PagesRecord, > + InitMap, > + InitMapCount > + ); > + if (TestStatus != UNIT_TEST_PASSED) { > + return TestStatus; > + } > + } > + > + if (InitMapCount != 0) { > + FreePages (InitMap, EFI_SIZE_TO_PAGES (InitMapCount*sizeof > (IA32_MAP_ENTRY))); > + } > + } > + > + FreePages ( > + MapEntrys, > + EFI_SIZE_TO_PAGES (1000*sizeof (MAP_ENTRY) + sizeof (MAP_ENTRYS)) > + ); > + > + for (Index = 0; Index < PagesRecord->Count; Index++) { > + FreePages (PagesRecord->Records[Index].Buffer, PagesRecord- > >Records[Index].Pages); > + } > + > + FreePages (PagesRecord, EFI_SIZE_TO_PAGES (1000*sizeof > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Fuzzy Test > + > + @param[in] Context [Optional] An optional parameter that enables: > + 1) test-case reuse with varied parameters and > + 2) test-case re-entry for Target tests that need a > + reboot. This parameter is a VOID* and it is the > + responsibility of the test author to ensure that the > + contents are well understood by all test cases that may > + consume it. > + > + @retval UNIT_TEST_PASSED The Unit test has completed and the > test > + case was successful. > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > +**/ > +UNIT_TEST_STATUS > +EFIAPI > +TestCaseforFuzzyTest ( > + IN UNIT_TEST_CONTEXT Context > + ) > +{ > + UNIT_TEST_STATUS Status; > + UINTN Index; > + > + UT_ASSERT_EQUAL (RandomSeed (NULL, 0), TRUE); > + UT_ASSERT_EQUAL (Random32 (100, 100), 100); > + UT_ASSERT_EQUAL (Random64 (100, 100), 100); > + UT_ASSERT_TRUE ((Random32 (9, 10) >= 9) & (Random32 (9, 10) <= 10)); > + UT_ASSERT_TRUE ((Random64 (9, 10) >= 9) & (Random64 (9, 10) <= 10)); > + > + mSupportedBit.Bits.Present = 1; > + mSupportedBit.Bits.ReadWrite = 1; > + mSupportedBit.Bits.UserSupervisor = 1; > + mSupportedBit.Bits.WriteThrough = 1; > + mSupportedBit.Bits.CacheDisabled = 1; > + mSupportedBit.Bits.Accessed = 1; > + mSupportedBit.Bits.Dirty = 1; > + mSupportedBit.Bits.Pat = 1; > + mSupportedBit.Bits.Global = 1; > + mSupportedBit.Bits.Reserved1 = 0; > + mSupportedBit.Bits.PageTableBaseAddress = 0; > + mSupportedBit.Bits.Reserved2 = 0; > + mSupportedBit.Bits.ProtectionKey = 0xF; > + mSupportedBit.Bits.Nx = 1; > + > + mFuzzOption = ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > *)Context)->FuzzOption; > + mNumberIndex = 0; > + > + for (Index = 0; Index < ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > *)Context)->TestCount; Index++) { > + Status = MultipleMapEntryTest ( > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > >TestRangeCount, > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > >PagingMode > + ); > + if (Status != UNIT_TEST_PASSED) { > + return Status; > + } > + > + DEBUG ((DEBUG_INFO, ".")); > + } > + > + DEBUG ((DEBUG_INFO, "\n")); > + > + return UNIT_TEST_PASSED; > +} > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > new file mode 100644 > index 0000000000..e7c35b1c29 > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > @@ -0,0 +1,57 @@ > +/** @file > + Internal header for fuzzy test. > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#ifndef FUZZY_TEST_H_ > +#define FUZZY_TEST_H_ > + > +#include "CpuPageTableLibUnitTest.h" > + > +typedef struct _ALLOCATE_PAGE_RECORDS ALLOCATE_PAGE_RECORDS; > + > +typedef > +VOID * > +(EFIAPI *ALLOCATE_PAGES)( > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > + IN UINTN Pages > + ); > + > +typedef struct { > + VOID *Buffer; > + UINTN Pages; > +} ALLOCATE_PAGE_RECORD; > + > +struct _ALLOCATE_PAGE_RECORDS { > + UINTN Count; > + UINTN MaxCount; > + ALLOCATE_PAGES AllocatePagesForPageTable; > + ALLOCATE_PAGE_RECORD Records[0]; > +}; > + > +typedef struct { > + UINT64 LinearAddress; > + UINT64 Length; > + IA32_MAP_ATTRIBUTE Attribute; > + IA32_MAP_ATTRIBUTE Mask; > +} MAP_ENTRY; > + > +typedef struct { > + UINTN Count; > + UINTN InitCount; > + UINTN MaxCount; > + MAP_ENTRY Maps[10]; > +} MAP_ENTRYS; > + > +UINT64 > +GetEntryFromPageTable ( > + IN UINTN PageTable, > + IN PAGING_MODE PagingMode, > + IN UINT64 Address, > + OUT UINTN *Level > + ); > + > +#endif > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > new file mode 100644 > index 0000000000..4ccbc47d9e > --- /dev/null > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > @@ -0,0 +1,5009 @@ > +/** @file > + Pre-generated random number used by CpuPageTableLib test. > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + **/ > +UINTN mNumberCount = 50000; > +UINT8 mNumbers[] = { > + 250, 22, 243, 87, 160, 129, 26, 103, 242, 136, > + 193, 195, 125, 183, 205, 246, 65, 169, 187, 121, > + 129, 195, 32, 183, 49, 100, 34, 51, 143, 84, > + 215, 111, 113, 121, 59, 119, 33, 56, 224, 245, > + 254, 244, 114, 20, 63, 216, 118, 253, 145, 171, > + 108, 208, 155, 4, 47, 174, 154, 5, 92, 107, > + 127, 176, 76, 238, 147, 4, 21, 26, 116, 251, > + 54, 33, 126, 239, 125, 21, 188, 17, 65, 2, > + 176, 77, 54, 82, 60, 32, 133, 105, 5, 211, > + 41, 67, 24, 246, 122, 160, 96, 3, 27, 53, > + 116, 129, 220, 46, 16, 251, 49, 70, 149, 153, > + 14, 102, 69, 131, 125, 166, 221, 13, 36, 189, > + 103, 28, 229, 50, 217, 174, 163, 98, 1, 101, > + 226, 237, 164, 232, 153, 165, 48, 155, 152, 26, > + 112, 129, 155, 23, 84, 154, 53, 147, 240, 195, > + 248, 207, 129, 49, 35, 151, 90, 77, 170, 216, > + 27, 51, 143, 214, 195, 161, 61, 219, 68, 106, > + 159, 225, 204, 197, 59, 176, 37, 203, 61, 23, > + 12, 76, 116, 118, 169, 250, 161, 68, 2, 247, > + 184, 242, 199, 226, 86, 150, 216, 112, 116, 194, > + 57, 173, 11, 146, 23, 244, 168, 185, 85, 234, > + 57, 209, 48, 95, 130, 137, 107, 148, 113, 152, > + 28, 152, 53, 2, 180, 115, 18, 32, 93, 178, > + 158, 230, 216, 3, 230, 150, 244, 153, 200, 24, > + 54, 195, 181, 205, 234, 159, 76, 162, 92, 91, > + 255, 87, 145, 10, 250, 76, 150, 79, 13, 48, > + 119, 161, 245, 145, 56, 216, 107, 237, 189, 197, > + 192, 90, 52, 251, 176, 247, 163, 5, 82, 56, > + 234, 155, 160, 208, 252, 10, 1, 148, 153, 21, > + 221, 42, 205, 226, 6, 13, 243, 146, 123, 14, > + 234, 102, 179, 156, 13, 30, 31, 182, 179, 252, > + 32, 174, 65, 247, 53, 152, 106, 134, 120, 116, > + 188, 59, 59, 217, 26, 39, 113, 246, 170, 127, > + 91, 18, 15, 117, 9, 175, 165, 92, 111, 208, > + 250, 48, 33, 57, 14, 129, 154, 4, 95, 216, > + 76, 51, 80, 234, 173, 189, 203, 146, 54, 6, > + 225, 175, 138, 148, 49, 123, 112, 211, 195, 119, > + 248, 241, 24, 60, 0, 70, 109, 54, 49, 157, > + 240, 15, 171, 235, 76, 60, 236, 105, 92, 183, > + 238, 160, 203, 157, 205, 246, 149, 13, 246, 67, > + 205, 249, 245, 154, 81, 30, 149, 145, 227, 208, > + 65, 190, 72, 232, 102, 176, 69, 231, 156, 85, > + 216, 241, 192, 157, 88, 169, 247, 23, 200, 41, > + 247, 62, 173, 240, 35, 52, 98, 224, 159, 53, > + 15, 141, 59, 213, 100, 28, 76, 48, 26, 73, > + 48, 209, 164, 18, 176, 99, 15, 248, 154, 240, > + 134, 70, 217, 179, 133, 76, 222, 185, 247, 40, > + 139, 101, 85, 137, 197, 186, 89, 66, 35, 127, > + 31, 201, 231, 81, 39, 206, 99, 231, 106, 26, > + 69, 72, 208, 207, 49, 227, 141, 233, 41, 247, > + 176, 102, 47, 51, 237, 80, 88, 149, 229, 18, > + 89, 77, 126, 156, 32, 72, 132, 216, 247, 142, > + 103, 179, 220, 178, 162, 133, 215, 249, 52, 160, > + 25, 223, 226, 103, 4, 253, 103, 93, 191, 46, > + 250, 20, 186, 223, 145, 73, 114, 195, 159, 76, > + 44, 215, 46, 142, 190, 141, 201, 241, 134, 40, > + 135, 140, 28, 105, 147, 102, 55, 210, 102, 44, > + 180, 229, 217, 207, 46, 145, 161, 94, 8, 44, > + 110, 4, 38, 254, 174, 75, 36, 64, 113, 51, > + 98, 73, 97, 94, 147, 101, 168, 22, 67, 232, > + 3, 20, 35, 104, 166, 105, 168, 45, 133, 122, > + 101, 170, 238, 103, 31, 245, 66, 16, 81, 166, > + 68, 155, 34, 71, 172, 186, 156, 37, 105, 171, > + 90, 137, 248, 76, 123, 220, 208, 138, 209, 48, > + 127, 195, 191, 150, 19, 19, 148, 229, 91, 73, > + 204, 28, 112, 141, 239, 86, 130, 65, 238, 77, > + 0, 133, 137, 105, 62, 107, 0, 132, 109, 180, > + 182, 194, 215, 232, 207, 171, 189, 50, 169, 186, > + 177, 76, 56, 56, 155, 204, 176, 145, 80, 67, > + 178, 229, 32, 144, 10, 182, 98, 7, 129, 74, > + 216, 213, 96, 172, 206, 205, 27, 4, 215, 121, > + 55, 60, 73, 234, 223, 181, 60, 150, 32, 212, > + 254, 35, 202, 173, 9, 234, 0, 103, 229, 21, > + 23, 137, 101, 75, 102, 40, 225, 180, 203, 121, > + 109, 172, 227, 249, 172, 75, 126, 33, 1, 20, > + 130, 66, 205, 131, 154, 16, 72, 184, 76, 10, > + 98, 226, 65, 208, 177, 154, 111, 80, 130, 27, > + 46, 224, 46, 113, 61, 227, 125, 136, 118, 129, > + 121, 144, 140, 83, 197, 235, 226, 140, 141, 154, > + 240, 173, 133, 114, 138, 101, 114, 242, 73, 70, > + 104, 236, 72, 141, 58, 129, 108, 211, 11, 189, > + 212, 95, 37, 117, 40, 236, 67, 168, 251, 228, > + 111, 152, 209, 130, 3, 209, 8, 21, 217, 223, > + 202, 134, 159, 13, 126, 137, 150, 185, 93, 207, > + 218, 38, 77, 183, 197, 250, 134, 36, 184, 228, > + 213, 109, 220, 69, 219, 229, 39, 153, 78, 125, > + 223, 57, 239, 131, 116, 73, 4, 147, 105, 239, > + 132, 57, 160, 255, 66, 233, 145, 183, 225, 82, > + 170, 151, 244, 113, 130, 180, 63, 66, 236, 237, > + 7, 82, 29, 141, 83, 61, 93, 219, 79, 89, > + 192, 102, 77, 47, 191, 96, 250, 191, 186, 235, > + 24, 40, 244, 70, 91, 193, 102, 171, 110, 55, > + 158, 127, 226, 211, 86, 16, 56, 42, 20, 81, > + 143, 82, 47, 189, 112, 85, 246, 111, 177, 229, > + 28, 179, 101, 35, 114, 38, 148, 26, 134, 246, > + 123, 102, 141, 0, 11, 207, 173, 232, 92, 129, > + 182, 97, 175, 143, 89, 42, 112, 238, 3, 137, > + 96, 51, 150, 148, 20, 71, 4, 209, 94, 181, > + 232, 175, 110, 244, 148, 44, 172, 99, 129, 161, > + 253, 136, 100, 180, 141, 103, 81, 153, 96, 213, > + 250, 140, 9, 89, 93, 123, 166, 177, 85, 235, > + 56, 72, 63, 15, 164, 161, 5, 68, 214, 188, > + 93, 15, 41, 64, 233, 117, 0, 9, 255, 96, > + 190, 47, 27, 209, 79, 28, 117, 202, 185, 211, > + 58, 184, 150, 75, 67, 22, 36, 243, 148, 21, > + 218, 208, 214, 68, 173, 218, 164, 50, 139, 85, > + 108, 106, 134, 4, 22, 210, 181, 209, 187, 239, > + 137, 19, 250, 75, 93, 117, 214, 21, 138, 62, > + 249, 172, 72, 36, 209, 119, 198, 35, 156, 231, > + 7, 3, 153, 29, 46, 197, 147, 47, 105, 234, > + 129, 160, 130, 96, 231, 27, 178, 11, 180, 172, > + 155, 168, 14, 66, 73, 211, 143, 171, 42, 61, > + 36, 34, 207, 31, 56, 158, 138, 30, 125, 238, > + 145, 56, 93, 233, 231, 195, 115, 208, 54, 131, > + 171, 11, 13, 151, 41, 39, 165, 132, 44, 147, > + 79, 140, 107, 103, 189, 108, 51, 24, 178, 214, > + 21, 139, 25, 240, 231, 36, 17, 132, 246, 211, > + 87, 62, 149, 98, 27, 209, 189, 72, 11, 181, > + 151, 161, 3, 254, 90, 120, 62, 40, 36, 49, > + 71, 206, 33, 234, 57, 76, 112, 23, 79, 22, > + 181, 9, 105, 251, 193, 84, 103, 75, 114, 30, > + 49, 0, 36, 168, 169, 205, 11, 154, 187, 2, > + 115, 168, 242, 251, 244, 124, 77, 39, 174, 42, > + 182, 162, 124, 76, 201, 92, 47, 110, 5, 122, > + 35, 139, 212, 181, 239, 120, 99, 105, 29, 143, > + 109, 13, 242, 219, 38, 82, 197, 44, 28, 160, > + 7, 181, 82, 144, 156, 83, 28, 68, 240, 147, > + 119, 247, 130, 55, 158, 175, 41, 23, 126, 98, > + 89, 192, 233, 22, 24, 13, 170, 83, 122, 125, > + 28, 72, 120, 237, 115, 29, 171, 236, 52, 187, > + 191, 160, 36, 10, 104, 77, 170, 46, 138, 53, > + 42, 89, 131, 119, 94, 198, 237, 180, 158, 81, > + 202, 1, 238, 141, 245, 65, 108, 177, 235, 9, > + 156, 167, 59, 55, 105, 49, 191, 116, 110, 255, > + 121, 123, 87, 28, 80, 47, 10, 24, 228, 107, > + 99, 107, 167, 144, 174, 2, 89, 53, 62, 151, > + 143, 221, 30, 226, 135, 203, 50, 39, 96, 119, > + 46, 121, 13, 178, 103, 245, 218, 141, 158, 112, > + 155, 1, 7, 130, 35, 6, 57, 67, 59, 27, > + 81, 136, 147, 51, 17, 147, 119, 236, 173, 150, > + 150, 241, 201, 35, 31, 144, 12, 121, 118, 165, > + 102, 70, 234, 179, 183, 60, 19, 159, 217, 6, > + 207, 87, 88, 189, 215, 198, 244, 7, 16, 143, > + 24, 132, 116, 74, 205, 147, 33, 232, 141, 96, > + 140, 249, 67, 82, 57, 38, 34, 238, 161, 2, > + 201, 207, 5, 110, 75, 231, 239, 22, 255, 56, > + 240, 136, 105, 207, 223, 48, 232, 80, 185, 123, > + 141, 234, 193, 197, 6, 90, 131, 174, 106, 69, > + 229, 72, 160, 206, 180, 33, 252, 101, 106, 215, > + 156, 77, 114, 112, 216, 83, 222, 171, 159, 89, > + 118, 222, 93, 201, 24, 253, 217, 106, 2, 0, > + 39, 155, 55, 17, 239, 248, 253, 49, 103, 138, > + 134, 229, 134, 186, 41, 83, 29, 234, 126, 216, > + 157, 210, 47, 165, 225, 24, 217, 124, 130, 5, > + 58, 154, 111, 116, 92, 38, 159, 228, 172, 92, > + 44, 103, 7, 140, 88, 54, 12, 17, 112, 179, > + 69, 216, 27, 29, 50, 239, 219, 127, 136, 152, > + 84, 245, 136, 253, 80, 7, 64, 21, 177, 0, > + 163, 145, 228, 238, 202, 102, 127, 239, 186, 14, > + 15, 136, 193, 114, 112, 137, 146, 108, 47, 103, > + 238, 71, 223, 170, 56, 97, 31, 246, 74, 219, > + 7, 17, 111, 9, 96, 140, 99, 7, 33, 13, > + 117, 222, 117, 86, 165, 179, 49, 135, 235, 75, > + 132, 61, 18, 248, 235, 81, 182, 255, 9, 149, > + 218, 63, 96, 10, 123, 79, 78, 64, 221, 25, > + 67, 33, 113, 24, 90, 123, 223, 86, 228, 242, > + 134, 21, 240, 230, 10, 184, 65, 103, 157, 183, > + 130, 5, 253, 139, 60, 105, 38, 39, 217, 29, > + 203, 117, 213, 90, 150, 45, 153, 143, 121, 202, > + 251, 57, 58, 88, 212, 152, 195, 43, 7, 92, > + 227, 14, 74, 242, 54, 172, 135, 150, 101, 247, > + 81, 82, 240, 10, 46, 17, 196, 179, 18, 195, > + 12, 179, 98, 1, 126, 158, 6, 95, 41, 122, > + 118, 143, 0, 75, 197, 239, 112, 133, 213, 46, > + 148, 60, 4, 49, 224, 138, 248, 77, 212, 6, > + 250, 85, 209, 147, 161, 162, 209, 235, 99, 60, > + 19, 115, 5, 219, 171, 195, 184, 236, 60, 241, > + 141, 6, 132, 100, 225, 35, 64, 131, 97, 130, > + 19, 226, 201, 64, 225, 146, 233, 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b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > @@ -0,0 +1,309 @@ > +/** @file > + helper file for Unit tests of the CpuPageTableLib instance of the > CpuPageTableLib class > + > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include "CpuPageTableLibUnitTest.h" > +#include "../CpuPageTable.h" > + > +// > +// Global Data to validate if the page table is legal > +// mValidMaskNoLeaf[0] is not used > +// mValidMaskNoLeaf[1] ... mValidMaskNoLeaf [5] represent PTE ... PML5E > +// mValidMaskNoLeaf[Index] means if it is a valid no leaf entry, entry > should equal to (entry & mValidMaskNoLeaf[Index]) > +// mValidMaskLeaf[Index] means if it is a valid leaf entry, entry should > equal to (entry & mValidMaskLeaf[Index]) > +// mValidMaskLeafFlag[Index] means if it is a leaf entry, if and only if ((entry > & mValidMaskLeafFlag[Index]) == mValidMaskLeafFlag[Index]) > +// > +IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > +IA32_PAGING_ENTRY mValidMaskLeaf[6]; > +IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > + > +/** > + Init global data. > + > + @param[in] MemorySpace Memory space > +**/ > +VOID > +InitGlobalData ( > + UINTN MemorySpace > + ) > +{ > + UINTN Index; > + > + ASSERT (MemorySpace <= 52); > + mValidMaskNoLeaf[0].Uint64 = 0; > + mValidMaskLeaf[0].Uint64 = 0; > + mValidMaskLeafFlag[0].Uint64 = 0; > + > + // > + // Set common part for all kinds of entrys. > + // > + for (Index = 1; Index < 6; Index++) { > + mValidMaskNoLeaf[Index].Uint64 = MAX_UINT64; > + mValidMaskLeaf[Index].Uint64 = MAX_UINT64; > + > + // > + // bit 51:M is reserved, and should be zero > + // > + if (MemorySpace - 1 < 51) { > + mValidMaskNoLeaf[Index].Uint64 = BitFieldWrite64 > (mValidMaskNoLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > + mValidMaskLeaf[Index].Uint64 = BitFieldWrite64 > (mValidMaskLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > + } > + } > + > + // > + // Handle mask for no leaf entry. > + // > + mValidMaskNoLeaf[1].Uint64 = 0; // PTE can't map to page > structure. > + mValidMaskNoLeaf[2].Pnle.Bits.MustBeZero = 0; // for PML4E, bit 7 must > be zero. > + mValidMaskNoLeaf[3].Pnle.Bits.MustBeZero = 0; // for PML5E, bit 7 must > be zero. > + mValidMaskNoLeaf[4].Pml4.Bits.MustBeZero = 0; // for PML4E, bit 7 must > be zero. > + mValidMaskNoLeaf[5].Pml4.Bits.MustBeZero = 0; // for PML5E, bit 7 must > be zero. > + > + // > + // Handle mask for leaf entry. > + // No need to modification for PTE, since it doesn't have extra reserved bit > + // > + mValidMaskLeaf[2].Uint64 = BitFieldWrite64 (mValidMaskLeaf[2].Uint64, > 13, 20, 0); // bit 13-20 is reserved for PDE > + mValidMaskLeaf[3].Uint64 = BitFieldWrite64 (mValidMaskLeaf[2].Uint64, > 13, 29, 0); // bit 13-29 is reserved for PDPTE > + mValidMaskLeaf[4].Uint64 = 0; // for PML4E, no > possible to map to page. > + mValidMaskLeaf[5].Uint64 = 0; // for PML5E, no > possible to map to page. > + > + // > + // Handle Flags to indicate it is a leaf entry. > + // for PML4E and PML5E, no possible to map to page, so the flag should be > MAX_UINT64. > + // > + mValidMaskLeafFlag[1].Pce.Present = 1; // For PTE, as long as it is present, > it maps to page > + // > + // For PDE and PDPTE, the bit 7 should be set to map to pages > + // > + mValidMaskLeafFlag[2].Pde2M.Bits.MustBeOne = 1; > + mValidMaskLeafFlag[2].Pde2M.Bits.Present = 1; > + mValidMaskLeafFlag[3].Pde2M.Bits.MustBeOne = 1; > + mValidMaskLeafFlag[3].Pde2M.Bits.Present = 1; > + mValidMaskLeafFlag[4].Uint64 = MAX_UINT64; > + mValidMaskLeafFlag[5].Uint64 = MAX_UINT64; > +} > + > +/** > + Check if the Page table entry is valid > + > + @param[in] PagingEntry The entry in page table to verify > + @param[in] Level the level of PagingEntry. > + @param[in] MaxLeafLevel Max leaf entry level. > + @param[in] LinearAddress The linear address verified. > + > + @retval Leaf entry. > +**/ > +UNIT_TEST_STATUS > +IsPageTableEntryValid ( > + IN IA32_PAGING_ENTRY *PagingEntry, > + IN UINTN Level, > + IN UINTN MaxLeafLevel, > + IN UINT64 Address > + ) > +{ > + UINT64 Index; > + IA32_PAGING_ENTRY *ChildPageEntry; > + UNIT_TEST_STATUS Status; > + > + if (PagingEntry->Pce.Present == 0) { > + return UNIT_TEST_PASSED; > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > mValidMaskLeafFlag[Level].Uint64) { > + // > + // It is a Leaf > + // > + if (Level > MaxLeafLevel) { > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d entry 0x%lx is a leaf entry, > but max leaf level is %d \n", Level, PagingEntry->Uint64, MaxLeafLevel)); > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry- > >Uint64) { > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d Leaf entry is 0x%lx, which > reserved bit is set \n", Level, PagingEntry->Uint64)); > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > + } > + > + return UNIT_TEST_PASSED; > + } > + > + // > + // Not a leaf > + // > + UT_ASSERT_NOT_EQUAL (Level, 1); > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > PagingEntry->Uint64) { > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, which > reserved bit is set \n", Level, PagingEntry->Uint64)); > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > + } > + > + ChildPageEntry = (IA32_PAGING_ENTRY > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); > + for (Index = 0; Index < 512; Index++) { > + Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, > MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); > + if (Status != UNIT_TEST_PASSED) { > + return Status; > + } > + } > + > + return UNIT_TEST_PASSED; > +} > + > +/** > + Check if the Page table is valid > + > + @param[in] PageTable The pointer to the page table. > + @param[in] PagingMode The paging mode. > + > + @retval UNIT_TEST_PASSED It is a valid Page Table > +**/ > +UNIT_TEST_STATUS > +IsPageTableValid ( > + IN UINTN PageTable, > + IN PAGING_MODE PagingMode > + ) > +{ > + UINTN MaxLevel; > + UINTN MaxLeafLevel; > + UINT64 Index; > + UNIT_TEST_STATUS Status; > + IA32_PAGING_ENTRY *PagingEntry; > + > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > (PagingMode >= PagingModeMax)) { > + // > + // 32bit paging is never supported. > + // PAE paging will be supported later. > + // > + return UNIT_TEST_ERROR_TEST_FAILED; > + } > + > + MaxLeafLevel = (UINT8)PagingMode; > + MaxLevel = (UINT8)(PagingMode >> 8); > + > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > + for (Index = 0; Index < 512; Index++) { > + Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, > MaxLeafLevel, Index << (9 * MaxLevel + 3)); > + if (Status != UNIT_TEST_PASSED) { > + return Status; > + } > + } > + > + return Status; > +} > + > +/** > + Get the leaf entry for a given linear address from one entry in page table > + > + @param[in] PagingEntry The entry in page table which covers the > linear address > + @param[in, out] Level On input, is the level of PagingEntry. > + On outout, is the level of the leaf entry > + @param[in] MaxLeafLevel Max leaf entry level. > + @param[in] LinearAddress The linear address. > + > + @retval Leaf entry. > +**/ > +UINT64 > +GetEntryFromSubPageTable ( > + IN IA32_PAGING_ENTRY *PagingEntry, > + IN OUT UINTN *Level, > + IN UINTN MaxLeafLevel, > + IN UINT64 Address > + ) > +{ > + UINT64 Index; > + IA32_PAGING_ENTRY *ChildPageEntry; > + > + if (PagingEntry->Pce.Present == 0) { > + return 0; > + } > + > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[*Level].Uint64) == > mValidMaskLeafFlag[*Level].Uint64) { > + // > + // It is a Leaf > + // > + return PagingEntry->Uint64; > + } > + > + // > + // Not a leaf > + // > + ChildPageEntry = (IA32_PAGING_ENTRY > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); > + *Level = *Level -1; > + Index = Address >> (*Level * 9 + 3); > + ASSERT (Index == (Index & ((1<< 9) - 1))); > + > + return GetEntryFromSubPageTable (&ChildPageEntry[Index], Level, > MaxLeafLevel, Address - (Index << (9 * *Level + 3))); > +} > + > +/** > + Get the leaf entry for a given linear address from a page table > + > + @param[in] PageTable The pointer to the page table. > + @param[in] PagingMode The paging mode. > + @param[in] LinearAddress The linear address. > + @param[out] Level leaf entry's level. > + > + @retval Leaf entry. > +**/ > +UINT64 > +GetEntryFromPageTable ( > + IN UINTN PageTable, > + IN PAGING_MODE PagingMode, > + IN UINT64 Address, > + OUT UINTN *Level > + ) > +{ > + UINTN MaxLevel; > + UINTN MaxLeafLevel; > + UINT64 Index; > + IA32_PAGING_ENTRY *PagingEntry; > + > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > (PagingMode >= PagingModeMax)) { > + // > + // 32bit paging is never supported. > + // PAE paging will be supported later. > + // > + return 0; > + } > + > + MaxLeafLevel = (UINT8)PagingMode; > + MaxLevel = (UINT8)(PagingMode >> 8); > + > + Index = Address >> (MaxLevel * 9 + 3); > + ASSERT (Index == (Index & ((1<< 9) - 1))); > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > + *Level = MaxLevel; > + > + return GetEntryFromSubPageTable (&PagingEntry[Index], Level, > MaxLeafLevel, Address - (Index << (9 * MaxLevel + 3))); > +} > + > +/** > + Get max physical adrress supported by specific page mode > + > + @param[in] Mode The paging mode. > + > + @retval max address. > +**/ > +UINT64 > +GetMaxAddress ( > + IN PAGING_MODE Mode > + ) > +{ > + switch (Mode) { > + case Paging32bit: > + case PagingPae: > + return SIZE_4GB; > + > + case Paging4Level: > + case Paging4Level1GB: > + case Paging5Level: > + case Paging5Level1GB: > + return 1ull << MIN (12 + (Mode >> 8) * 9, 52); > + > + default: > + ASSERT (0); > + return 0; > + } > +} > diff --git a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > index 8a5c456830..e72e4cd622 100644 > --- a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > +++ b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > @@ -20,6 +20,10 @@ > > [LibraryClasses] > MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf > + > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf > + > BaseCryptLib|CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf > + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf > > [PcdsPatchableInModule] > gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 > @@ -29,3 +33,8 @@ > # Build HOST_APPLICATION that tests the MtrrLib > # > UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTestHost.inf > + > + # > + # Build HOST_APPLICATION that tests the CpuPageTableLib > + # > + > UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo > st.inf > diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml > b/UefiCpuPkg/UefiCpuPkg.ci.yaml > index 6e0ab95fd8..bbdc44a45b 100644 > --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml > +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml > @@ -15,6 +15,7 @@ > ## "<ErrorID>", "<KeyWord>" > ## ] > "ExceptionList": [ > + "8006", "main" > ], > ## Both file path and directory path are accepted. > "IgnoreFiles": [ > @@ -38,7 +39,8 @@ > ], > # For host based unit tests > "AcceptableDependencies-HOST_APPLICATION":[ > - "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec" > + "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec", > + "CryptoPkg/CryptoPkg.dec" > ], > # For UEFI shell based apps > "AcceptableDependencies-UEFI_APPLICATION":[], > -- > 2.31.1.windows.1 > > > > > ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test 2022-08-12 9:19 ` [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test Zhiguang Liu @ 2022-08-12 18:12 ` Michael D Kinney 2022-08-15 3:23 ` Zhiguang Liu 0 siblings, 1 reply; 3+ messages in thread From: Michael D Kinney @ 2022-08-12 18:12 UTC (permalink / raw) To: devel@edk2.groups.io, Liu, Zhiguang, Kinney, Michael D Cc: Dong, Eric, Ni, Ray, Kumar, Rahul R Hi Zhiguang, Thank you for adding unit tests for this component. I do want to make sure we are using consistent terminology related to different type of testing. I think what you have implemented here consists of randomly generated test vectors. I think fuzz testing usually involves the use of fuzzing tools that perform source code analysis to generate a focused set of test vectors that exercise different code paths and data patterns. If your style is randomly generated test vectors without the use of fuzzing tools, then I recommend we do not use the terms "Fuzz" or "FUZZ" in the unit test sources. Perhaps use terms like "Random" and "RANDOM". Thanks, Mike > -----Original Message----- > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Zhiguang Liu > Sent: Friday, August 12, 2022 2:20 AM > To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@intel.com> > Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R <rahul.r.kumar@intel.com> > Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test > > Hi all, > This patch contains a big C file, containing random number to make it possible to reproduce issue in fuzzy test. > If the mail is hard to review, please review from https://github.com/tianocore/edk2/pull/3201 > > Thanks > Zhiguang > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > > Zhiguang Liu > > Sent: Friday, August 12, 2022 5:14 PM > > To: devel@edk2.groups.io > > Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric > > <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R > > <rahul.r.kumar@intel.com> > > Subject: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add > > host based unit test > > > > Add host based unit tests for the CpuPageTableLib services. > > > > Unit test focuses on PageTableMap function, containing two kinds of test > > cases: manual test case and fuzzy test case. > > Manual test case creates some corner case to test function PageTableMap. > > Fuzzy test case generates multiple random memory entries (with random > > attribute) as the input of function PageTableMap to get the output > > pagetable. Output pagetable will be validated and be parsed to get output > > memory entries, and then the input and output memory entries will be > > compared to verify the functionality. > > > > The unit test is not perfect yet. There are options for fuzzy test, and > > some of them control the test coverage, and some option are not ready. > > Will enhance in the future. > > > > Cc: Eric Dong <eric.dong@intel.com> > > Cc: Ray Ni <ray.ni@intel.com> > > Cc: Rahul Kumar <rahul1.kumar@intel.com> > > Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> > > --- > > > > diff --git > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > h > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > h > > new file mode 100644 > > index 0000000000..01d281f9c8 > > --- /dev/null > > +++ > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > h > > @@ -0,0 +1,117 @@ > > +/** @file > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef CPU_PAGE_TABLE_SUPPORT_H_ > > +#define CPU_PAGE_TABLE_SUPPORT_H_ > > + > > +#include <stdio.h> > > +#include <stdlib.h> > > +#include <string.h> > > +#include <stdarg.h> > > +#include <stddef.h> > > +#include <setjmp.h> > > +#include <cmocka.h> > > +#include <time.h> > > + > > +#include <Uefi.h> > > +#include <Library/BaseLib.h> > > +#include <Library/BaseMemoryLib.h> > > +#include <Library/DebugLib.h> > > +#include <Library/UnitTestLib.h> > > +#include <Library/CpuPageTableLib.h> > > +#include <Library/MemoryAllocationLib.h> > > +#include <Library/UnitTestHostBaseLib.h> > > +#include <Library/BaseCryptLib.h> > > +#include "../CpuPageTable.h" > > + > > +#define UNIT_TEST_APP_NAME "Cpu Page Table Lib Unit Tests" > > +#define UNIT_TEST_APP_VERSION "1.0" > > + > > +// > > +// Fuzz Options > > +// > > + > > +// > > +// Only test one-one mapping case > > +// > > +#define ONLY_ONE_ONE_MAPPING 0x00000001 > > + > > +// > > +// Change page table without using function PageTableMap, and use the > > modified page table as input > > +// > > +#define MANUAL_CHANGE_PAGE_TABLE 0x00000002 > > + > > +// > > +// Use pre-generated random number array to generate random number > > +// > > +#define USE_RANDOM_ARRAY 0x00000004 > > + > > +typedef struct { > > + PAGING_MODE PagingMode; > > + UINTN TestCount; > > + UINTN TestRangeCount; > > + UINTN FuzzOption; > > +} CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT; > > + > > +/** > > + Fuzzy Test > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseforFuzzyTest ( > > + IN UNIT_TEST_CONTEXT Context > > + ); > > + > > +/** > > + Init global data > > + > > + @param[in] MemorySpace Memory space > > +**/ > > +VOID > > +InitGlobalData ( > > + UINTN MemorySpace > > + ); > > + > > +/** > > + Check if the Page table is valid > > + > > + @param[in] PageTable The pointer to the page table. > > + @param[in] PagingMode The paging mode. > > + > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > +**/ > > +UNIT_TEST_STATUS > > +IsPageTableValid ( > > + IN UINTN PageTable, > > + IN PAGING_MODE PagingMode > > + ); > > + > > +/** > > + Get max physical adrress supported by specific page mode > > + > > + @param[in] Mode The paging mode. > > + > > + @retval max address. > > +**/ > > +UINT64 > > +GetMaxAddress ( > > + IN PAGING_MODE Mode > > + ); > > + > > +#endif > > diff --git > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.c > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.c > > new file mode 100644 > > index 0000000000..a0409bc318 > > --- /dev/null > > +++ > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.c > > @@ -0,0 +1,794 @@ > > +/** @file > > + Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include "CpuPageTableLibUnitTest.h" > > + > > +// ----------------------------------------------------------------------- PageMode-- > > TestCount-TestRangeCount---FuzzOptions > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > mTestContextPaging4Level = { Paging4Level, 100, 20, > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > mTestContextPaging4Level1GB = { Paging4Level1GB, 100, 20, > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > mTestContextPaging5Level = { Paging5Level, 100, 20, > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > mTestContextPaging5Level1GB = { Paging5Level1GB, 100, 20, > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > + > > +/** > > + Check if the input parameters are not supported. > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseForParameter ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + UINTN Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = 0; > > + PagingMode = Paging5Level1GB; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + > > + // > > + // If the input linear address is not 4K align, it should return invalid > > parameter > > + // > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > > RETURN_INVALID_PARAMETER); > > + > > + // > > + // If the input PageTableBufferSize is not 4K align, it should return invalid > > parameter > > + // > > + PageTableBufferSize = 10; > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > > &PageTableBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), > > RETURN_INVALID_PARAMETER); > > + > > + // > > + // If the input PagingMode is Paging32bit, it should return invalid > > parameter > > + // > > + PageTableBufferSize = 0; > > + PagingMode = Paging32bit; > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > > RETURN_UNSUPPORTED); > > + > > + // > > + // If the input MapMask is NULL, it should return invalid parameter > > + // > > + PagingMode = Paging5Level1GB; > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, &Buffer, > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), > > RETURN_INVALID_PARAMETER); > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check the case that modifying page table doesn't need extra buffe > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseWhichNoNeedExtraSize ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + UNIT_TEST_STATUS TestStatus; > > + > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = 0; > > + PagingMode = Paging4Level1GB; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Bits.Present = 1; > > + MapAttribute.Bits.Nx = 1; > > + MapMask.Bits.Present = 1; > > + MapMask.Uint64 = MAX_UINT64; > > + > > + // > > + // Create page table to cover [0, 10M], it should have 5 PTE > > + // > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + // > > + // call library to cover [0, 4K], because the page table is already cover [0, > > 10M], and no attribute change, > > + // We assume the fucntion doesn't need to change page table, return > > success and output BufferSize is 0 > > + // > > + Buffer = NULL; > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + // > > + // Same range and same attribute, only clear one mask attribute bit > > + // We assume the fucntion doesn't need to change page table, return > > success and output BufferSize is 0 > > + // > > + MapMask.Bits.Nx = 0; > > + PageTableBufferSize = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + // > > + // call library to cover [2M, 4M], while the page table is already cover [0, > > 10M], > > + // only change one attribute bit, we assume the page table change be > > modified even if the > > + // input Buffer is NULL, and BufferSize is 0 > > + // > > + MapAttribute.Bits.Accessed = 1; > > + MapMask.Bits.Accessed = 1; > > + PageTableBufferSize = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, > > &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Test Case that check the case to map [0, 1G] to [8K, 1G+8K] > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCase1Gmapto4K ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + UNIT_TEST_STATUS TestStatus; > > + > > + // > > + // Create Page table to map [0,1G] to [8K, 1G+8K] > > + // > > + PagingMode = Paging4Level1GB; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Uint64 = (UINT64)SIZE_4KB * 2; > > + MapMask.Uint64 = (UINT64)SIZE_4KB * 2; > > + MapAttribute.Bits.Present = 1; > > + MapMask.Bits.Present = 1; > > + MapMask.Uint64 = MAX_UINT64; > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + > > + // > > + // Page table should be valid. (All reserved bits are zero) > > + // > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check if the parent entry has different R/W attribute > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseManualChangeReadWrite ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + IA32_MAP_ENTRY *Map; > > + UINTN MapCount; > > + IA32_PAGING_ENTRY *PagingEntry; > > + VOID *BackupBuffer; > > + UINTN BackupPageTableBufferSize; > > + > > + PagingMode = Paging4Level; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = MAX_UINT64; > > + MapAttribute.Bits.Present = 1; > > + MapAttribute.Bits.ReadWrite = 1; > > + > > + // > > + // Create Page table to cover [0,2G], with ReadWrite = 1 > > + // > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + BackupPageTableBufferSize = PageTableBufferSize; > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES > > (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + IsPageTableValid (PageTable, PagingMode); > > + > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + IsPageTableValid (PageTable, PagingMode); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Manually change ReadWrite to 0 for non-leaf entry, which covers [0,2G] > > + // > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Copy the page entry structure memory for future compare > > + // > > + BackupBuffer = AllocateCopyPool (BackupPageTableBufferSize, Buffer); > > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > > BackupPageTableBufferSize); > > + > > + // > > + // Call library to change ReadWrite to 0 for [0,2M] > > + // > > + MapAttribute.Bits.ReadWrite = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + IsPageTableValid (PageTable, PagingMode); > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + // > > + // There should be 1 range [0, 2G] with ReadWrite = 0 > > + // > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // The latest PageTableMap call should change nothing. > > + // The memory should be identical before and after the funtion is called. > > + // > > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > > BackupPageTableBufferSize); > > + > > + // > > + // Call library to change ReadWrite to 1 for [0, 2M] > > + // > > + MapAttribute.Bits.ReadWrite = 1; > > + PageTableBufferSize = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + IsPageTableValid (PageTable, PagingMode); > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + // > > + // There should be 2 range [0, 2M] with ReadWrite = 1 and [2M, 2G] with > > ReadWrite = 0 > > + // > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 2); > > + > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2MB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2GB - SIZE_2MB); > > + ExpectedMapAttribute.Uint64 = SIZE_2MB; > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > + ExpectedMapAttribute.Bits.Present = 1; > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check if the needed size is expected > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseManualSizeNotMatch ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + IA32_MAP_ENTRY *Map; > > + UINTN MapCount; > > + IA32_PAGING_ENTRY *PagingEntry; > > + > > + PagingMode = Paging4Level; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = MAX_UINT64; > > + MapAttribute.Bits.Present = 1; > > + MapAttribute.Bits.ReadWrite = 1; > > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12; > > + // > > + // Create Page table to cover [2M-4K, 4M], with ReadWrite = 1 > > + // > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > > &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > > &MapAttribute, &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + IsPageTableValid (PageTable, PagingMode); > > + > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + IsPageTableValid (PageTable, PagingMode); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB + SIZE_2MB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Manually change ReadWrite to 0 for 3 level non-leaf entry, which covers > > [0,2M] > > + // Then the map is: > > + // [2M-4K,2M], R/W = 0 > > + // [2M ,4M], R/W = 1 > > + // > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > // Get 4 level entry > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > > >Pnle.Bits.PageTableBaseAddress << 12); // Get 3 level entry > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > > >Pnle.Bits.PageTableBaseAddress << 12); // Get 2 level entry > > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 2); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + ExpectedMapAttribute.Bits.ReadWrite = 1; > > + ExpectedMapAttribute.Bits.PageTableBaseAddress = SIZE_2MB >> 12; > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s > > ReadWrite is already 1 > > + // Just need to set [2M-4K,2M], won't need extra size, so the status should > > be success > > + // > > + MapAttribute.Bits.Present = 1; > > + MapAttribute.Bits.ReadWrite = 1; > > + PageTableBufferSize = 0; > > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> 12; > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check that won't merge entries > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseManualNotMergeEntry ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + UNIT_TEST_STATUS TestStatus; > > + > > + PagingMode = Paging4Level1GB; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = MAX_UINT64; > > + MapAttribute.Bits.Present = 1; > > + MapMask.Bits.Present = 1; > > + > > + // > > + // Create Page table to cover [0,4M], and [4M, 1G] is not present > > + // > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + // > > + // Let Page table to cover [0,1G], we assume it won't use a big 1G entry to > > cover whole range > > + // It looks like the chioce is not bad, but sometime, we need to keep some > > small entry > > + // > > + PageTableBufferSize = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + MapAttribute.Bits.Accessed = 1; > > + PageTableBufferSize = 0; > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, > > &MapMask); > > + // > > + // If it didn't use a big 1G entry to cover whole range, only change [0,2M] > > for some attribute won't need extra memory > > + // > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check if the parent entry has different Nx attribute > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseManualChangeNx ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UINTN PageTable; > > + PAGING_MODE PagingMode; > > + VOID *Buffer; > > + UINTN PageTableBufferSize; > > + IA32_MAP_ATTRIBUTE MapAttribute; > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > + IA32_MAP_ATTRIBUTE MapMask; > > + RETURN_STATUS Status; > > + IA32_MAP_ENTRY *Map; > > + UINTN MapCount; > > + IA32_PAGING_ENTRY *PagingEntry; > > + UNIT_TEST_STATUS TestStatus; > > + > > + PagingMode = Paging4Level1GB; > > + PageTableBufferSize = 0; > > + PageTable = 0; > > + Buffer = NULL; > > + MapAttribute.Uint64 = 0; > > + MapMask.Uint64 = MAX_UINT64; > > + MapAttribute.Bits.Present = 1; > > + MapAttribute.Bits.Nx = 0; > > + > > + // > > + // Create Page table to cover [0,2G], with Nx = 0 > > + // > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > (IA32_MAP_ENTRY))); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Manually change Nx to 1 for non-leaf entry, which covers [0,2G] > > + // > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > + PagingEntry->Uint64 = PagingEntry->Uint64 | BIT63; > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > (IA32_MAP_ENTRY))); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + UT_ASSERT_EQUAL (MapCount, 1); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > + ExpectedMapAttribute.Bits.Nx = 1; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + > > + // > > + // Call library to change Nx to 0 for [0,1G] > > + // > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > &MapMask); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + MapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > (IA32_MAP_ENTRY))); > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + > > + // > > + // There should be two ranges [0, 1G] with Nx = 0 and [1G, 2G] with Nx = 1 > > + // > > + UT_ASSERT_EQUAL (MapCount, 2); > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_1GB); > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_1GB); > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_1GB); > > + ExpectedMapAttribute.Uint64 = SIZE_1GB; > > + ExpectedMapAttribute.Bits.Present = 1; > > + ExpectedMapAttribute.Bits.Nx = 1; > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > ExpectedMapAttribute.Uint64); > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Initialize the unit test framework, suite, and unit tests for the > > + sample unit tests and run the unit tests. > > + > > + @retval EFI_SUCCESS All test cases were dispatched. > > + @retval EFI_OUT_OF_RESOURCES There are not enough resources > > available to > > + initialize the unit tests. > > +**/ > > +EFI_STATUS > > +EFIAPI > > +UefiTestMain ( > > + VOID > > + ) > > +{ > > + EFI_STATUS Status; > > + UNIT_TEST_FRAMEWORK_HANDLE Framework; > > + UNIT_TEST_SUITE_HANDLE ManualTestCase; > > + UNIT_TEST_SUITE_HANDLE FuzzyTestCase; > > + > > + Framework = NULL; > > + > > + DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, > > UNIT_TEST_APP_VERSION)); > > + > > + // > > + // Start setting up the test framework for running the tests. > > + // > > + Status = InitUnitTestFramework (&Framework, UNIT_TEST_APP_NAME, > > gEfiCallerBaseName, UNIT_TEST_APP_VERSION); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status > > = %r\n", Status)); > > + goto EXIT; > > + } > > + > > + // > > + // Populate the Manual Test Cases. > > + // > > + Status = CreateUnitTestSuite (&ManualTestCase, Framework, "Manual > > Test Cases", "CpuPageTableLib.Manual", NULL, NULL); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Manual Test > > Cases\n")); > > + Status = EFI_OUT_OF_RESOURCES; > > + goto EXIT; > > + } > > + > > + AddTestCase (ManualTestCase, "Check if the input parameters are not > > supported.", "Manual Test Case1", TestCaseForParameter, NULL, NULL, > > NULL); > > + AddTestCase (ManualTestCase, "Check the case that modifying page table > > doesn't need extra buffer", "Manual Test Case2", > > TestCaseWhichNoNeedExtraSize, NULL, NULL, NULL); > > + AddTestCase (ManualTestCase, "Check the case to map [0, 1G] to [8K, > > 1G+8K]", "Manual Test Case3", TestCase1Gmapto4K, NULL, NULL, NULL); > > + AddTestCase (ManualTestCase, "Check won't merge entries", "Manual > > Test Case4", TestCaseManualNotMergeEntry, NULL, NULL, NULL); > > + AddTestCase (ManualTestCase, "Check if the parent entry has different > > ReadWrite attribute", "Manual Test Case5", > > TestCaseManualChangeReadWrite, NULL, NULL, NULL); > > + AddTestCase (ManualTestCase, "Check if the parent entry has different Nx > > attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, > > NULL); > > + AddTestCase (ManualTestCase, "Check if the needed size is expected", > > "Manual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); > > + > > + // > > + // Populate the Fuzzy Test Cases. > > + // > > + Status = CreateUnitTestSuite (&FuzzyTestCase, Framework, "Fuzzy Test > > Cases", "CpuPageTableLib.Fuzzy", NULL, NULL); > > + if (EFI_ERROR (Status)) { > > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Fuzzy Test > > Cases\n")); > > + Status = EFI_OUT_OF_RESOURCES; > > + goto EXIT; > > + } > > + > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level", "Fuzzy Test > > Case1", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging4Level); > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level1G", "Fuzzy Test > > Case2", TestCaseforFuzzyTest, NULL, NULL, > > &mTestContextPaging4Level1GB); > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level", "Fuzzy Test > > Case3", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging5Level); > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level1G", "Fuzzy Test > > Case4", TestCaseforFuzzyTest, NULL, NULL, > > &mTestContextPaging5Level1GB); > > + > > + // > > + // Execute the tests. > > + // > > + Status = RunAllTestSuites (Framework); > > + > > +EXIT: > > + if (Framework) { > > + FreeUnitTestFramework (Framework); > > + } > > + > > + return Status; > > +} > > + > > +/** > > + Standard POSIX C entry point for host based unit test execution. > > + > > + @param Argc Number of arguments. > > + @param Argv Array of arguments. > > + > > + @return Test application exit code. > > +**/ > > +INT32 > > +main ( > > + INT32 Argc, > > + CHAR8 *Argv[] > > + ) > > +{ > > + InitGlobalData (52); > > + return UefiTestMain (); > > +} > > diff --git > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.inf > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.inf > > new file mode 100644 > > index 0000000000..2854df46d3 > > --- /dev/null > > +++ > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > Host.inf > > @@ -0,0 +1,42 @@ > > +## @file > > +# Unit tests of the CpuPageTableLib instance of the CpuPageTableLib class > > +# > > +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > +## > > + > > +[Defines] > > + INF_VERSION = 0x00010006 > > + BASE_NAME = CpuPageTableLibUnitTestHost > > + FILE_GUID = D8DC32C2-7272-43A8-B145-1723BED8E119 > > + MODULE_TYPE = HOST_APPLICATION > > + VERSION_STRING = 1.0 > > + > > +# > > +# The following information is for reference only and not required by the > > build tools. > > +# > > +# VALID_ARCHITECTURES = IA32 X64 > > +# > > + > > +[Sources] > > + CpuPageTableLibUnitTestHost.c > > + FuzzyTest.c > > + TestHelper.c > > + RandomNumber.c > > + FuzzyTest.h > > + CpuPageTableLibUnitTest.h > > + > > +[Packages] > > + MdePkg/MdePkg.dec > > + UefiCpuPkg/UefiCpuPkg.dec > > + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec > > + CryptoPkg/CryptoPkg.dec > > + > > +[LibraryClasses] > > + BaseLib > > + BaseMemoryLib > > + DebugLib > > + CpuPageTableLib > > + UnitTestLib > > + MemoryAllocationLib > > + BaseCryptLib > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > new file mode 100644 > > index 0000000000..05ab66d406 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > @@ -0,0 +1,926 @@ > > +/** @file > > + Fuzzy test case for Unit tests of the CpuPageTableLib instance of the > > CpuPageTableLib class > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include "CpuPageTableLibUnitTest.h" > > +#include "FuzzyTest.h" > > + > > +UINTN RandomNumber = 0; > > +extern IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > > +extern IA32_PAGING_ENTRY mValidMaskLeaf[6]; > > +extern IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > > +UINTN mFuzzOption; > > +IA32_MAP_ATTRIBUTE mSupportedBit; > > +extern UINTN mNumberCount; > > +extern UINT8 mNumbers[]; > > +UINTN mNumberIndex; > > +UINT64 AlignedTable[] = { > > + ~((UINT64)SIZE_4KB - 1), > > + ~((UINT64)SIZE_2MB - 1), > > + ~((UINT64)SIZE_1GB - 1) > > +}; > > + > > +/** > > + Generates a pseudorandom byte stream of the specified size. > > + > > + Return FALSE to indicate this interface is not supported. > > + > > + @param[out] Output Pointer to buffer to receive random value. > > + @param[in] Size Size of random bytes to generate. > > + > > + @retval TRUE Always return TRUE > > + > > +**/ > > +BOOLEAN > > +EFIAPI > > +RandomBytesUsingArray ( > > + OUT UINT8 *Output, > > + IN UINTN Size > > + ) > > +{ > > + UINTN Index; > > + > > + for (Index = 0; Index < Size; Index++) { > > + if (mNumberIndex >= mNumberCount) { > > + mNumberIndex = 0; > > + } > > + > > + Output[Index] = mNumbers[mNumberIndex]; > > + mNumberIndex++; > > + } > > + > > + return TRUE; > > +} > > + > > +/** > > + Generates a pseudorandom byte stream of the specified size. > > + > > + Return FALSE to indicate this interface is not supported. > > + > > + @param[out] Output Pointer to buffer to receive random value. > > + @param[in] Size Size of random bytes to generate. > > + > > + @retval TRUE Pseudorandom byte stream generated successfully. > > + @retval FALSE Pseudorandom number generator fails > > +**/ > > +BOOLEAN > > +EFIAPI > > +LocalRandomBytes ( > > + OUT UINT8 *Output, > > + IN UINTN Size > > + ) > > +{ > > + if (mFuzzOption & USE_RANDOM_ARRAY) { > > + return RandomBytesUsingArray (Output, Size); > > + } else { > > + return RandomBytes (Output, Size); > > + } > > +} > > + > > +/** > > + Return a random boolean. > > + > > + @return boolean > > +**/ > > +BOOLEAN > > +RandomBoolean ( > > + VOID > > + ) > > +{ > > + BOOLEAN Value; > > + > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); > > + return Value%2; > > +} > > + > > +/** > > + Return a 32bit random number. > > + > > + @param Start Start of the random number range. > > + @param Limit Limit of the random number range, and return value can be > > Limit. > > + @return 32bit random number > > +**/ > > +UINT32 > > +Random32 ( > > + UINT32 Start, > > + UINT32 Limit > > + ) > > +{ > > + UINT64 Value; > > + > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > > + return (UINT32)(Value % (Limit - Start + 1)) + Start; > > +} > > + > > +/** > > + Return a 64bit random number. > > + > > + @param Start Start of the random number range. > > + @param Limit Limit of the random number range, and return value can be > > Limit. > > + @return 64bit random number > > +**/ > > +UINT64 > > +Random64 ( > > + UINT64 Start, > > + UINT64 Limit > > + ) > > +{ > > + UINT64 Value; > > + > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > > + if (Limit - Start == MAX_UINT64) { > > + return (UINT64)(Value); > > + } > > + > > + return (UINT64)(Value % (Limit - Start + 1)) + Start; > > +} > > + > > +/** > > + Check if the Page table entry is valid > > + > > + @param[in] PagingEntry The entry in page table to verify > > + @param[in] Level the level of PagingEntry. > > + @param[in] MaxLeafLevel Max leaf entry level. > > + @param[in] LinearAddress The linear address verified. > > + > > + @retval Leaf entry. > > +**/ > > +UNIT_TEST_STATUS > > +ValidateAndRandomeModifyPageTablePageTableEntry ( > > + IN IA32_PAGING_ENTRY *PagingEntry, > > + IN UINTN Level, > > + IN UINTN MaxLeafLevel, > > + IN UINT64 Address > > + ) > > +{ > > + UINT64 Index; > > + UINT64 TempPhysicalBase; > > + IA32_PAGING_ENTRY *ChildPageEntry; > > + UNIT_TEST_STATUS Status; > > + > > + if (PagingEntry->Pce.Present == 0) { > > + return UNIT_TEST_PASSED; > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > > mValidMaskLeafFlag[Level].Uint64) { > > + // > > + // It is a Leaf > > + // > > + if (Level > MaxLeafLevel) { > > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry- > > >Uint64) { > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > + } > > + > > + if ((RandomNumber < 100) && RandomBoolean ()) { > > + RandomNumber++; > > + if (Level == 1) { > > + TempPhysicalBase = PagingEntry->Pte4K.Bits.PageTableBaseAddress; > > + } else { > > + TempPhysicalBase = PagingEntry->PleB.Bits.PageTableBaseAddress; > > + } > > + > > + PagingEntry->Uint64 = (Random64 (0, MAX_UINT64) & > > mValidMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; > > + PagingEntry->Pte4K.Bits.Present = 1; > > + if (Level == 1) { > > + PagingEntry->Pte4K.Bits.PageTableBaseAddress = TempPhysicalBase; > > + } else { > > + PagingEntry->PleB.Bits.PageTableBaseAddress = TempPhysicalBase; > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != > > PagingEntry->Uint64) { > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > + } > > + } > > + > > + return UNIT_TEST_PASSED; > > + } > > + > > + // > > + // Not a leaf > > + // > > + UT_ASSERT_NOT_EQUAL (Level, 1); > > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > > PagingEntry->Uint64) { > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, which > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > > + } > > + > > + if ((RandomNumber < 100) && RandomBoolean ()) { > > + RandomNumber++; > > + TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress; > > + > > + PagingEntry->Uint64 = Random64 (0, MAX_UINT64) & > > mValidMaskNoLeaf[Level].Uint64; > > + PagingEntry->Pnle.Bits.Present = 1; > > + PagingEntry->Pnle.Bits.PageTableBaseAddress = TempPhysicalBase; > > + ASSERT ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) != > > mValidMaskLeafFlag[Level].Uint64); > > + } > > + > > + ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry- > > >Pnle.Bits.PageTableBaseAddress) << 12); > > + for (Index = 0; Index < 512; Index++) { > > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > > (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + > > (Index<<(9*(Level-1) + 3))); > > + if (Status != UNIT_TEST_PASSED) { > > + return Status; > > + } > > + } > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check if the Page table is valid > > + > > + @param[in] PageTable The pointer to the page table. > > + @param[in] PagingMode The paging mode. > > + > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > +**/ > > +UNIT_TEST_STATUS > > +ValidateAndRandomeModifyPageTable ( > > + IN UINTN PageTable, > > + IN PAGING_MODE PagingMode > > + ) > > +{ > > + UINTN MaxLevel; > > + UINTN MaxLeafLevel; > > + UINT64 Index; > > + UNIT_TEST_STATUS Status; > > + IA32_PAGING_ENTRY *PagingEntry; > > + > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > (PagingMode >= PagingModeMax)) { > > + // > > + // 32bit paging is never supported. > > + // PAE paging will be supported later. > > + // > > + return UNIT_TEST_ERROR_TEST_FAILED; > > + } > > + > > + MaxLeafLevel = (UINT8)PagingMode; > > + MaxLevel = (UINT8)(PagingMode >> 8); > > + > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > + for (Index = 0; Index < 512; Index++) { > > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > > (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel + 3)); > > + if (Status != UNIT_TEST_PASSED) { > > + return Status; > > + } > > + } > > + > > + return Status; > > +} > > + > > +/** > > + Generate single random map entry. > > + The map entry can be the input of function PageTableMap > > + the LinearAddress and length is aligned to aligned table. > > + > > + @param MaxAddress Max Address. > > + @param MapEntrys Output MapEntrys contains all parameter as input of > > function PageTableMap > > +**/ > > +VOID > > +GenerateSingleRandomMapEntry ( > > + IN UINT64 MaxAddress, > > + IN OUT MAP_ENTRYS *MapEntrys > > + ) > > +{ > > + UINTN MapsIndex; > > + UINT64 FormerLinearAddress; > > + UINT64 FormerLinearAddressBottom; > > + UINT64 FormerLinearAddressTop; > > + > > + MapsIndex = MapEntrys->Count; > > + > > + ASSERT (MapsIndex < MapEntrys->MaxCount); > > + // > > + // use AlignedTable to avoid that a random number can be very hard to be > > 1G or 2M aligned > > + // > > + if ((MapsIndex != 0) && (RandomBoolean ())) { > > + FormerLinearAddress = MapEntrys->Maps[Random32 (0, > > (UINT32)MapsIndex-1)].LinearAddress; > > + if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { > > + FormerLinearAddressBottom = 0; > > + } else { > > + FormerLinearAddressBottom = FormerLinearAddress - 2 * > > (UINT64)SIZE_1GB; > > + } > > + > > + if (FormerLinearAddress + 2 * (UINT64)SIZE_1GB > MaxAddress) { > > + FormerLinearAddressTop = MaxAddress; > > + } else { > > + FormerLinearAddressTop = FormerLinearAddress + 2 * > > (UINT64)SIZE_1GB; > > + } > > + > > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 > > (FormerLinearAddressBottom, FormerLinearAddressTop) & > > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > > + } else { > > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 (0, > > MaxAddress) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > > + } > > + > > + // > > + // To have better performance, limit the size less than 10G > > + // > > + MapEntrys->Maps[MapsIndex].Length = Random64 (0, MIN (MaxAddress > > - MapEntrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) & > > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > > + > > + if ((MapsIndex != 0) && (RandomBoolean ())) { > > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = MapEntrys- > > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; > > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = MapEntrys- > > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; > > + } else { > > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = Random64 (0, > > MAX_UINT64) & mSupportedBit.Uint64; > > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = Random64 (0, > > MAX_UINT64) & mSupportedBit.Uint64; > > + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey != 0) { > > + MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey = 0xF; > > + } > > + } > > + > > + if (mFuzzOption & ONLY_ONE_ONE_MAPPING) { > > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = > > MapEntrys->Maps[MapsIndex].LinearAddress >> 12; > > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = > > 0xFFFFFFFFFF; > > + } else { > > + // > > + // Todo: If the mask bit for base address is zero, when dump the > > pagetable, every entry mapping to physical address zeor. > > + // This means the map count will be a large number, and impossible to > > finish in proper time. > > + // Need to avoid such case when remove the fuzzy option > > ONLY_ONE_ONE_MAPPING > > + // > > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress = > > (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, > > ARRAY_SIZE (AlignedTable) -1)])>> 12; > > + if (RandomBoolean ()) { > > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0; > > + } > > + } > > + > > + MapEntrys->Count += 1; > > +} > > + > > +/** > > + Compare the attribute for one point. > > + MapEntrys records every memory ranges that is used as input > > + Map and MapCount are gotten from Page table > > + Compare if this point have same attribute. > > + > > + @param[in] Address Address of one Point. > > + @param[in] MapEntrys Record every memory ranges that is used as > > input > > + @param[in] Map Pointer to an array that describes multiple linear > > address ranges. > > + @param[in] MapCount Pointer to a UINTN that hold the number of > > entries in the Map. > > + @param[in] InitMap Pointer to an array that describes init map entries. > > + @param[in] InitMapCount Pointer to a UINTN that hold the number of init > > map entries. > > + > > + @retval TRUE At least one byte of data is available to be read > > + @retval FALSE No data is available to be read > > +**/ > > +BOOLEAN > > +CompareEntrysforOnePoint ( > > + IN UINT64 Address, > > + IN MAP_ENTRYS *MapEntrys, > > + IN IA32_MAP_ENTRY *Map, > > + IN UINTN MapCount, > > + IN IA32_MAP_ENTRY *InitMap, > > + IN UINTN InitMapCount > > + ) > > +{ > > + UINTN Index; > > + IA32_MAP_ATTRIBUTE AttributeInInitMap; > > + IA32_MAP_ATTRIBUTE AttributeInMap; > > + IA32_MAP_ATTRIBUTE AttributeInMapEntrys; > > + IA32_MAP_ATTRIBUTE MaskInMapEntrys; > > + > > + AttributeInMap.Uint64 = 0; > > + AttributeInMapEntrys.Uint64 = 0; > > + AttributeInInitMap.Uint64 = 0; > > + MaskInMapEntrys.Uint64 = 0; > > + // > > + // Assume every entry in maps does not overlap with each other > > + // > > + for (Index = 0; Index < MapCount; Index++) { > > + if ((Address >= Map[Index].LinearAddress) && (Address < > > (Map[Index].LinearAddress + Map[Index].Length))) { > > + AttributeInMap.Uint64 = (Map[Index].Attribute.Uint64 & > > mSupportedBit.Uint64); > > + AttributeInMap.Bits.PageTableBaseAddress = ((Address - > > Map[Index].LinearAddress) >> 12) + > > Map[Index].Attribute.Bits.PageTableBaseAddress; > > + break; > > + } > > + } > > + > > + // > > + // Assume every entry in maps does not overlap with each other > > + // > > + for (Index = 0; Index < InitMapCount; Index++) { > > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > > + AttributeInInitMap.Uint64 = (InitMap[Index].Attribute.Uint64 > > & mSupportedBit.Uint64); > > + AttributeInInitMap.Bits.PageTableBaseAddress = ((Address - > > InitMap[Index].LinearAddress) >> 12) + > > InitMap[Index].Attribute.Bits.PageTableBaseAddress; > > + break; > > + } > > + } > > + > > + AttributeInMapEntrys.Uint64 = AttributeInInitMap.Uint64; > > + > > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; Index++) { > > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && (Address < > > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > >Maps[Index].Length))) { > > + if (AttributeInMapEntrys.Bits.Present == 0) { > > + AttributeInMapEntrys.Uint64 = 0; > > + MaskInMapEntrys.Uint64 = 0; > > + } > > + > > + MaskInMapEntrys.Uint64 |= MapEntrys->Maps[Index].Mask.Uint64; > > + AttributeInMapEntrys.Uint64 &= (~MapEntrys- > > >Maps[Index].Mask.Uint64); > > + AttributeInMapEntrys.Uint64 |= (MapEntrys- > > >Maps[Index].Attribute.Uint64 & MapEntrys->Maps[Index].Mask.Uint64); > > + if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress != 0) { > > + AttributeInMapEntrys.Bits.PageTableBaseAddress = ((Address - > > MapEntrys->Maps[Index].LinearAddress) >> 12) + MapEntrys- > > >Maps[Index].Attribute.Bits.PageTableBaseAddress; > > + } > > + } > > + } > > + > > + if (AttributeInMap.Bits.Present == 0) { > > + if (AttributeInMapEntrys.Bits.Present == 0) { > > + return TRUE; > > + } > > + } > > + > > + if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) != > > (AttributeInMapEntrys.Uint64 & MaskInMapEntrys.Uint64)) { > > + DEBUG ((DEBUG_INFO, "======detailed information begin=====\n")); > > + DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point > > with linear address: 0x%lx\n", Address)); > > + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute > > 0x%lx, and map to physical address 0x%lx\n", > > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMap) & > > MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBaseAddress)); > > + DEBUG ((DEBUG_INFO, "While according to inputs, the point should > > Attribute 0x%lx, and should map to physical address 0x%lx\n", > > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMapEntrys) & > > MaskInMapEntrys.Uint64, > > AttributeInMapEntrys.Bits.PageTableBaseAddress)); > > + DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", > > MaskInMapEntrys.Uint64)); > > + > > + if (MapEntrys->InitCount != 0) { > > + DEBUG ((DEBUG_INFO, "Below is the initialization status:\n")); > > + for (Index = 0; Index < InitMapCount; Index++) { > > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > > + DEBUG ((DEBUG_INFO, " *")); > > + } else { > > + DEBUG ((DEBUG_INFO, " ")); > > + } > > + > > + DEBUG ((DEBUG_INFO, " %02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > > InitMap[Index].LinearAddress, InitMap[Index].LinearAddress + > > InitMap[Index].Length, InitMap[Index].Attribute.Uint64)); > > + } > > + } > > + > > + DEBUG ((DEBUG_INFO, "Below is the inputs:\n")); > > + DEBUG ((DEBUG_INFO, " Index: {LinearAddress, LinearLimit, Mask, > > Attribute}\n")); > > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; Index++) > > { > > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && (Address < > > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > >Maps[Index].Length))) { > > + DEBUG ((DEBUG_INFO, " *")); > > + } else { > > + DEBUG ((DEBUG_INFO, " ")); > > + } > > + > > + DEBUG (( > > + DEBUG_INFO, > > + " %02d: {0x%lx, 0x%lx, 0x%lx,0x%lx}\n", > > + Index, > > + MapEntrys->Maps[Index].LinearAddress, > > + MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > >Maps[Index].Length, > > + MapEntrys->Maps[Index].Mask.Uint64, > > + MapEntrys->Maps[Index].Attribute.Uint64 > > + )); > > + } > > + > > + DEBUG ((DEBUG_INFO, "Below is the dumped from pagetable:\n")); > > + for (Index = 0; Index < MapCount; Index++) { > > + if ((Address >= Map[Index].LinearAddress) && (Address < > > (Map[Index].LinearAddress + Map[Index].Length))) { > > + DEBUG ((DEBUG_INFO, " *")); > > + } else { > > + DEBUG ((DEBUG_INFO, " ")); > > + } > > + > > + DEBUG ((DEBUG_INFO, "%02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > > Map[Index].LinearAddress, Map[Index].LinearAddress + Map[Index].Length, > > Map[Index].Attribute.Uint64)); > > + } > > + > > + DEBUG ((DEBUG_INFO, "======detailed information done=====\n")); > > + return FALSE; > > + } > > + > > + return TRUE; > > +} > > + > > +/** > > + Append key point of a given address to Buffer > > + if buffer is NULL, only count needed count > > + > > + @param[in, out] Buffer Buffer to contains all key point. > > + @param[in, out] Count Count of the key point. > > + @param[in] Address given address > > +**/ > > +VOID > > +AppendKeyPointToBuffer ( > > + IN OUT UINT64 *Buffer, > > + IN OUT UINTN *Count, > > + IN UINT64 Address > > + ) > > +{ > > + if ( Buffer != NULL) { > > + Buffer[*Count] = Address; > > + (*Count)++; > > + Buffer[*Count] = Address+1; > > + (*Count)++; > > + Buffer[*Count] = Address-1; > > + (*Count)++; > > + } else { > > + (*Count) = (*Count) +3; > > + } > > +} > > + > > +/** > > + Get all key points from a buffer > > + if buffer is NULL, only count needed count > > + > > + @param[in] MapEntrys Record every memory ranges that is used as > > input > > + @param[in] Map Pointer to an array that describes multiple linear > > address ranges. > > + @param[in] MapCount Pointer to a UINTN that hold the actual number > > of entries in the Map. > > + @param[in, out] Buffer Buffer to contains all key point. > > + @param[in, out] Count Count of the key point. > > +**/ > > +VOID > > +GetKeyPointList ( > > + IN MAP_ENTRYS *MapEntrys, > > + IN IA32_MAP_ENTRY *Map, > > + IN UINTN MapCount, > > + IN OUT UINT64 *Buffer, > > + IN OUT UINTN *Count > > + ) > > +{ > > + UINTN TemCount; > > + UINTN Index1; > > + UINTN Index2; > > + > > + TemCount = 0; > > + > > + for (Index1 = 0; Index1 < MapEntrys->Count; Index1++) { > > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > > >Maps[Index1].LinearAddress); > > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > > >Maps[Index1].LinearAddress + MapEntrys->Maps[Index1].Length); > > + } > > + > > + for (Index2 = 0; Index2 < MapCount; Index2++) { > > + if (Buffer != NULL) { > > + for (Index1 = 0; Index1 < TemCount; Index1++) { > > + if (Buffer[Index1] == Map[Index2].LinearAddress) { > > + break; > > + } > > + } > > + > > + if (Index1 < TemCount) { > > + continue; > > + } > > + } > > + > > + AppendKeyPointToBuffer (Buffer, &TemCount, > > Map[Index2].LinearAddress); > > + } > > + > > + for (Index2 = 0; Index2 < MapCount; Index2++) { > > + if (Buffer != NULL) { > > + for (Index1 = 0; Index1 < TemCount; Index1++) { > > + if (Buffer[Index1] == (Map[Index2].LinearAddress + > > Map[Index2].Length)) { > > + break; > > + } > > + } > > + > > + if (Index1 < TemCount) { > > + continue; > > + } > > + } > > + > > + AppendKeyPointToBuffer (Buffer, &TemCount, > > Map[Index2].LinearAddress + Map[Index2].Length); > > + } > > + > > + *Count = TemCount; > > +} > > + > > +/** > > + Generate random one range with randome attribute, and add it into > > pagetable > > + Compare the key point has same attribute > > + > > + @param[in, out] PageTable The pointer to the page table to update, or > > pointer to NULL if a new page table is to be created. > > + @param[in] PagingMode The paging mode. > > + @param[in] MaxAddress Max Address. > > + @param[in] MapEntrys Record every memory ranges that is used as > > input > > + @param[in] PagesRecord Used to record memory usage for page table. > > + @param[in] InitMap Pointer to an array that describes init map > > entries. > > + @param[in] InitMapCount Pointer to a UINTN that hold the number of > > init map entries. > > + > > + @retval UNIT_TEST_PASSED The test is successful. > > +**/ > > +UNIT_TEST_STATUS > > +SingleMapEntryTest ( > > + IN OUT UINTN *PageTable, > > + IN PAGING_MODE PagingMode, > > + IN UINT64 MaxAddress, > > + IN MAP_ENTRYS *MapEntrys, > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > + IN IA32_MAP_ENTRY *InitMap, > > + IN UINTN InitMapCount > > + ) > > +{ > > + UINTN MapsIndex; > > + RETURN_STATUS Status; > > + UINTN PageTableBufferSize; > > + VOID *Buffer; > > + IA32_MAP_ENTRY *Map; > > + UINTN MapCount; > > + UINTN Index; > > + UINTN KeyPointCount; > > + UINTN NewKeyPointCount; > > + UINT64 *KeyPointBuffer; > > + UINTN Level; > > + UINT64 Value; > > + UNIT_TEST_STATUS TestStatus; > > + > > + MapsIndex = MapEntrys->Count; > > + > > + GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); > > + > > + PageTableBufferSize = 0; > > + Status = PageTableMap ( > > + PageTable, > > + PagingMode, > > + NULL, > > + &PageTableBufferSize, > > + MapEntrys->Maps[MapsIndex].LinearAddress, > > + MapEntrys->Maps[MapsIndex].Length, > > + &MapEntrys->Maps[MapsIndex].Attribute, > > + &MapEntrys->Maps[MapsIndex].Mask > > + ); > > + if (PageTableBufferSize != 0) { > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + > > + // > > + // Allocate memory for Page table > > + // Note the memory is used in one complete fuzzy test. > > + // > > + Buffer = PagesRecord->AllocatePagesForPageTable (PagesRecord, > > EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > + UT_ASSERT_NOT_EQUAL (Buffer, NULL); > > + Status = PageTableMap ( > > + PageTable, > > + PagingMode, > > + Buffer, > > + &PageTableBufferSize, > > + MapEntrys->Maps[MapsIndex].LinearAddress, > > + MapEntrys->Maps[MapsIndex].Length, > > + &MapEntrys->Maps[MapsIndex].Attribute, > > + &MapEntrys->Maps[MapsIndex].Mask > > + ); > > + } > > + > > + if (Status != RETURN_SUCCESS ) { > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + } > > + > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + TestStatus = IsPageTableValid (*PageTable, PagingMode); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + MapCount = 0; > > + Status = PageTableParse (*PageTable, PagingMode, NULL, &MapCount); > > + if (MapCount != 0) { > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + > > + // > > + // Allocate memory for Maps > > + // Note the memory is only used in this one Single MapEntry Test > > + // > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof > > (IA32_MAP_ENTRY))); > > + ASSERT (Map != NULL); > > + Status = PageTableParse (*PageTable, PagingMode, Map, &MapCount); > > + } > > + > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + > > + // > > + // Allocate memory to record all key point > > + // Note the memory is only used in this one Single MapEntry Test > > + // > > + KeyPointCount = 0; > > + GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); > > + KeyPointBuffer = AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount * > > sizeof (UINT64))); > > + ASSERT (KeyPointBuffer != NULL); > > + NewKeyPointCount = 0; > > + GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, > > &NewKeyPointCount); > > + > > + // > > + // Compare all key point's attribute > > + // > > + for (Index = 0; Index < NewKeyPointCount; Index++) { > > + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, Map, > > MapCount, InitMap, InitMapCount)) { > > + DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); > > + DEBUG ((DEBUG_INFO, "Index = %d KeyPointBuffer[Index] = 0x%lx\n", > > Index, KeyPointBuffer[Index])); > > + Value = GetEntryFromPageTable (*PageTable, PagingMode, > > KeyPointBuffer[Index], &Level); > > + DEBUG ((DEBUG_INFO, "From Page table, this key point is in level %d > > entry, with entry value is 0x%lx\n", Level, Value)); > > + UT_ASSERT_TRUE (FALSE); > > + } > > + } > > + > > + FreePages (KeyPointBuffer, EFI_SIZE_TO_PAGES (KeyPointCount * sizeof > > (UINT64))); > > + if (MapCount != 0) { > > + FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof > > (IA32_MAP_ENTRY))); > > + } > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Allocate page and record the information in PagesRecord > > + > > + @param[in] PagesRecord Point to a struct to record memory usage > > + @param[in] Pages Page count needed to allocate > > + > > + @return A pointer to the allocated buffer or NULL if allocation fails. > > +**/ > > +VOID * > > +EFIAPI > > +RecordAllocatePages ( > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > + IN UINTN Pages > > + ) > > +{ > > + VOID *Buffer; > > + > > + Buffer = NULL; > > + if (PagesRecord->Count < PagesRecord->MaxCount) { > > + Buffer = AllocatePages (Pages); > > + PagesRecord->Records[PagesRecord->Count].Buffer = Buffer; > > + PagesRecord->Records[PagesRecord->Count].Pages = Pages; > > + PagesRecord->Count++; > > + } > > + > > + ASSERT (Buffer != NULL); > > + > > + return Buffer; > > +} > > + > > +/** > > + The function is a whole fuzzy test, it will call SingleMapEntryTest for > > ExpctedEntryNumber times > > + > > + @param[in] ExpctedEntryNumber The count of random entry > > + @param[in] PagingMode The paging mode. > > + > > + @retval UNIT_TEST_PASSED The test is successful. > > +**/ > > +UNIT_TEST_STATUS > > +MultipleMapEntryTest ( > > + IN UINTN ExpctedEntryNumber, > > + IN PAGING_MODE PagingMode > > + ) > > +{ > > + UINTN PageTable; > > + UINT64 MaxAddress; > > + MAP_ENTRYS *MapEntrys; > > + ALLOCATE_PAGE_RECORDS *PagesRecord; > > + UINTN Index; > > + UNIT_TEST_STATUS TestStatus; > > + RETURN_STATUS Status; > > + IA32_MAP_ENTRY *InitMap; > > + UINTN InitMapCount; > > + > > + MaxAddress = GetMaxAddress (PagingMode); > > + PageTable = 0; > > + MapEntrys = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > > (MAP_ENTRY) + sizeof (MAP_ENTRYS))); > > + ASSERT (MapEntrys != NULL); > > + MapEntrys->Count = 0; > > + MapEntrys->InitCount = 0; > > + MapEntrys->MaxCount = 1000; > > + PagesRecord = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > > + ASSERT (PagesRecord != NULL); > > + PagesRecord->Count = 0; > > + PagesRecord->MaxCount = 1000; > > + PagesRecord->AllocatePagesForPageTable = RecordAllocatePages; > > + > > + if (mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) { > > + ExpctedEntryNumber = ExpctedEntryNumber/2; > > + } > > + > > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > > + TestStatus = SingleMapEntryTest ( > > + &PageTable, > > + PagingMode, > > + MaxAddress, > > + MapEntrys, > > + PagesRecord, > > + NULL, > > + 0 > > + ); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + } > > + > > + if ((mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) != 0) { > > + MapEntrys->InitCount = ExpctedEntryNumber; > > + TestStatus = ValidateAndRandomeModifyPageTable (PageTable, > > PagingMode); > > + RandomNumber = 0; > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + > > + InitMapCount = 0; > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > &InitMapCount); > > + if (InitMapCount != 0) { > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > + > > + // > > + // Allocate memory for Maps > > + // Note the memory is only used in this one Single MapEntry Test > > + // > > + InitMap = AllocatePages (EFI_SIZE_TO_PAGES (InitMapCount * sizeof > > (IA32_MAP_ENTRY))); > > + ASSERT (InitMap != NULL); > > + Status = PageTableParse (PageTable, PagingMode, InitMap, > > &InitMapCount); > > + } > > + > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > > + TestStatus = SingleMapEntryTest ( > > + &PageTable, > > + PagingMode, > > + MaxAddress, > > + MapEntrys, > > + PagesRecord, > > + InitMap, > > + InitMapCount > > + ); > > + if (TestStatus != UNIT_TEST_PASSED) { > > + return TestStatus; > > + } > > + } > > + > > + if (InitMapCount != 0) { > > + FreePages (InitMap, EFI_SIZE_TO_PAGES (InitMapCount*sizeof > > (IA32_MAP_ENTRY))); > > + } > > + } > > + > > + FreePages ( > > + MapEntrys, > > + EFI_SIZE_TO_PAGES (1000*sizeof (MAP_ENTRY) + sizeof (MAP_ENTRYS)) > > + ); > > + > > + for (Index = 0; Index < PagesRecord->Count; Index++) { > > + FreePages (PagesRecord->Records[Index].Buffer, PagesRecord- > > >Records[Index].Pages); > > + } > > + > > + FreePages (PagesRecord, EFI_SIZE_TO_PAGES (1000*sizeof > > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Fuzzy Test > > + > > + @param[in] Context [Optional] An optional parameter that enables: > > + 1) test-case reuse with varied parameters and > > + 2) test-case re-entry for Target tests that need a > > + reboot. This parameter is a VOID* and it is the > > + responsibility of the test author to ensure that the > > + contents are well understood by all test cases that may > > + consume it. > > + > > + @retval UNIT_TEST_PASSED The Unit test has completed and the > > test > > + case was successful. > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has failed. > > +**/ > > +UNIT_TEST_STATUS > > +EFIAPI > > +TestCaseforFuzzyTest ( > > + IN UNIT_TEST_CONTEXT Context > > + ) > > +{ > > + UNIT_TEST_STATUS Status; > > + UINTN Index; > > + > > + UT_ASSERT_EQUAL (RandomSeed (NULL, 0), TRUE); > > + UT_ASSERT_EQUAL (Random32 (100, 100), 100); > > + UT_ASSERT_EQUAL (Random64 (100, 100), 100); > > + UT_ASSERT_TRUE ((Random32 (9, 10) >= 9) & (Random32 (9, 10) <= 10)); > > + UT_ASSERT_TRUE ((Random64 (9, 10) >= 9) & (Random64 (9, 10) <= 10)); > > + > > + mSupportedBit.Bits.Present = 1; > > + mSupportedBit.Bits.ReadWrite = 1; > > + mSupportedBit.Bits.UserSupervisor = 1; > > + mSupportedBit.Bits.WriteThrough = 1; > > + mSupportedBit.Bits.CacheDisabled = 1; > > + mSupportedBit.Bits.Accessed = 1; > > + mSupportedBit.Bits.Dirty = 1; > > + mSupportedBit.Bits.Pat = 1; > > + mSupportedBit.Bits.Global = 1; > > + mSupportedBit.Bits.Reserved1 = 0; > > + mSupportedBit.Bits.PageTableBaseAddress = 0; > > + mSupportedBit.Bits.Reserved2 = 0; > > + mSupportedBit.Bits.ProtectionKey = 0xF; > > + mSupportedBit.Bits.Nx = 1; > > + > > + mFuzzOption = ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > *)Context)->FuzzOption; > > + mNumberIndex = 0; > > + > > + for (Index = 0; Index < ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > *)Context)->TestCount; Index++) { > > + Status = MultipleMapEntryTest ( > > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > > >TestRangeCount, > > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > > >PagingMode > > + ); > > + if (Status != UNIT_TEST_PASSED) { > > + return Status; > > + } > > + > > + DEBUG ((DEBUG_INFO, ".")); > > + } > > + > > + DEBUG ((DEBUG_INFO, "\n")); > > + > > + return UNIT_TEST_PASSED; > > +} > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > new file mode 100644 > > index 0000000000..e7c35b1c29 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > @@ -0,0 +1,57 @@ > > +/** @file > > + Internal header for fuzzy test. > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef FUZZY_TEST_H_ > > +#define FUZZY_TEST_H_ > > + > > +#include "CpuPageTableLibUnitTest.h" > > + > > +typedef struct _ALLOCATE_PAGE_RECORDS ALLOCATE_PAGE_RECORDS; > > + > > +typedef > > +VOID * > > +(EFIAPI *ALLOCATE_PAGES)( > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > + IN UINTN Pages > > + ); > > + > > +typedef struct { > > + VOID *Buffer; > > + UINTN Pages; > > +} ALLOCATE_PAGE_RECORD; > > + > > +struct _ALLOCATE_PAGE_RECORDS { > > + UINTN Count; > > + UINTN MaxCount; > > + ALLOCATE_PAGES AllocatePagesForPageTable; > > + ALLOCATE_PAGE_RECORD Records[0]; > > +}; > > + > > +typedef struct { > > + UINT64 LinearAddress; > > + UINT64 Length; > > + IA32_MAP_ATTRIBUTE Attribute; > > + IA32_MAP_ATTRIBUTE Mask; > > +} MAP_ENTRY; > > + > > +typedef struct { > > + UINTN Count; > > + UINTN InitCount; > > + UINTN MaxCount; > > + MAP_ENTRY Maps[10]; > > +} MAP_ENTRYS; > > + > > +UINT64 > > +GetEntryFromPageTable ( > > + IN UINTN PageTable, > > + IN PAGING_MODE PagingMode, > > + IN UINT64 Address, > > + OUT UINTN *Level > > + ); > > + > > +#endif > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > new file mode 100644 > > index 0000000000..4ccbc47d9e > > --- /dev/null > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > @@ -0,0 +1,5009 @@ > > +/** @file > > + Pre-generated random number used by CpuPageTableLib test. > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + **/ > > +UINTN mNumberCount = 50000; > > +UINT8 mNumbers[] = { > > + 250, 22, 243, 87, 160, 129, 26, 103, 242, 136, > > + 193, 195, 125, 183, 205, 246, 65, 169, 187, 121, > > + 129, 195, 32, 183, 49, 100, 34, 51, 143, 84, > > + 215, 111, 113, 121, 59, 119, 33, 56, 224, 245, > > + 254, 244, 114, 20, 63, 216, 118, 253, 145, 171, > > + 108, 208, 155, 4, 47, 174, 154, 5, 92, 107, > > + 127, 176, 76, 238, 147, 4, 21, 26, 116, 251, > > + 54, 33, 126, 239, 125, 21, 188, 17, 65, 2, > > + 176, 77, 54, 82, 60, 32, 133, 105, 5, 211, > > + 41, 67, 24, 246, 122, 160, 96, 3, 27, 53, > > + 116, 129, 220, 46, 16, 251, 49, 70, 149, 153, > > + 14, 102, 69, 131, 125, 166, 221, 13, 36, 189, > > + 103, 28, 229, 50, 217, 174, 163, 98, 1, 101, > > + 226, 237, 164, 232, 153, 165, 48, 155, 152, 26, > > + 112, 129, 155, 23, 84, 154, 53, 147, 240, 195, > > + 248, 207, 129, 49, 35, 151, 90, 77, 170, 216, > > + 27, 51, 143, 214, 195, 161, 61, 219, 68, 106, > > + 159, 225, 204, 197, 59, 176, 37, 203, 61, 23, > > + 12, 76, 116, 118, 169, 250, 161, 68, 2, 247, > > + 184, 242, 199, 226, 86, 150, 216, 112, 116, 194, > > + 57, 173, 11, 146, 23, 244, 168, 185, 85, 234, > > + 57, 209, 48, 95, 130, 137, 107, 148, 113, 152, > > + 28, 152, 53, 2, 180, 115, 18, 32, 93, 178, > > + 158, 230, 216, 3, 230, 150, 244, 153, 200, 24, > > + 54, 195, 181, 205, 234, 159, 76, 162, 92, 91, > > + 255, 87, 145, 10, 250, 76, 150, 79, 13, 48, > > + 119, 161, 245, 145, 56, 216, 107, 237, 189, 197, > > + 192, 90, 52, 251, 176, 247, 163, 5, 82, 56, > > + 234, 155, 160, 208, 252, 10, 1, 148, 153, 21, > > + 221, 42, 205, 226, 6, 13, 243, 146, 123, 14, > > + 234, 102, 179, 156, 13, 30, 31, 182, 179, 252, > > + 32, 174, 65, 247, 53, 152, 106, 134, 120, 116, > > + 188, 59, 59, 217, 26, 39, 113, 246, 170, 127, > > + 91, 18, 15, 117, 9, 175, 165, 92, 111, 208, > > + 250, 48, 33, 57, 14, 129, 154, 4, 95, 216, > > + 76, 51, 80, 234, 173, 189, 203, 146, 54, 6, > > + 225, 175, 138, 148, 49, 123, 112, 211, 195, 119, > > + 248, 241, 24, 60, 0, 70, 109, 54, 49, 157, > > + 240, 15, 171, 235, 76, 60, 236, 105, 92, 183, > > + 238, 160, 203, 157, 205, 246, 149, 13, 246, 67, > > + 205, 249, 245, 154, 81, 30, 149, 145, 227, 208, > > + 65, 190, 72, 232, 102, 176, 69, 231, 156, 85, > > + 216, 241, 192, 157, 88, 169, 247, 23, 200, 41, > > + 247, 62, 173, 240, 35, 52, 98, 224, 159, 53, > > + 15, 141, 59, 213, 100, 28, 76, 48, 26, 73, > > + 48, 209, 164, 18, 176, 99, 15, 248, 154, 240, > > + 134, 70, 217, 179, 133, 76, 222, 185, 247, 40, > > + 139, 101, 85, 137, 197, 186, 89, 66, 35, 127, > > + 31, 201, 231, 81, 39, 206, 99, 231, 106, 26, > > + 69, 72, 208, 207, 49, 227, 141, 233, 41, 247, > > + 176, 102, 47, 51, 237, 80, 88, 149, 229, 18, > > + 89, 77, 126, 156, 32, 72, 132, 216, 247, 142, > > + 103, 179, 220, 178, 162, 133, 215, 249, 52, 160, > > + 25, 223, 226, 103, 4, 253, 103, 93, 191, 46, > > + 250, 20, 186, 223, 145, 73, 114, 195, 159, 76, > > + 44, 215, 46, 142, 190, 141, 201, 241, 134, 40, > > + 135, 140, 28, 105, 147, 102, 55, 210, 102, 44, > > + 180, 229, 217, 207, 46, 145, 161, 94, 8, 44, > > + 110, 4, 38, 254, 174, 75, 36, 64, 113, 51, > > + 98, 73, 97, 94, 147, 101, 168, 22, 67, 232, > > + 3, 20, 35, 104, 166, 105, 168, 45, 133, 122, > > + 101, 170, 238, 103, 31, 245, 66, 16, 81, 166, > > + 68, 155, 34, 71, 172, 186, 156, 37, 105, 171, > > + 90, 137, 248, 76, 123, 220, 208, 138, 209, 48, > > + 127, 195, 191, 150, 19, 19, 148, 229, 91, 73, > > + 204, 28, 112, 141, 239, 86, 130, 65, 238, 77, > > + 0, 133, 137, 105, 62, 107, 0, 132, 109, 180, > > + 182, 194, 215, 232, 207, 171, 189, 50, 169, 186, > > + 177, 76, 56, 56, 155, 204, 176, 145, 80, 67, > > + 178, 229, 32, 144, 10, 182, 98, 7, 129, 74, > > + 216, 213, 96, 172, 206, 205, 27, 4, 215, 121, > > + 55, 60, 73, 234, 223, 181, 60, 150, 32, 212, > > + 254, 35, 202, 173, 9, 234, 0, 103, 229, 21, > > + 23, 137, 101, 75, 102, 40, 225, 180, 203, 121, > > + 109, 172, 227, 249, 172, 75, 126, 33, 1, 20, > > + 130, 66, 205, 131, 154, 16, 72, 184, 76, 10, > > + 98, 226, 65, 208, 177, 154, 111, 80, 130, 27, > > + 46, 224, 46, 113, 61, 227, 125, 136, 118, 129, > > + 121, 144, 140, 83, 197, 235, 226, 140, 141, 154, > > + 240, 173, 133, 114, 138, 101, 114, 242, 73, 70, > > + 104, 236, 72, 141, 58, 129, 108, 211, 11, 189, > > + 212, 95, 37, 117, 40, 236, 67, 168, 251, 228, > > + 111, 152, 209, 130, 3, 209, 8, 21, 217, 223, > > + 202, 134, 159, 13, 126, 137, 150, 185, 93, 207, > > + 218, 38, 77, 183, 197, 250, 134, 36, 184, 228, > > + 213, 109, 220, 69, 219, 229, 39, 153, 78, 125, > > + 223, 57, 239, 131, 116, 73, 4, 147, 105, 239, > > + 132, 57, 160, 255, 66, 233, 145, 183, 225, 82, > > + 170, 151, 244, 113, 130, 180, 63, 66, 236, 237, > > + 7, 82, 29, 141, 83, 61, 93, 219, 79, 89, > > + 192, 102, 77, 47, 191, 96, 250, 191, 186, 235, > > + 24, 40, 244, 70, 91, 193, 102, 171, 110, 55, > > + 158, 127, 226, 211, 86, 16, 56, 42, 20, 81, > > + 143, 82, 47, 189, 112, 85, 246, 111, 177, 229, > > + 28, 179, 101, 35, 114, 38, 148, 26, 134, 246, > > + 123, 102, 141, 0, 11, 207, 173, 232, 92, 129, > > + 182, 97, 175, 143, 89, 42, 112, 238, 3, 137, > > + 96, 51, 150, 148, 20, 71, 4, 209, 94, 181, > > + 232, 175, 110, 244, 148, 44, 172, 99, 129, 161, > > + 253, 136, 100, 180, 141, 103, 81, 153, 96, 213, > > + 250, 140, 9, 89, 93, 123, 166, 177, 85, 235, > > + 56, 72, 63, 15, 164, 161, 5, 68, 214, 188, > > + 93, 15, 41, 64, 233, 117, 0, 9, 255, 96, > > + 190, 47, 27, 209, 79, 28, 117, 202, 185, 211, > > + 58, 184, 150, 75, 67, 22, 36, 243, 148, 21, > > + 218, 208, 214, 68, 173, 218, 164, 50, 139, 85, > > + 108, 106, 134, 4, 22, 210, 181, 209, 187, 239, > > + 137, 19, 250, 75, 93, 117, 214, 21, 138, 62, > > + 249, 172, 72, 36, 209, 119, 198, 35, 156, 231, > > + 7, 3, 153, 29, 46, 197, 147, 47, 105, 234, > > + 129, 160, 130, 96, 231, 27, 178, 11, 180, 172, > > + 155, 168, 14, 66, 73, 211, 143, 171, 42, 61, > > + 36, 34, 207, 31, 56, 158, 138, 30, 125, 238, > > + 145, 56, 93, 233, 231, 195, 115, 208, 54, 131, > > + 171, 11, 13, 151, 41, 39, 165, 132, 44, 147, > > + 79, 140, 107, 103, 189, 108, 51, 24, 178, 214, > > + 21, 139, 25, 240, 231, 36, 17, 132, 246, 211, > > + 87, 62, 149, 98, 27, 209, 189, 72, 11, 181, > > + 151, 161, 3, 254, 90, 120, 62, 40, 36, 49, > > + 71, 206, 33, 234, 57, 76, 112, 23, 79, 22, > > + 181, 9, 105, 251, 193, 84, 103, 75, 114, 30, > > + 49, 0, 36, 168, 169, 205, 11, 154, 187, 2, > > + 115, 168, 242, 251, 244, 124, 77, 39, 174, 42, > > + 182, 162, 124, 76, 201, 92, 47, 110, 5, 122, > > + 35, 139, 212, 181, 239, 120, 99, 105, 29, 143, > > + 109, 13, 242, 219, 38, 82, 197, 44, 28, 160, > > + 7, 181, 82, 144, 156, 83, 28, 68, 240, 147, > > + 119, 247, 130, 55, 158, 175, 41, 23, 126, 98, > > + 89, 192, 233, 22, 24, 13, 170, 83, 122, 125, > > + 28, 72, 120, 237, 115, 29, 171, 236, 52, 187, > > + 191, 160, 36, 10, 104, 77, 170, 46, 138, 53, > > + 42, 89, 131, 119, 94, 198, 237, 180, 158, 81, > > + 202, 1, 238, 141, 245, 65, 108, 177, 235, 9, > > + 156, 167, 59, 55, 105, 49, 191, 116, 110, 255, > > + 121, 123, 87, 28, 80, 47, 10, 24, 228, 107, > > + 99, 107, 167, 144, 174, 2, 89, 53, 62, 151, > > + 143, 221, 30, 226, 135, 203, 50, 39, 96, 119, > > + 46, 121, 13, 178, 103, 245, 218, 141, 158, 112, > > + 155, 1, 7, 130, 35, 6, 57, 67, 59, 27, > > + 81, 136, 147, 51, 17, 147, 119, 236, 173, 150, > > + 150, 241, 201, 35, 31, 144, 12, 121, 118, 165, > > + 102, 70, 234, 179, 183, 60, 19, 159, 217, 6, > > + 207, 87, 88, 189, 215, 198, 244, 7, 16, 143, > > + 24, 132, 116, 74, 205, 147, 33, 232, 141, 96, > > + 140, 249, 67, 82, 57, 38, 34, 238, 161, 2, > > + 201, 207, 5, 110, 75, 231, 239, 22, 255, 56, > > + 240, 136, 105, 207, 223, 48, 232, 80, 185, 123, > > + 141, 234, 193, 197, 6, 90, 131, 174, 106, 69, > > + 229, 72, 160, 206, 180, 33, 252, 101, 106, 215, > > + 156, 77, 114, 112, 216, 83, 222, 171, 159, 89, > > + 118, 222, 93, 201, 24, 253, 217, 106, 2, 0, > > + 39, 155, 55, 17, 239, 248, 253, 49, 103, 138, > > + 134, 229, 134, 186, 41, 83, 29, 234, 126, 216, > > + 157, 210, 47, 165, 225, 24, 217, 124, 130, 5, > > + 58, 154, 111, 116, 92, 38, 159, 228, 172, 92, > > + 44, 103, 7, 140, 88, 54, 12, 17, 112, 179, > > + 69, 216, 27, 29, 50, 239, 219, 127, 136, 152, > > + 84, 245, 136, 253, 80, 7, 64, 21, 177, 0, > > + 163, 145, 228, 238, 202, 102, 127, 239, 186, 14, > > + 15, 136, 193, 114, 112, 137, 146, 108, 47, 103, > > + 238, 71, 223, 170, 56, 97, 31, 246, 74, 219, > > + 7, 17, 111, 9, 96, 140, 99, 7, 33, 13, > > + 117, 222, 117, 86, 165, 179, 49, 135, 235, 75, > > + 132, 61, 18, 248, 235, 81, 182, 255, 9, 149, > > + 218, 63, 96, 10, 123, 79, 78, 64, 221, 25, > > + 67, 33, 113, 24, 90, 123, 223, 86, 228, 242, > > + 134, 21, 240, 230, 10, 184, 65, 103, 157, 183, > > + 130, 5, 253, 139, 60, 105, 38, 39, 217, 29, > > + 203, 117, 213, 90, 150, 45, 153, 143, 121, 202, > > + 251, 57, 58, 88, 212, 152, 195, 43, 7, 92, > > + 227, 14, 74, 242, 54, 172, 135, 150, 101, 247, > > + 81, 82, 240, 10, 46, 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> > + 158, 4, 160, 57, 117, 84, 41, 9, 21, 86, > > + 104, 209, 163, 107, 6, 137, 161, 253, 242, 85, > > + 166, 6, 245, 42, 205, 152, 218, 1, 69, 165, > > + 236, 147, 74, 16, 189, 230, 43, 10, 61, 220, > > + 116, 113, 255, 180, 85, 106, 210, 92, 133, 126, > > + 142, 170, 254, 33, 4, 0, 236, 176, 208, 196, > > + 158, 26, 123, 234, 44, 208, 75, 235, 27, 18, > > + 128, 224, 110, 251, 122, 13, 153, 252, 65, 134, > > + 33, 112, 38, 70, 80, 234, 79, 226, 64, 110, > > + 74, 105, 183, 178, 198, 67, 216, 60, 168, 214, > > + 132, 207, 236, 79, 27, 33, 49, 229, 193, 109, > > + 252, 244, 167, 231, 99, 166, 9, 135, 75, 45, > > + 187, 184, 57, 250, 87, 80, 229, 197, 209, 184, > > + 203, 68, 67, 6, 216, 113, 154, 190, 103, 60, > > + 245, 14, 241, 222, 100, 40, 140, 71, 101, 198, > > + 240, 157, 61, 25, 242, 244, 25, 247, 9, 198, > > + 104, 170, 162, 26, 89, 39, 27, 173, 160, 67, > > + 113, 198, 128, 46, 59, 251, 55, 214, 164, 102, > > + 223, 141, 167, 95, 78, 151, 44, 210, 144, 143, > > + 171, 100, 140, 187, 23, 178, 14, 55, 249, 68, > > + 187, 200, 201, 50, 7, 30, 155, 254, 77, 159, > > + 34, 123, 101, 249, 230, 56, 130, 54, 180, 151, > > + 124, 15, 219, 98, 165, 58, 39, 195, 87, 139, > > + 0, 45, 140, 182, 223, 51, 214, 19, 61, 109, > > + 205, 84, 12, 127, 75, 233, 139, 204, 87, 34, > > + 88, 88, 98, 29, 63, 106, 233, 163, 234, 183, > > + 166, 56, 113, 26, 49, 51, 25, 104, 147, 183, > > + 152, 76, 62, 12, 117, 217, 99, 100, 213, 202, > > + 239, 172, 24, 50, 212, 156, 251, 63, 34, 70, > > + 159, 92, 35, 196, 181, 253, 192, 146, 145, 35, > > + 123, 6, 47, 227, 2, 211, 115, 145, 73, 0, > > + 179, 66, 17, 197, 86, 70, 106, 18, 162, 122, > > + 186, 101, 137, 166, 232, 109, 82, 247, 223, 111, > > +}; > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > new file mode 100644 > > index 0000000000..5bd70c0f65 > > --- /dev/null > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > @@ -0,0 +1,309 @@ > > +/** @file > > + helper file for Unit tests of the CpuPageTableLib instance of the > > CpuPageTableLib class > > + > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#include "CpuPageTableLibUnitTest.h" > > +#include "../CpuPageTable.h" > > + > > +// > > +// Global Data to validate if the page table is legal > > +// mValidMaskNoLeaf[0] is not used > > +// mValidMaskNoLeaf[1] ... mValidMaskNoLeaf [5] represent PTE ... PML5E > > +// mValidMaskNoLeaf[Index] means if it is a valid no leaf entry, entry > > should equal to (entry & mValidMaskNoLeaf[Index]) > > +// mValidMaskLeaf[Index] means if it is a valid leaf entry, entry should > > equal to (entry & mValidMaskLeaf[Index]) > > +// mValidMaskLeafFlag[Index] means if it is a leaf entry, if and only if ((entry > > & mValidMaskLeafFlag[Index]) == mValidMaskLeafFlag[Index]) > > +// > > +IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > > +IA32_PAGING_ENTRY mValidMaskLeaf[6]; > > +IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > > + > > +/** > > + Init global data. > > + > > + @param[in] MemorySpace Memory space > > +**/ > > +VOID > > +InitGlobalData ( > > + UINTN MemorySpace > > + ) > > +{ > > + UINTN Index; > > + > > + ASSERT (MemorySpace <= 52); > > + mValidMaskNoLeaf[0].Uint64 = 0; > > + mValidMaskLeaf[0].Uint64 = 0; > > + mValidMaskLeafFlag[0].Uint64 = 0; > > + > > + // > > + // Set common part for all kinds of entrys. > > + // > > + for (Index = 1; Index < 6; Index++) { > > + mValidMaskNoLeaf[Index].Uint64 = MAX_UINT64; > > + mValidMaskLeaf[Index].Uint64 = MAX_UINT64; > > + > > + // > > + // bit 51:M is reserved, and should be zero > > + // > > + if (MemorySpace - 1 < 51) { > > + mValidMaskNoLeaf[Index].Uint64 = BitFieldWrite64 > > (mValidMaskNoLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > > + mValidMaskLeaf[Index].Uint64 = BitFieldWrite64 > > (mValidMaskLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > > + } > > + } > > + > > + // > > + // Handle mask for no leaf entry. > > + // > > + mValidMaskNoLeaf[1].Uint64 = 0; // PTE can't map to page > > structure. > > + mValidMaskNoLeaf[2].Pnle.Bits.MustBeZero = 0; // for PML4E, bit 7 must > > be zero. > > + mValidMaskNoLeaf[3].Pnle.Bits.MustBeZero = 0; // for PML5E, bit 7 must > > be zero. > > + mValidMaskNoLeaf[4].Pml4.Bits.MustBeZero = 0; // for PML4E, bit 7 must > > be zero. > > + mValidMaskNoLeaf[5].Pml4.Bits.MustBeZero = 0; // for PML5E, bit 7 must > > be zero. > > + > > + // > > + // Handle mask for leaf entry. > > + // No need to modification for PTE, since it doesn't have extra reserved bit > > + // > > + mValidMaskLeaf[2].Uint64 = BitFieldWrite64 (mValidMaskLeaf[2].Uint64, > > 13, 20, 0); // bit 13-20 is reserved for PDE > > + mValidMaskLeaf[3].Uint64 = BitFieldWrite64 (mValidMaskLeaf[2].Uint64, > > 13, 29, 0); // bit 13-29 is reserved for PDPTE > > + mValidMaskLeaf[4].Uint64 = 0; // for PML4E, no > > possible to map to page. > > + mValidMaskLeaf[5].Uint64 = 0; // for PML5E, no > > possible to map to page. > > + > > + // > > + // Handle Flags to indicate it is a leaf entry. > > + // for PML4E and PML5E, no possible to map to page, so the flag should be > > MAX_UINT64. > > + // > > + mValidMaskLeafFlag[1].Pce.Present = 1; // For PTE, as long as it is present, > > it maps to page > > + // > > + // For PDE and PDPTE, the bit 7 should be set to map to pages > > + // > > + mValidMaskLeafFlag[2].Pde2M.Bits.MustBeOne = 1; > > + mValidMaskLeafFlag[2].Pde2M.Bits.Present = 1; > > + mValidMaskLeafFlag[3].Pde2M.Bits.MustBeOne = 1; > > + mValidMaskLeafFlag[3].Pde2M.Bits.Present = 1; > > + mValidMaskLeafFlag[4].Uint64 = MAX_UINT64; > > + mValidMaskLeafFlag[5].Uint64 = MAX_UINT64; > > +} > > + > > +/** > > + Check if the Page table entry is valid > > + > > + @param[in] PagingEntry The entry in page table to verify > > + @param[in] Level the level of PagingEntry. > > + @param[in] MaxLeafLevel Max leaf entry level. > > + @param[in] LinearAddress The linear address verified. > > + > > + @retval Leaf entry. > > +**/ > > +UNIT_TEST_STATUS > > +IsPageTableEntryValid ( > > + IN IA32_PAGING_ENTRY *PagingEntry, > > + IN UINTN Level, > > + IN UINTN MaxLeafLevel, > > + IN UINT64 Address > > + ) > > +{ > > + UINT64 Index; > > + IA32_PAGING_ENTRY *ChildPageEntry; > > + UNIT_TEST_STATUS Status; > > + > > + if (PagingEntry->Pce.Present == 0) { > > + return UNIT_TEST_PASSED; > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > > mValidMaskLeafFlag[Level].Uint64) { > > + // > > + // It is a Leaf > > + // > > + if (Level > MaxLeafLevel) { > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d entry 0x%lx is a leaf entry, > > but max leaf level is %d \n", Level, PagingEntry->Uint64, MaxLeafLevel)); > > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != PagingEntry- > > >Uint64) { > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d Leaf entry is 0x%lx, which > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > + } > > + > > + return UNIT_TEST_PASSED; > > + } > > + > > + // > > + // Not a leaf > > + // > > + UT_ASSERT_NOT_EQUAL (Level, 1); > > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > > PagingEntry->Uint64) { > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, which > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > > + } > > + > > + ChildPageEntry = (IA32_PAGING_ENTRY > > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); > > + for (Index = 0; Index < 512; Index++) { > > + Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, > > MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); > > + if (Status != UNIT_TEST_PASSED) { > > + return Status; > > + } > > + } > > + > > + return UNIT_TEST_PASSED; > > +} > > + > > +/** > > + Check if the Page table is valid > > + > > + @param[in] PageTable The pointer to the page table. > > + @param[in] PagingMode The paging mode. > > + > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > +**/ > > +UNIT_TEST_STATUS > > +IsPageTableValid ( > > + IN UINTN PageTable, > > + IN PAGING_MODE PagingMode > > + ) > > +{ > > + UINTN MaxLevel; > > + UINTN MaxLeafLevel; > > + UINT64 Index; > > + UNIT_TEST_STATUS Status; > > + IA32_PAGING_ENTRY *PagingEntry; > > + > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > (PagingMode >= PagingModeMax)) { > > + // > > + // 32bit paging is never supported. > > + // PAE paging will be supported later. > > + // > > + return UNIT_TEST_ERROR_TEST_FAILED; > > + } > > + > > + MaxLeafLevel = (UINT8)PagingMode; > > + MaxLevel = (UINT8)(PagingMode >> 8); > > + > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > + for (Index = 0; Index < 512; Index++) { > > + Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, > > MaxLeafLevel, Index << (9 * MaxLevel + 3)); > > + if (Status != UNIT_TEST_PASSED) { > > + return Status; > > + } > > + } > > + > > + return Status; > > +} > > + > > +/** > > + Get the leaf entry for a given linear address from one entry in page table > > + > > + @param[in] PagingEntry The entry in page table which covers the > > linear address > > + @param[in, out] Level On input, is the level of PagingEntry. > > + On outout, is the level of the leaf entry > > + @param[in] MaxLeafLevel Max leaf entry level. > > + @param[in] LinearAddress The linear address. > > + > > + @retval Leaf entry. > > +**/ > > +UINT64 > > +GetEntryFromSubPageTable ( > > + IN IA32_PAGING_ENTRY *PagingEntry, > > + IN OUT UINTN *Level, > > + IN UINTN MaxLeafLevel, > > + IN UINT64 Address > > + ) > > +{ > > + UINT64 Index; > > + IA32_PAGING_ENTRY *ChildPageEntry; > > + > > + if (PagingEntry->Pce.Present == 0) { > > + return 0; > > + } > > + > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[*Level].Uint64) == > > mValidMaskLeafFlag[*Level].Uint64) { > > + // > > + // It is a Leaf > > + // > > + return PagingEntry->Uint64; > > + } > > + > > + // > > + // Not a leaf > > + // > > + ChildPageEntry = (IA32_PAGING_ENTRY > > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << 12); > > + *Level = *Level -1; > > + Index = Address >> (*Level * 9 + 3); > > + ASSERT (Index == (Index & ((1<< 9) - 1))); > > + > > + return GetEntryFromSubPageTable (&ChildPageEntry[Index], Level, > > MaxLeafLevel, Address - (Index << (9 * *Level + 3))); > > +} > > + > > +/** > > + Get the leaf entry for a given linear address from a page table > > + > > + @param[in] PageTable The pointer to the page table. > > + @param[in] PagingMode The paging mode. > > + @param[in] LinearAddress The linear address. > > + @param[out] Level leaf entry's level. > > + > > + @retval Leaf entry. > > +**/ > > +UINT64 > > +GetEntryFromPageTable ( > > + IN UINTN PageTable, > > + IN PAGING_MODE PagingMode, > > + IN UINT64 Address, > > + OUT UINTN *Level > > + ) > > +{ > > + UINTN MaxLevel; > > + UINTN MaxLeafLevel; > > + UINT64 Index; > > + IA32_PAGING_ENTRY *PagingEntry; > > + > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > (PagingMode >= PagingModeMax)) { > > + // > > + // 32bit paging is never supported. > > + // PAE paging will be supported later. > > + // > > + return 0; > > + } > > + > > + MaxLeafLevel = (UINT8)PagingMode; > > + MaxLevel = (UINT8)(PagingMode >> 8); > > + > > + Index = Address >> (MaxLevel * 9 + 3); > > + ASSERT (Index == (Index & ((1<< 9) - 1))); > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > + *Level = MaxLevel; > > + > > + return GetEntryFromSubPageTable (&PagingEntry[Index], Level, > > MaxLeafLevel, Address - (Index << (9 * MaxLevel + 3))); > > +} > > + > > +/** > > + Get max physical adrress supported by specific page mode > > + > > + @param[in] Mode The paging mode. > > + > > + @retval max address. > > +**/ > > +UINT64 > > +GetMaxAddress ( > > + IN PAGING_MODE Mode > > + ) > > +{ > > + switch (Mode) { > > + case Paging32bit: > > + case PagingPae: > > + return SIZE_4GB; > > + > > + case Paging4Level: > > + case Paging4Level1GB: > > + case Paging5Level: > > + case Paging5Level1GB: > > + return 1ull << MIN (12 + (Mode >> 8) * 9, 52); > > + > > + default: > > + ASSERT (0); > > + return 0; > > + } > > +} > > diff --git a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > index 8a5c456830..e72e4cd622 100644 > > --- a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > +++ b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > @@ -20,6 +20,10 @@ > > > > [LibraryClasses] > > MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf > > + > > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > > + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf > > + > > BaseCryptLib|CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf > > + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf > > > > [PcdsPatchableInModule] > > gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 > > @@ -29,3 +33,8 @@ > > # Build HOST_APPLICATION that tests the MtrrLib > > # > > UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTestHost.inf > > + > > + # > > + # Build HOST_APPLICATION that tests the CpuPageTableLib > > + # > > + > > UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo > > st.inf > > diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml > > b/UefiCpuPkg/UefiCpuPkg.ci.yaml > > index 6e0ab95fd8..bbdc44a45b 100644 > > --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml > > +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml > > @@ -15,6 +15,7 @@ > > ## "<ErrorID>", "<KeyWord>" > > ## ] > > "ExceptionList": [ > > + "8006", "main" > > ], > > ## Both file path and directory path are accepted. > > "IgnoreFiles": [ > > @@ -38,7 +39,8 @@ > > ], > > # For host based unit tests > > "AcceptableDependencies-HOST_APPLICATION":[ > > - "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec" > > + "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec", > > + "CryptoPkg/CryptoPkg.dec" > > ], > > # For UEFI shell based apps > > "AcceptableDependencies-UEFI_APPLICATION":[], > > -- > > 2.31.1.windows.1 > > > > > > > > > > > > > > > ^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test 2022-08-12 18:12 ` Michael D Kinney @ 2022-08-15 3:23 ` Zhiguang Liu 0 siblings, 0 replies; 3+ messages in thread From: Zhiguang Liu @ 2022-08-15 3:23 UTC (permalink / raw) To: Kinney, Michael D, devel@edk2.groups.io Cc: Dong, Eric, Ni, Ray, Kumar, Rahul R Hi Mike, Thanks for the comments, I agree fuzz term will cause confusion. I will remove the fuzz term in next version patch. Thanks Zhiguang > -----Original Message----- > From: Kinney, Michael D <michael.d.kinney@intel.com> > Sent: Saturday, August 13, 2022 2:12 AM > To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@intel.com>; Kinney, > Michael D <michael.d.kinney@intel.com> > Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, > Rahul R <rahul.r.kumar@intel.com> > Subject: RE: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: > Add host based unit test > > Hi Zhiguang, > > Thank you for adding unit tests for this component. > > I do want to make sure we are using consistent terminology related to > different type of testing. > > I think what you have implemented here consists of randomly generated > test vectors. > > I think fuzz testing usually involves the use of fuzzing tools that perform > source code analysis > to generate a focused set of test vectors that exercise different code paths > and data patterns. > > If your style is randomly generated test vectors without the use of fuzzing > tools, > then I recommend we do not use the terms "Fuzz" or "FUZZ" in the unit test > sources. > Perhaps use terms like "Random" and "RANDOM". > > Thanks, > > Mike > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > Zhiguang Liu > > Sent: Friday, August 12, 2022 2:20 AM > > To: devel@edk2.groups.io; Liu, Zhiguang <zhiguang.liu@intel.com> > > Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, > Rahul R <rahul.r.kumar@intel.com> > > Subject: Re: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: > Add host based unit test > > > > Hi all, > > This patch contains a big C file, containing random number to make it > possible to reproduce issue in fuzzy test. > > If the mail is hard to review, please review from > https://github.com/tianocore/edk2/pull/3201 > > > > Thanks > > Zhiguang > > > > > -----Original Message----- > > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of > > > Zhiguang Liu > > > Sent: Friday, August 12, 2022 5:14 PM > > > To: devel@edk2.groups.io > > > Cc: Liu, Zhiguang <zhiguang.liu@intel.com>; Dong, Eric > > > <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Kumar, Rahul R > > > <rahul.r.kumar@intel.com> > > > Subject: [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: > Add > > > host based unit test > > > > > > Add host based unit tests for the CpuPageTableLib services. > > > > > > Unit test focuses on PageTableMap function, containing two kinds of test > > > cases: manual test case and fuzzy test case. > > > Manual test case creates some corner case to test function > PageTableMap. > > > Fuzzy test case generates multiple random memory entries (with random > > > attribute) as the input of function PageTableMap to get the output > > > pagetable. Output pagetable will be validated and be parsed to get > output > > > memory entries, and then the input and output memory entries will be > > > compared to verify the functionality. > > > > > > The unit test is not perfect yet. There are options for fuzzy test, and > > > some of them control the test coverage, and some option are not ready. > > > Will enhance in the future. > > > > > > Cc: Eric Dong <eric.dong@intel.com> > > > Cc: Ray Ni <ray.ni@intel.com> > > > Cc: Rahul Kumar <rahul1.kumar@intel.com> > > > Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com> > > > --- > > > > > > diff --git > > > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > > h > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > > h > > > new file mode 100644 > > > index 0000000000..01d281f9c8 > > > --- /dev/null > > > +++ > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest. > > > h > > > @@ -0,0 +1,117 @@ > > > +/** @file > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#ifndef CPU_PAGE_TABLE_SUPPORT_H_ > > > +#define CPU_PAGE_TABLE_SUPPORT_H_ > > > + > > > +#include <stdio.h> > > > +#include <stdlib.h> > > > +#include <string.h> > > > +#include <stdarg.h> > > > +#include <stddef.h> > > > +#include <setjmp.h> > > > +#include <cmocka.h> > > > +#include <time.h> > > > + > > > +#include <Uefi.h> > > > +#include <Library/BaseLib.h> > > > +#include <Library/BaseMemoryLib.h> > > > +#include <Library/DebugLib.h> > > > +#include <Library/UnitTestLib.h> > > > +#include <Library/CpuPageTableLib.h> > > > +#include <Library/MemoryAllocationLib.h> > > > +#include <Library/UnitTestHostBaseLib.h> > > > +#include <Library/BaseCryptLib.h> > > > +#include "../CpuPageTable.h" > > > + > > > +#define UNIT_TEST_APP_NAME "Cpu Page Table Lib Unit Tests" > > > +#define UNIT_TEST_APP_VERSION "1.0" > > > + > > > +// > > > +// Fuzz Options > > > +// > > > + > > > +// > > > +// Only test one-one mapping case > > > +// > > > +#define ONLY_ONE_ONE_MAPPING 0x00000001 > > > + > > > +// > > > +// Change page table without using function PageTableMap, and use > the > > > modified page table as input > > > +// > > > +#define MANUAL_CHANGE_PAGE_TABLE 0x00000002 > > > + > > > +// > > > +// Use pre-generated random number array to generate random > number > > > +// > > > +#define USE_RANDOM_ARRAY 0x00000004 > > > + > > > +typedef struct { > > > + PAGING_MODE PagingMode; > > > + UINTN TestCount; > > > + UINTN TestRangeCount; > > > + UINTN FuzzOption; > > > +} CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT; > > > + > > > +/** > > > + Fuzzy Test > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseforFuzzyTest ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ); > > > + > > > +/** > > > + Init global data > > > + > > > + @param[in] MemorySpace Memory space > > > +**/ > > > +VOID > > > +InitGlobalData ( > > > + UINTN MemorySpace > > > + ); > > > + > > > +/** > > > + Check if the Page table is valid > > > + > > > + @param[in] PageTable The pointer to the page table. > > > + @param[in] PagingMode The paging mode. > > > + > > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > > +**/ > > > +UNIT_TEST_STATUS > > > +IsPageTableValid ( > > > + IN UINTN PageTable, > > > + IN PAGING_MODE PagingMode > > > + ); > > > + > > > +/** > > > + Get max physical adrress supported by specific page mode > > > + > > > + @param[in] Mode The paging mode. > > > + > > > + @retval max address. > > > +**/ > > > +UINT64 > > > +GetMaxAddress ( > > > + IN PAGING_MODE Mode > > > + ); > > > + > > > +#endif > > > diff --git > > > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.c > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.c > > > new file mode 100644 > > > index 0000000000..a0409bc318 > > > --- /dev/null > > > +++ > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.c > > > @@ -0,0 +1,794 @@ > > > +/** @file > > > + Unit tests of the CpuPageTableLib instance of the CpuPageTableLib > class > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#include "CpuPageTableLibUnitTest.h" > > > + > > > +// ----------------------------------------------------------------------- > PageMode-- > > > TestCount-TestRangeCount---FuzzOptions > > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > mTestContextPaging4Level = { Paging4Level, 100, 20, > > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > mTestContextPaging4Level1GB = { Paging4Level1GB, 100, 20, > > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > mTestContextPaging5Level = { Paging5Level, 100, 20, > > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > > +static CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > mTestContextPaging5Level1GB = { Paging5Level1GB, 100, 20, > > > ONLY_ONE_ONE_MAPPING|USE_RANDOM_ARRAY }; > > > + > > > +/** > > > + Check if the input parameters are not supported. > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseForParameter ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + UINTN Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = 0; > > > + PagingMode = Paging5Level1GB; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + > > > + // > > > + // If the input linear address is not 4K align, it should return invalid > > > parameter > > > + // > > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, > &Buffer, > > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > > > RETURN_INVALID_PARAMETER); > > > + > > > + // > > > + // If the input PageTableBufferSize is not 4K align, it should return > invalid > > > parameter > > > + // > > > + PageTableBufferSize = 10; > > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, > &Buffer, > > > &PageTableBufferSize, 0, SIZE_4KB, &MapAttribute, &MapMask), > > > RETURN_INVALID_PARAMETER); > > > + > > > + // > > > + // If the input PagingMode is Paging32bit, it should return invalid > > > parameter > > > + // > > > + PageTableBufferSize = 0; > > > + PagingMode = Paging32bit; > > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, > &Buffer, > > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, &MapMask), > > > RETURN_UNSUPPORTED); > > > + > > > + // > > > + // If the input MapMask is NULL, it should return invalid parameter > > > + // > > > + PagingMode = Paging5Level1GB; > > > + UT_ASSERT_EQUAL (PageTableMap (&PageTable, PagingMode, > &Buffer, > > > &PageTableBufferSize, 1, SIZE_4KB, &MapAttribute, NULL), > > > RETURN_INVALID_PARAMETER); > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check the case that modifying page table doesn't need extra buffe > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseWhichNoNeedExtraSize ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + UNIT_TEST_STATUS TestStatus; > > > + > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = 0; > > > + PagingMode = Paging4Level1GB; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Bits.Present = 1; > > > + MapAttribute.Bits.Nx = 1; > > > + MapMask.Bits.Present = 1; > > > + MapMask.Uint64 = MAX_UINT64; > > > + > > > + // > > > + // Create page table to cover [0, 10M], it should have 5 PTE > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, 0, (UINT64)SIZE_2MB * 5, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + // > > > + // call library to cover [0, 4K], because the page table is already cover [0, > > > 10M], and no attribute change, > > > + // We assume the fucntion doesn't need to change page table, return > > > success and output BufferSize is 0 > > > + // > > > + Buffer = NULL; > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, > &MapMask); > > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + // > > > + // Same range and same attribute, only clear one mask attribute bit > > > + // We assume the fucntion doesn't need to change page table, return > > > success and output BufferSize is 0 > > > + // > > > + MapMask.Bits.Nx = 0; > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, 0, (UINT64)SIZE_4KB, &MapAttribute, > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + // > > > + // call library to cover [2M, 4M], while the page table is already cover [0, > > > 10M], > > > + // only change one attribute bit, we assume the page table change be > > > modified even if the > > > + // input Buffer is NULL, and BufferSize is 0 > > > + // > > > + MapAttribute.Bits.Accessed = 1; > > > + MapMask.Bits.Accessed = 1; > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, (UINT64)SIZE_2MB, (UINT64)SIZE_2MB, > > > &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (PageTableBufferSize, 0); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Test Case that check the case to map [0, 1G] to [8K, 1G+8K] > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCase1Gmapto4K ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + UNIT_TEST_STATUS TestStatus; > > > + > > > + // > > > + // Create Page table to map [0,1G] to [8K, 1G+8K] > > > + // > > > + PagingMode = Paging4Level1GB; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Uint64 = (UINT64)SIZE_4KB * 2; > > > + MapMask.Uint64 = (UINT64)SIZE_4KB * 2; > > > + MapAttribute.Bits.Present = 1; > > > + MapMask.Bits.Present = 1; > > > + MapMask.Uint64 = MAX_UINT64; > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + > > > + // > > > + // Page table should be valid. (All reserved bits are zero) > > > + // > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check if the parent entry has different R/W attribute > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseManualChangeReadWrite ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + IA32_MAP_ENTRY *Map; > > > + UINTN MapCount; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + VOID *BackupBuffer; > > > + UINTN BackupPageTableBufferSize; > > > + > > > + PagingMode = Paging4Level; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = MAX_UINT64; > > > + MapAttribute.Bits.Present = 1; > > > + MapAttribute.Bits.ReadWrite = 1; > > > + > > > + // > > > + // Create Page table to cover [0,2G], with ReadWrite = 1 > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + BackupPageTableBufferSize = PageTableBufferSize; > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES > > > (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, 0, SIZE_2GB, &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + IsPageTableValid (PageTable, PagingMode); > > > + > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + IsPageTableValid (PageTable, PagingMode); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Manually change ReadWrite to 0 for non-leaf entry, which covers > [0,2G] > > > + // > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Copy the page entry structure memory for future compare > > > + // > > > + BackupBuffer = AllocateCopyPool (BackupPageTableBufferSize, Buffer); > > > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > > > BackupPageTableBufferSize); > > > + > > > + // > > > + // Call library to change ReadWrite to 0 for [0,2M] > > > + // > > > + MapAttribute.Bits.ReadWrite = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + IsPageTableValid (PageTable, PagingMode); > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + // > > > + // There should be 1 range [0, 2G] with ReadWrite = 0 > > > + // > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // The latest PageTableMap call should change nothing. > > > + // The memory should be identical before and after the funtion is > called. > > > + // > > > + UT_ASSERT_MEM_EQUAL (Buffer, BackupBuffer, > > > BackupPageTableBufferSize); > > > + > > > + // > > > + // Call library to change ReadWrite to 1 for [0, 2M] > > > + // > > > + MapAttribute.Bits.ReadWrite = 1; > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, 0, SIZE_2MB, &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + IsPageTableValid (PageTable, PagingMode); > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + // > > > + // There should be 2 range [0, 2M] with ReadWrite = 1 and [2M, 2G] > with > > > ReadWrite = 0 > > > + // > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 2); > > > + > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2MB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2GB - SIZE_2MB); > > > + ExpectedMapAttribute.Uint64 = SIZE_2MB; > > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > > + ExpectedMapAttribute.Bits.Present = 1; > > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check if the needed size is expected > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseManualSizeNotMatch ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + IA32_MAP_ENTRY *Map; > > > + UINTN MapCount; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + > > > + PagingMode = Paging4Level; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = MAX_UINT64; > > > + MapAttribute.Bits.Present = 1; > > > + MapAttribute.Bits.ReadWrite = 1; > > > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> > 12; > > > + // > > > + // Create Page table to cover [2M-4K, 4M], with ReadWrite = 1 > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > > > &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB + SIZE_2MB, > > > &MapAttribute, &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + IsPageTableValid (PageTable, PagingMode); > > > + > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + IsPageTableValid (PageTable, PagingMode); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB + SIZE_2MB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Manually change ReadWrite to 0 for 3 level non-leaf entry, which > covers > > > [0,2M] > > > + // Then the map is: > > > + // [2M-4K,2M], R/W = 0 > > > + // [2M ,4M], R/W = 1 > > > + // > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > // Get 4 level entry > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > > > >Pnle.Bits.PageTableBaseAddress << 12); // Get 3 level entry > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)(PagingEntry- > > > >Pnle.Bits.PageTableBaseAddress << 12); // Get 2 level entry > > > + PagingEntry->Uint64 = PagingEntry->Uint64 & (~(UINT64)0x2); > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount)); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 2); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, SIZE_2MB - SIZE_4KB); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_4KB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + ExpectedMapAttribute.Bits.ReadWrite = 0; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_2MB); > > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_2MB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + ExpectedMapAttribute.Bits.ReadWrite = 1; > > > + ExpectedMapAttribute.Bits.PageTableBaseAddress = SIZE_2MB >> 12; > > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Set Page table [2M-4K, 2M+4K]'s ReadWrite = 1, [2M,2M+4K]'s > > > ReadWrite is already 1 > > > + // Just need to set [2M-4K,2M], won't need extra size, so the status > should > > > be success > > > + // > > > + MapAttribute.Bits.Present = 1; > > > + MapAttribute.Bits.ReadWrite = 1; > > > + PageTableBufferSize = 0; > > > + MapAttribute.Bits.PageTableBaseAddress = (SIZE_2MB - SIZE_4KB) >> > 12; > > > + Status = PageTableMap (&PageTable, PagingMode, > Buffer, > > > &PageTableBufferSize, SIZE_2MB - SIZE_4KB, SIZE_4KB * 2, > &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check that won't merge entries > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseManualNotMergeEntry ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + UNIT_TEST_STATUS TestStatus; > > > + > > > + PagingMode = Paging4Level1GB; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = MAX_UINT64; > > > + MapAttribute.Bits.Present = 1; > > > + MapMask.Bits.Present = 1; > > > + > > > + // > > > + // Create Page table to cover [0,4M], and [4M, 1G] is not present > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, > &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB * 2, > &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + // > > > + // Let Page table to cover [0,1G], we assume it won't use a big 1G entry > to > > > cover whole range > > > + // It looks like the chioce is not bad, but sometime, we need to keep > some > > > small entry > > > + // > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + MapAttribute.Bits.Accessed = 1; > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_2MB, &MapAttribute, > > > &MapMask); > > > + // > > > + // If it didn't use a big 1G entry to cover whole range, only change > [0,2M] > > > for some attribute won't need extra memory > > > + // > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check if the parent entry has different Nx attribute > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseManualChangeNx ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UINTN PageTable; > > > + PAGING_MODE PagingMode; > > > + VOID *Buffer; > > > + UINTN PageTableBufferSize; > > > + IA32_MAP_ATTRIBUTE MapAttribute; > > > + IA32_MAP_ATTRIBUTE ExpectedMapAttribute; > > > + IA32_MAP_ATTRIBUTE MapMask; > > > + RETURN_STATUS Status; > > > + IA32_MAP_ENTRY *Map; > > > + UINTN MapCount; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + UNIT_TEST_STATUS TestStatus; > > > + > > > + PagingMode = Paging4Level1GB; > > > + PageTableBufferSize = 0; > > > + PageTable = 0; > > > + Buffer = NULL; > > > + MapAttribute.Uint64 = 0; > > > + MapMask.Uint64 = MAX_UINT64; > > > + MapAttribute.Bits.Present = 1; > > > + MapAttribute.Bits.Nx = 0; > > > + > > > + // > > > + // Create Page table to cover [0,2G], with Nx = 0 > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Buffer = AllocatePages (EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + Status = PageTableMap (&PageTable, PagingMode, Buffer, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB * 2, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > > (IA32_MAP_ENTRY))); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Manually change Nx to 1 for non-leaf entry, which covers [0,2G] > > > + // > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > + PagingEntry->Uint64 = PagingEntry->Uint64 | BIT63; > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > > (IA32_MAP_ENTRY))); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + UT_ASSERT_EQUAL (MapCount, 1); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_2GB); > > > + ExpectedMapAttribute.Bits.Nx = 1; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + > > > + // > > > + // Call library to change Nx to 0 for [0,1G] > > > + // > > > + Status = PageTableMap (&PageTable, PagingMode, NULL, > > > &PageTableBufferSize, (UINT64)0, (UINT64)SIZE_1GB, &MapAttribute, > > > &MapMask); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + MapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount* sizeof > > > (IA32_MAP_ENTRY))); > > > + Status = PageTableParse (PageTable, PagingMode, Map, &MapCount); > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + > > > + // > > > + // There should be two ranges [0, 1G] with Nx = 0 and [1G, 2G] with Nx > = 1 > > > + // > > > + UT_ASSERT_EQUAL (MapCount, 2); > > > + UT_ASSERT_EQUAL (Map[0].LinearAddress, 0); > > > + UT_ASSERT_EQUAL (Map[0].Length, SIZE_1GB); > > > + ExpectedMapAttribute.Uint64 = MapAttribute.Uint64; > > > + UT_ASSERT_EQUAL (Map[0].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + UT_ASSERT_EQUAL (Map[1].LinearAddress, SIZE_1GB); > > > + UT_ASSERT_EQUAL (Map[1].Length, SIZE_1GB); > > > + ExpectedMapAttribute.Uint64 = SIZE_1GB; > > > + ExpectedMapAttribute.Bits.Present = 1; > > > + ExpectedMapAttribute.Bits.Nx = 1; > > > + UT_ASSERT_EQUAL (Map[1].Attribute.Uint64, > > > ExpectedMapAttribute.Uint64); > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Initialize the unit test framework, suite, and unit tests for the > > > + sample unit tests and run the unit tests. > > > + > > > + @retval EFI_SUCCESS All test cases were dispatched. > > > + @retval EFI_OUT_OF_RESOURCES There are not enough resources > > > available to > > > + initialize the unit tests. > > > +**/ > > > +EFI_STATUS > > > +EFIAPI > > > +UefiTestMain ( > > > + VOID > > > + ) > > > +{ > > > + EFI_STATUS Status; > > > + UNIT_TEST_FRAMEWORK_HANDLE Framework; > > > + UNIT_TEST_SUITE_HANDLE ManualTestCase; > > > + UNIT_TEST_SUITE_HANDLE FuzzyTestCase; > > > + > > > + Framework = NULL; > > > + > > > + DEBUG ((DEBUG_INFO, "%a v%a\n", UNIT_TEST_APP_NAME, > > > UNIT_TEST_APP_VERSION)); > > > + > > > + // > > > + // Start setting up the test framework for running the tests. > > > + // > > > + Status = InitUnitTestFramework (&Framework, > UNIT_TEST_APP_NAME, > > > gEfiCallerBaseName, UNIT_TEST_APP_VERSION); > > > + if (EFI_ERROR (Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed in InitUnitTestFramework. Status > > > = %r\n", Status)); > > > + goto EXIT; > > > + } > > > + > > > + // > > > + // Populate the Manual Test Cases. > > > + // > > > + Status = CreateUnitTestSuite (&ManualTestCase, Framework, "Manual > > > Test Cases", "CpuPageTableLib.Manual", NULL, NULL); > > > + if (EFI_ERROR (Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Manual > Test > > > Cases\n")); > > > + Status = EFI_OUT_OF_RESOURCES; > > > + goto EXIT; > > > + } > > > + > > > + AddTestCase (ManualTestCase, "Check if the input parameters are not > > > supported.", "Manual Test Case1", TestCaseForParameter, NULL, NULL, > > > NULL); > > > + AddTestCase (ManualTestCase, "Check the case that modifying page > table > > > doesn't need extra buffer", "Manual Test Case2", > > > TestCaseWhichNoNeedExtraSize, NULL, NULL, NULL); > > > + AddTestCase (ManualTestCase, "Check the case to map [0, 1G] to [8K, > > > 1G+8K]", "Manual Test Case3", TestCase1Gmapto4K, NULL, NULL, NULL); > > > + AddTestCase (ManualTestCase, "Check won't merge entries", "Manual > > > Test Case4", TestCaseManualNotMergeEntry, NULL, NULL, NULL); > > > + AddTestCase (ManualTestCase, "Check if the parent entry has > different > > > ReadWrite attribute", "Manual Test Case5", > > > TestCaseManualChangeReadWrite, NULL, NULL, NULL); > > > + AddTestCase (ManualTestCase, "Check if the parent entry has > different Nx > > > attribute", "Manual Test Case6", TestCaseManualChangeNx, NULL, NULL, > > > NULL); > > > + AddTestCase (ManualTestCase, "Check if the needed size is expected", > > > "Manual Test Case7", TestCaseManualSizeNotMatch, NULL, NULL, NULL); > > > + > > > + // > > > + // Populate the Fuzzy Test Cases. > > > + // > > > + Status = CreateUnitTestSuite (&FuzzyTestCase, Framework, "Fuzzy > Test > > > Cases", "CpuPageTableLib.Fuzzy", NULL, NULL); > > > + if (EFI_ERROR (Status)) { > > > + DEBUG ((DEBUG_ERROR, "Failed in CreateUnitTestSuite for Fuzzy Test > > > Cases\n")); > > > + Status = EFI_OUT_OF_RESOURCES; > > > + goto EXIT; > > > + } > > > + > > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level", "Fuzzy > Test > > > Case1", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging4Level); > > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging4Level1G", "Fuzzy > Test > > > Case2", TestCaseforFuzzyTest, NULL, NULL, > > > &mTestContextPaging4Level1GB); > > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level", "Fuzzy > Test > > > Case3", TestCaseforFuzzyTest, NULL, NULL, &mTestContextPaging5Level); > > > + AddTestCase (FuzzyTestCase, "Fuzzy Test for Paging5Level1G", "Fuzzy > Test > > > Case4", TestCaseforFuzzyTest, NULL, NULL, > > > &mTestContextPaging5Level1GB); > > > + > > > + // > > > + // Execute the tests. > > > + // > > > + Status = RunAllTestSuites (Framework); > > > + > > > +EXIT: > > > + if (Framework) { > > > + FreeUnitTestFramework (Framework); > > > + } > > > + > > > + return Status; > > > +} > > > + > > > +/** > > > + Standard POSIX C entry point for host based unit test execution. > > > + > > > + @param Argc Number of arguments. > > > + @param Argv Array of arguments. > > > + > > > + @return Test application exit code. > > > +**/ > > > +INT32 > > > +main ( > > > + INT32 Argc, > > > + CHAR8 *Argv[] > > > + ) > > > +{ > > > + InitGlobalData (52); > > > + return UefiTestMain (); > > > +} > > > diff --git > > > > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.inf > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.inf > > > new file mode 100644 > > > index 0000000000..2854df46d3 > > > --- /dev/null > > > +++ > > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTest > > > Host.inf > > > @@ -0,0 +1,42 @@ > > > +## @file > > > +# Unit tests of the CpuPageTableLib instance of the CpuPageTableLib > class > > > +# > > > +# Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > +# SPDX-License-Identifier: BSD-2-Clause-Patent > > > +## > > > + > > > +[Defines] > > > + INF_VERSION = 0x00010006 > > > + BASE_NAME = CpuPageTableLibUnitTestHost > > > + FILE_GUID = D8DC32C2-7272-43A8-B145-1723BED8E119 > > > + MODULE_TYPE = HOST_APPLICATION > > > + VERSION_STRING = 1.0 > > > + > > > +# > > > +# The following information is for reference only and not required by > the > > > build tools. > > > +# > > > +# VALID_ARCHITECTURES = IA32 X64 > > > +# > > > + > > > +[Sources] > > > + CpuPageTableLibUnitTestHost.c > > > + FuzzyTest.c > > > + TestHelper.c > > > + RandomNumber.c > > > + FuzzyTest.h > > > + CpuPageTableLibUnitTest.h > > > + > > > +[Packages] > > > + MdePkg/MdePkg.dec > > > + UefiCpuPkg/UefiCpuPkg.dec > > > + UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec > > > + CryptoPkg/CryptoPkg.dec > > > + > > > +[LibraryClasses] > > > + BaseLib > > > + BaseMemoryLib > > > + DebugLib > > > + CpuPageTableLib > > > + UnitTestLib > > > + MemoryAllocationLib > > > + BaseCryptLib > > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > > new file mode 100644 > > > index 0000000000..05ab66d406 > > > --- /dev/null > > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.c > > > @@ -0,0 +1,926 @@ > > > +/** @file > > > + Fuzzy test case for Unit tests of the CpuPageTableLib instance of the > > > CpuPageTableLib class > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#include "CpuPageTableLibUnitTest.h" > > > +#include "FuzzyTest.h" > > > + > > > +UINTN RandomNumber = 0; > > > +extern IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > > > +extern IA32_PAGING_ENTRY mValidMaskLeaf[6]; > > > +extern IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > > > +UINTN mFuzzOption; > > > +IA32_MAP_ATTRIBUTE mSupportedBit; > > > +extern UINTN mNumberCount; > > > +extern UINT8 mNumbers[]; > > > +UINTN mNumberIndex; > > > +UINT64 AlignedTable[] = { > > > + ~((UINT64)SIZE_4KB - 1), > > > + ~((UINT64)SIZE_2MB - 1), > > > + ~((UINT64)SIZE_1GB - 1) > > > +}; > > > + > > > +/** > > > + Generates a pseudorandom byte stream of the specified size. > > > + > > > + Return FALSE to indicate this interface is not supported. > > > + > > > + @param[out] Output Pointer to buffer to receive random value. > > > + @param[in] Size Size of random bytes to generate. > > > + > > > + @retval TRUE Always return TRUE > > > + > > > +**/ > > > +BOOLEAN > > > +EFIAPI > > > +RandomBytesUsingArray ( > > > + OUT UINT8 *Output, > > > + IN UINTN Size > > > + ) > > > +{ > > > + UINTN Index; > > > + > > > + for (Index = 0; Index < Size; Index++) { > > > + if (mNumberIndex >= mNumberCount) { > > > + mNumberIndex = 0; > > > + } > > > + > > > + Output[Index] = mNumbers[mNumberIndex]; > > > + mNumberIndex++; > > > + } > > > + > > > + return TRUE; > > > +} > > > + > > > +/** > > > + Generates a pseudorandom byte stream of the specified size. > > > + > > > + Return FALSE to indicate this interface is not supported. > > > + > > > + @param[out] Output Pointer to buffer to receive random value. > > > + @param[in] Size Size of random bytes to generate. > > > + > > > + @retval TRUE Pseudorandom byte stream generated successfully. > > > + @retval FALSE Pseudorandom number generator fails > > > +**/ > > > +BOOLEAN > > > +EFIAPI > > > +LocalRandomBytes ( > > > + OUT UINT8 *Output, > > > + IN UINTN Size > > > + ) > > > +{ > > > + if (mFuzzOption & USE_RANDOM_ARRAY) { > > > + return RandomBytesUsingArray (Output, Size); > > > + } else { > > > + return RandomBytes (Output, Size); > > > + } > > > +} > > > + > > > +/** > > > + Return a random boolean. > > > + > > > + @return boolean > > > +**/ > > > +BOOLEAN > > > +RandomBoolean ( > > > + VOID > > > + ) > > > +{ > > > + BOOLEAN Value; > > > + > > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (BOOLEAN)); > > > + return Value%2; > > > +} > > > + > > > +/** > > > + Return a 32bit random number. > > > + > > > + @param Start Start of the random number range. > > > + @param Limit Limit of the random number range, and return value can > be > > > Limit. > > > + @return 32bit random number > > > +**/ > > > +UINT32 > > > +Random32 ( > > > + UINT32 Start, > > > + UINT32 Limit > > > + ) > > > +{ > > > + UINT64 Value; > > > + > > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > > > + return (UINT32)(Value % (Limit - Start + 1)) + Start; > > > +} > > > + > > > +/** > > > + Return a 64bit random number. > > > + > > > + @param Start Start of the random number range. > > > + @param Limit Limit of the random number range, and return value can > be > > > Limit. > > > + @return 64bit random number > > > +**/ > > > +UINT64 > > > +Random64 ( > > > + UINT64 Start, > > > + UINT64 Limit > > > + ) > > > +{ > > > + UINT64 Value; > > > + > > > + LocalRandomBytes ((UINT8 *)&Value, sizeof (UINT64)); > > > + if (Limit - Start == MAX_UINT64) { > > > + return (UINT64)(Value); > > > + } > > > + > > > + return (UINT64)(Value % (Limit - Start + 1)) + Start; > > > +} > > > + > > > +/** > > > + Check if the Page table entry is valid > > > + > > > + @param[in] PagingEntry The entry in page table to verify > > > + @param[in] Level the level of PagingEntry. > > > + @param[in] MaxLeafLevel Max leaf entry level. > > > + @param[in] LinearAddress The linear address verified. > > > + > > > + @retval Leaf entry. > > > +**/ > > > +UNIT_TEST_STATUS > > > +ValidateAndRandomeModifyPageTablePageTableEntry ( > > > + IN IA32_PAGING_ENTRY *PagingEntry, > > > + IN UINTN Level, > > > + IN UINTN MaxLeafLevel, > > > + IN UINT64 Address > > > + ) > > > +{ > > > + UINT64 Index; > > > + UINT64 TempPhysicalBase; > > > + IA32_PAGING_ENTRY *ChildPageEntry; > > > + UNIT_TEST_STATUS Status; > > > + > > > + if (PagingEntry->Pce.Present == 0) { > > > + return UNIT_TEST_PASSED; > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > > > mValidMaskLeafFlag[Level].Uint64) { > > > + // > > > + // It is a Leaf > > > + // > > > + if (Level > MaxLeafLevel) { > > > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != > PagingEntry- > > > >Uint64) { > > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > > + } > > > + > > > + if ((RandomNumber < 100) && RandomBoolean ()) { > > > + RandomNumber++; > > > + if (Level == 1) { > > > + TempPhysicalBase = PagingEntry- > >Pte4K.Bits.PageTableBaseAddress; > > > + } else { > > > + TempPhysicalBase = PagingEntry->PleB.Bits.PageTableBaseAddress; > > > + } > > > + > > > + PagingEntry->Uint64 = (Random64 (0, MAX_UINT64) & > > > mValidMaskLeaf[Level].Uint64) | mValidMaskLeafFlag[Level].Uint64; > > > + PagingEntry->Pte4K.Bits.Present = 1; > > > + if (Level == 1) { > > > + PagingEntry->Pte4K.Bits.PageTableBaseAddress = > TempPhysicalBase; > > > + } else { > > > + PagingEntry->PleB.Bits.PageTableBaseAddress = TempPhysicalBase; > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != > > > PagingEntry->Uint64) { > > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > > + } > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > + } > > > + > > > + // > > > + // Not a leaf > > > + // > > > + UT_ASSERT_NOT_EQUAL (Level, 1); > > > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > > > PagingEntry->Uint64) { > > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, > which > > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > > > + } > > > + > > > + if ((RandomNumber < 100) && RandomBoolean ()) { > > > + RandomNumber++; > > > + TempPhysicalBase = PagingEntry->Pnle.Bits.PageTableBaseAddress; > > > + > > > + PagingEntry->Uint64 = Random64 (0, MAX_UINT64) & > > > mValidMaskNoLeaf[Level].Uint64; > > > + PagingEntry->Pnle.Bits.Present = 1; > > > + PagingEntry->Pnle.Bits.PageTableBaseAddress = TempPhysicalBase; > > > + ASSERT ((PagingEntry->Uint64 & > mValidMaskLeafFlag[Level].Uint64) != > > > mValidMaskLeafFlag[Level].Uint64); > > > + } > > > + > > > + ChildPageEntry = (IA32_PAGING_ENTRY *)(UINTN)((PagingEntry- > > > >Pnle.Bits.PageTableBaseAddress) << 12); > > > + for (Index = 0; Index < 512; Index++) { > > > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > > > (&ChildPageEntry[Index], Level-1, MaxLeafLevel, Address + > > > (Index<<(9*(Level-1) + 3))); > > > + if (Status != UNIT_TEST_PASSED) { > > > + return Status; > > > + } > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check if the Page table is valid > > > + > > > + @param[in] PageTable The pointer to the page table. > > > + @param[in] PagingMode The paging mode. > > > + > > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > > +**/ > > > +UNIT_TEST_STATUS > > > +ValidateAndRandomeModifyPageTable ( > > > + IN UINTN PageTable, > > > + IN PAGING_MODE PagingMode > > > + ) > > > +{ > > > + UINTN MaxLevel; > > > + UINTN MaxLeafLevel; > > > + UINT64 Index; > > > + UNIT_TEST_STATUS Status; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + > > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > > (PagingMode >= PagingModeMax)) { > > > + // > > > + // 32bit paging is never supported. > > > + // PAE paging will be supported later. > > > + // > > > + return UNIT_TEST_ERROR_TEST_FAILED; > > > + } > > > + > > > + MaxLeafLevel = (UINT8)PagingMode; > > > + MaxLevel = (UINT8)(PagingMode >> 8); > > > + > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > + for (Index = 0; Index < 512; Index++) { > > > + Status = ValidateAndRandomeModifyPageTablePageTableEntry > > > (&PagingEntry[Index], MaxLevel, MaxLeafLevel, Index << (9 * MaxLevel > + 3)); > > > + if (Status != UNIT_TEST_PASSED) { > > > + return Status; > > > + } > > > + } > > > + > > > + return Status; > > > +} > > > + > > > +/** > > > + Generate single random map entry. > > > + The map entry can be the input of function PageTableMap > > > + the LinearAddress and length is aligned to aligned table. > > > + > > > + @param MaxAddress Max Address. > > > + @param MapEntrys Output MapEntrys contains all parameter as input > of > > > function PageTableMap > > > +**/ > > > +VOID > > > +GenerateSingleRandomMapEntry ( > > > + IN UINT64 MaxAddress, > > > + IN OUT MAP_ENTRYS *MapEntrys > > > + ) > > > +{ > > > + UINTN MapsIndex; > > > + UINT64 FormerLinearAddress; > > > + UINT64 FormerLinearAddressBottom; > > > + UINT64 FormerLinearAddressTop; > > > + > > > + MapsIndex = MapEntrys->Count; > > > + > > > + ASSERT (MapsIndex < MapEntrys->MaxCount); > > > + // > > > + // use AlignedTable to avoid that a random number can be very hard to > be > > > 1G or 2M aligned > > > + // > > > + if ((MapsIndex != 0) && (RandomBoolean ())) { > > > + FormerLinearAddress = MapEntrys->Maps[Random32 (0, > > > (UINT32)MapsIndex-1)].LinearAddress; > > > + if (FormerLinearAddress < 2 * (UINT64)SIZE_1GB) { > > > + FormerLinearAddressBottom = 0; > > > + } else { > > > + FormerLinearAddressBottom = FormerLinearAddress - 2 * > > > (UINT64)SIZE_1GB; > > > + } > > > + > > > + if (FormerLinearAddress + 2 * (UINT64)SIZE_1GB > MaxAddress) { > > > + FormerLinearAddressTop = MaxAddress; > > > + } else { > > > + FormerLinearAddressTop = FormerLinearAddress + 2 * > > > (UINT64)SIZE_1GB; > > > + } > > > + > > > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 > > > (FormerLinearAddressBottom, FormerLinearAddressTop) & > > > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > > > + } else { > > > + MapEntrys->Maps[MapsIndex].LinearAddress = Random64 (0, > > > MaxAddress) & AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) - > 1)]; > > > + } > > > + > > > + // > > > + // To have better performance, limit the size less than 10G > > > + // > > > + MapEntrys->Maps[MapsIndex].Length = Random64 (0, MIN > (MaxAddress > > > - MapEntrys->Maps[MapsIndex].LinearAddress, 10 * (UINT64)SIZE_1GB)) > & > > > AlignedTable[Random32 (0, ARRAY_SIZE (AlignedTable) -1)]; > > > + > > > + if ((MapsIndex != 0) && (RandomBoolean ())) { > > > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = MapEntrys- > > > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Attribute.Uint64; > > > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = MapEntrys- > > > >Maps[Random32 (0, (UINT32)MapsIndex-1)].Mask.Uint64; > > > + } else { > > > + MapEntrys->Maps[MapsIndex].Attribute.Uint64 = Random64 (0, > > > MAX_UINT64) & mSupportedBit.Uint64; > > > + MapEntrys->Maps[MapsIndex].Mask.Uint64 = Random64 (0, > > > MAX_UINT64) & mSupportedBit.Uint64; > > > + if (MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey != 0) { > > > + MapEntrys->Maps[MapsIndex].Mask.Bits.ProtectionKey = 0xF; > > > + } > > > + } > > > + > > > + if (mFuzzOption & ONLY_ONE_ONE_MAPPING) { > > > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress > = > > > MapEntrys->Maps[MapsIndex].LinearAddress >> 12; > > > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = > > > 0xFFFFFFFFFF; > > > + } else { > > > + // > > > + // Todo: If the mask bit for base address is zero, when dump the > > > pagetable, every entry mapping to physical address zeor. > > > + // This means the map count will be a large number, and impossible > to > > > finish in proper time. > > > + // Need to avoid such case when remove the fuzzy option > > > ONLY_ONE_ONE_MAPPING > > > + // > > > + MapEntrys->Maps[MapsIndex].Attribute.Bits.PageTableBaseAddress > = > > > (Random64 (0, (((UINT64)1)<<52) - 1) & AlignedTable[Random32 (0, > > > ARRAY_SIZE (AlignedTable) -1)])>> 12; > > > + if (RandomBoolean ()) { > > > + MapEntrys->Maps[MapsIndex].Mask.Bits.PageTableBaseAddress = 0; > > > + } > > > + } > > > + > > > + MapEntrys->Count += 1; > > > +} > > > + > > > +/** > > > + Compare the attribute for one point. > > > + MapEntrys records every memory ranges that is used as input > > > + Map and MapCount are gotten from Page table > > > + Compare if this point have same attribute. > > > + > > > + @param[in] Address Address of one Point. > > > + @param[in] MapEntrys Record every memory ranges that is used as > > > input > > > + @param[in] Map Pointer to an array that describes multiple linear > > > address ranges. > > > + @param[in] MapCount Pointer to a UINTN that hold the number of > > > entries in the Map. > > > + @param[in] InitMap Pointer to an array that describes init map > entries. > > > + @param[in] InitMapCount Pointer to a UINTN that hold the number of > init > > > map entries. > > > + > > > + @retval TRUE At least one byte of data is available to be read > > > + @retval FALSE No data is available to be read > > > +**/ > > > +BOOLEAN > > > +CompareEntrysforOnePoint ( > > > + IN UINT64 Address, > > > + IN MAP_ENTRYS *MapEntrys, > > > + IN IA32_MAP_ENTRY *Map, > > > + IN UINTN MapCount, > > > + IN IA32_MAP_ENTRY *InitMap, > > > + IN UINTN InitMapCount > > > + ) > > > +{ > > > + UINTN Index; > > > + IA32_MAP_ATTRIBUTE AttributeInInitMap; > > > + IA32_MAP_ATTRIBUTE AttributeInMap; > > > + IA32_MAP_ATTRIBUTE AttributeInMapEntrys; > > > + IA32_MAP_ATTRIBUTE MaskInMapEntrys; > > > + > > > + AttributeInMap.Uint64 = 0; > > > + AttributeInMapEntrys.Uint64 = 0; > > > + AttributeInInitMap.Uint64 = 0; > > > + MaskInMapEntrys.Uint64 = 0; > > > + // > > > + // Assume every entry in maps does not overlap with each other > > > + // > > > + for (Index = 0; Index < MapCount; Index++) { > > > + if ((Address >= Map[Index].LinearAddress) && (Address < > > > (Map[Index].LinearAddress + Map[Index].Length))) { > > > + AttributeInMap.Uint64 = (Map[Index].Attribute.Uint64 & > > > mSupportedBit.Uint64); > > > + AttributeInMap.Bits.PageTableBaseAddress = ((Address - > > > Map[Index].LinearAddress) >> 12) + > > > Map[Index].Attribute.Bits.PageTableBaseAddress; > > > + break; > > > + } > > > + } > > > + > > > + // > > > + // Assume every entry in maps does not overlap with each other > > > + // > > > + for (Index = 0; Index < InitMapCount; Index++) { > > > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > > > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > > > + AttributeInInitMap.Uint64 = > (InitMap[Index].Attribute.Uint64 > > > & mSupportedBit.Uint64); > > > + AttributeInInitMap.Bits.PageTableBaseAddress = ((Address - > > > InitMap[Index].LinearAddress) >> 12) + > > > InitMap[Index].Attribute.Bits.PageTableBaseAddress; > > > + break; > > > + } > > > + } > > > + > > > + AttributeInMapEntrys.Uint64 = AttributeInInitMap.Uint64; > > > + > > > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; > Index++) { > > > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && (Address > < > > > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > > >Maps[Index].Length))) { > > > + if (AttributeInMapEntrys.Bits.Present == 0) { > > > + AttributeInMapEntrys.Uint64 = 0; > > > + MaskInMapEntrys.Uint64 = 0; > > > + } > > > + > > > + MaskInMapEntrys.Uint64 |= MapEntrys- > >Maps[Index].Mask.Uint64; > > > + AttributeInMapEntrys.Uint64 &= (~MapEntrys- > > > >Maps[Index].Mask.Uint64); > > > + AttributeInMapEntrys.Uint64 |= (MapEntrys- > > > >Maps[Index].Attribute.Uint64 & MapEntrys- > >Maps[Index].Mask.Uint64); > > > + if (MapEntrys->Maps[Index].Mask.Bits.PageTableBaseAddress != 0) { > > > + AttributeInMapEntrys.Bits.PageTableBaseAddress = ((Address - > > > MapEntrys->Maps[Index].LinearAddress) >> 12) + MapEntrys- > > > >Maps[Index].Attribute.Bits.PageTableBaseAddress; > > > + } > > > + } > > > + } > > > + > > > + if (AttributeInMap.Bits.Present == 0) { > > > + if (AttributeInMapEntrys.Bits.Present == 0) { > > > + return TRUE; > > > + } > > > + } > > > + > > > + if ((AttributeInMap.Uint64 & MaskInMapEntrys.Uint64) != > > > (AttributeInMapEntrys.Uint64 & MaskInMapEntrys.Uint64)) { > > > + DEBUG ((DEBUG_INFO, "======detailed information > begin=====\n")); > > > + DEBUG ((DEBUG_INFO, "\nError: Detect different attribute on a point > > > with linear address: 0x%lx\n", Address)); > > > + DEBUG ((DEBUG_INFO, "By parsing page table, the point has Attribute > > > 0x%lx, and map to physical address 0x%lx\n", > > > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMap) & > > > MaskInMapEntrys.Uint64, AttributeInMap.Bits.PageTableBaseAddress)); > > > + DEBUG ((DEBUG_INFO, "While according to inputs, the point should > > > Attribute 0x%lx, and should map to physical address 0x%lx\n", > > > IA32_MAP_ATTRIBUTE_ATTRIBUTES (&AttributeInMapEntrys) & > > > MaskInMapEntrys.Uint64, > > > AttributeInMapEntrys.Bits.PageTableBaseAddress)); > > > + DEBUG ((DEBUG_INFO, "The total Mask is 0x%lx\n", > > > MaskInMapEntrys.Uint64)); > > > + > > > + if (MapEntrys->InitCount != 0) { > > > + DEBUG ((DEBUG_INFO, "Below is the initialization status:\n")); > > > + for (Index = 0; Index < InitMapCount; Index++) { > > > + if ((Address >= InitMap[Index].LinearAddress) && (Address < > > > (InitMap[Index].LinearAddress + InitMap[Index].Length))) { > > > + DEBUG ((DEBUG_INFO, " *")); > > > + } else { > > > + DEBUG ((DEBUG_INFO, " ")); > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, " %02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > > > InitMap[Index].LinearAddress, InitMap[Index].LinearAddress + > > > InitMap[Index].Length, InitMap[Index].Attribute.Uint64)); > > > + } > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, "Below is the inputs:\n")); > > > + DEBUG ((DEBUG_INFO, " Index: {LinearAddress, LinearLimit, Mask, > > > Attribute}\n")); > > > + for (Index = MapEntrys->InitCount; Index < MapEntrys->Count; > Index++) > > > { > > > + if ((Address >= MapEntrys->Maps[Index].LinearAddress) && > (Address < > > > (MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > > >Maps[Index].Length))) { > > > + DEBUG ((DEBUG_INFO, " *")); > > > + } else { > > > + DEBUG ((DEBUG_INFO, " ")); > > > + } > > > + > > > + DEBUG (( > > > + DEBUG_INFO, > > > + " %02d: {0x%lx, 0x%lx, 0x%lx,0x%lx}\n", > > > + Index, > > > + MapEntrys->Maps[Index].LinearAddress, > > > + MapEntrys->Maps[Index].LinearAddress + MapEntrys- > > > >Maps[Index].Length, > > > + MapEntrys->Maps[Index].Mask.Uint64, > > > + MapEntrys->Maps[Index].Attribute.Uint64 > > > + )); > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, "Below is the dumped from pagetable:\n")); > > > + for (Index = 0; Index < MapCount; Index++) { > > > + if ((Address >= Map[Index].LinearAddress) && (Address < > > > (Map[Index].LinearAddress + Map[Index].Length))) { > > > + DEBUG ((DEBUG_INFO, " *")); > > > + } else { > > > + DEBUG ((DEBUG_INFO, " ")); > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, "%02d: {0x%lx, 0x%lx, 0x%lx}\n", Index, > > > Map[Index].LinearAddress, Map[Index].LinearAddress + > Map[Index].Length, > > > Map[Index].Attribute.Uint64)); > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, "======detailed information > done=====\n")); > > > + return FALSE; > > > + } > > > + > > > + return TRUE; > > > +} > > > + > > > +/** > > > + Append key point of a given address to Buffer > > > + if buffer is NULL, only count needed count > > > + > > > + @param[in, out] Buffer Buffer to contains all key point. > > > + @param[in, out] Count Count of the key point. > > > + @param[in] Address given address > > > +**/ > > > +VOID > > > +AppendKeyPointToBuffer ( > > > + IN OUT UINT64 *Buffer, > > > + IN OUT UINTN *Count, > > > + IN UINT64 Address > > > + ) > > > +{ > > > + if ( Buffer != NULL) { > > > + Buffer[*Count] = Address; > > > + (*Count)++; > > > + Buffer[*Count] = Address+1; > > > + (*Count)++; > > > + Buffer[*Count] = Address-1; > > > + (*Count)++; > > > + } else { > > > + (*Count) = (*Count) +3; > > > + } > > > +} > > > + > > > +/** > > > + Get all key points from a buffer > > > + if buffer is NULL, only count needed count > > > + > > > + @param[in] MapEntrys Record every memory ranges that is used as > > > input > > > + @param[in] Map Pointer to an array that describes multiple linear > > > address ranges. > > > + @param[in] MapCount Pointer to a UINTN that hold the actual > number > > > of entries in the Map. > > > + @param[in, out] Buffer Buffer to contains all key point. > > > + @param[in, out] Count Count of the key point. > > > +**/ > > > +VOID > > > +GetKeyPointList ( > > > + IN MAP_ENTRYS *MapEntrys, > > > + IN IA32_MAP_ENTRY *Map, > > > + IN UINTN MapCount, > > > + IN OUT UINT64 *Buffer, > > > + IN OUT UINTN *Count > > > + ) > > > +{ > > > + UINTN TemCount; > > > + UINTN Index1; > > > + UINTN Index2; > > > + > > > + TemCount = 0; > > > + > > > + for (Index1 = 0; Index1 < MapEntrys->Count; Index1++) { > > > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > > > >Maps[Index1].LinearAddress); > > > + AppendKeyPointToBuffer (Buffer, &TemCount, MapEntrys- > > > >Maps[Index1].LinearAddress + MapEntrys->Maps[Index1].Length); > > > + } > > > + > > > + for (Index2 = 0; Index2 < MapCount; Index2++) { > > > + if (Buffer != NULL) { > > > + for (Index1 = 0; Index1 < TemCount; Index1++) { > > > + if (Buffer[Index1] == Map[Index2].LinearAddress) { > > > + break; > > > + } > > > + } > > > + > > > + if (Index1 < TemCount) { > > > + continue; > > > + } > > > + } > > > + > > > + AppendKeyPointToBuffer (Buffer, &TemCount, > > > Map[Index2].LinearAddress); > > > + } > > > + > > > + for (Index2 = 0; Index2 < MapCount; Index2++) { > > > + if (Buffer != NULL) { > > > + for (Index1 = 0; Index1 < TemCount; Index1++) { > > > + if (Buffer[Index1] == (Map[Index2].LinearAddress + > > > Map[Index2].Length)) { > > > + break; > > > + } > > > + } > > > + > > > + if (Index1 < TemCount) { > > > + continue; > > > + } > > > + } > > > + > > > + AppendKeyPointToBuffer (Buffer, &TemCount, > > > Map[Index2].LinearAddress + Map[Index2].Length); > > > + } > > > + > > > + *Count = TemCount; > > > +} > > > + > > > +/** > > > + Generate random one range with randome attribute, and add it into > > > pagetable > > > + Compare the key point has same attribute > > > + > > > + @param[in, out] PageTable The pointer to the page table to update, > or > > > pointer to NULL if a new page table is to be created. > > > + @param[in] PagingMode The paging mode. > > > + @param[in] MaxAddress Max Address. > > > + @param[in] MapEntrys Record every memory ranges that is used > as > > > input > > > + @param[in] PagesRecord Used to record memory usage for page > table. > > > + @param[in] InitMap Pointer to an array that describes init map > > > entries. > > > + @param[in] InitMapCount Pointer to a UINTN that hold the number > of > > > init map entries. > > > + > > > + @retval UNIT_TEST_PASSED The test is successful. > > > +**/ > > > +UNIT_TEST_STATUS > > > +SingleMapEntryTest ( > > > + IN OUT UINTN *PageTable, > > > + IN PAGING_MODE PagingMode, > > > + IN UINT64 MaxAddress, > > > + IN MAP_ENTRYS *MapEntrys, > > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > > + IN IA32_MAP_ENTRY *InitMap, > > > + IN UINTN InitMapCount > > > + ) > > > +{ > > > + UINTN MapsIndex; > > > + RETURN_STATUS Status; > > > + UINTN PageTableBufferSize; > > > + VOID *Buffer; > > > + IA32_MAP_ENTRY *Map; > > > + UINTN MapCount; > > > + UINTN Index; > > > + UINTN KeyPointCount; > > > + UINTN NewKeyPointCount; > > > + UINT64 *KeyPointBuffer; > > > + UINTN Level; > > > + UINT64 Value; > > > + UNIT_TEST_STATUS TestStatus; > > > + > > > + MapsIndex = MapEntrys->Count; > > > + > > > + GenerateSingleRandomMapEntry (MaxAddress, MapEntrys); > > > + > > > + PageTableBufferSize = 0; > > > + Status = PageTableMap ( > > > + PageTable, > > > + PagingMode, > > > + NULL, > > > + &PageTableBufferSize, > > > + MapEntrys->Maps[MapsIndex].LinearAddress, > > > + MapEntrys->Maps[MapsIndex].Length, > > > + &MapEntrys->Maps[MapsIndex].Attribute, > > > + &MapEntrys->Maps[MapsIndex].Mask > > > + ); > > > + if (PageTableBufferSize != 0) { > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + > > > + // > > > + // Allocate memory for Page table > > > + // Note the memory is used in one complete fuzzy test. > > > + // > > > + Buffer = PagesRecord->AllocatePagesForPageTable (PagesRecord, > > > EFI_SIZE_TO_PAGES (PageTableBufferSize)); > > > + UT_ASSERT_NOT_EQUAL (Buffer, NULL); > > > + Status = PageTableMap ( > > > + PageTable, > > > + PagingMode, > > > + Buffer, > > > + &PageTableBufferSize, > > > + MapEntrys->Maps[MapsIndex].LinearAddress, > > > + MapEntrys->Maps[MapsIndex].Length, > > > + &MapEntrys->Maps[MapsIndex].Attribute, > > > + &MapEntrys->Maps[MapsIndex].Mask > > > + ); > > > + } > > > + > > > + if (Status != RETURN_SUCCESS ) { > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + } > > > + > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + TestStatus = IsPageTableValid (*PageTable, PagingMode); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + MapCount = 0; > > > + Status = PageTableParse (*PageTable, PagingMode, NULL, > &MapCount); > > > + if (MapCount != 0) { > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + > > > + // > > > + // Allocate memory for Maps > > > + // Note the memory is only used in this one Single MapEntry Test > > > + // > > > + Map = AllocatePages (EFI_SIZE_TO_PAGES (MapCount * sizeof > > > (IA32_MAP_ENTRY))); > > > + ASSERT (Map != NULL); > > > + Status = PageTableParse (*PageTable, PagingMode, Map, > &MapCount); > > > + } > > > + > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + > > > + // > > > + // Allocate memory to record all key point > > > + // Note the memory is only used in this one Single MapEntry Test > > > + // > > > + KeyPointCount = 0; > > > + GetKeyPointList (MapEntrys, Map, MapCount, NULL, &KeyPointCount); > > > + KeyPointBuffer = AllocatePages (EFI_SIZE_TO_PAGES (KeyPointCount > * > > > sizeof (UINT64))); > > > + ASSERT (KeyPointBuffer != NULL); > > > + NewKeyPointCount = 0; > > > + GetKeyPointList (MapEntrys, Map, MapCount, KeyPointBuffer, > > > &NewKeyPointCount); > > > + > > > + // > > > + // Compare all key point's attribute > > > + // > > > + for (Index = 0; Index < NewKeyPointCount; Index++) { > > > + if (!CompareEntrysforOnePoint (KeyPointBuffer[Index], MapEntrys, > Map, > > > MapCount, InitMap, InitMapCount)) { > > > + DEBUG ((DEBUG_INFO, "Error happens at below key point\n")); > > > + DEBUG ((DEBUG_INFO, "Index = %d KeyPointBuffer[Index] = > 0x%lx\n", > > > Index, KeyPointBuffer[Index])); > > > + Value = GetEntryFromPageTable (*PageTable, PagingMode, > > > KeyPointBuffer[Index], &Level); > > > + DEBUG ((DEBUG_INFO, "From Page table, this key point is in level %d > > > entry, with entry value is 0x%lx\n", Level, Value)); > > > + UT_ASSERT_TRUE (FALSE); > > > + } > > > + } > > > + > > > + FreePages (KeyPointBuffer, EFI_SIZE_TO_PAGES (KeyPointCount * > sizeof > > > (UINT64))); > > > + if (MapCount != 0) { > > > + FreePages (Map, EFI_SIZE_TO_PAGES (MapCount * sizeof > > > (IA32_MAP_ENTRY))); > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Allocate page and record the information in PagesRecord > > > + > > > + @param[in] PagesRecord Point to a struct to record memory usage > > > + @param[in] Pages Page count needed to allocate > > > + > > > + @return A pointer to the allocated buffer or NULL if allocation fails. > > > +**/ > > > +VOID * > > > +EFIAPI > > > +RecordAllocatePages ( > > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > > + IN UINTN Pages > > > + ) > > > +{ > > > + VOID *Buffer; > > > + > > > + Buffer = NULL; > > > + if (PagesRecord->Count < PagesRecord->MaxCount) { > > > + Buffer = AllocatePages (Pages); > > > + PagesRecord->Records[PagesRecord->Count].Buffer = Buffer; > > > + PagesRecord->Records[PagesRecord->Count].Pages = Pages; > > > + PagesRecord->Count++; > > > + } > > > + > > > + ASSERT (Buffer != NULL); > > > + > > > + return Buffer; > > > +} > > > + > > > +/** > > > + The function is a whole fuzzy test, it will call SingleMapEntryTest for > > > ExpctedEntryNumber times > > > + > > > + @param[in] ExpctedEntryNumber The count of random entry > > > + @param[in] PagingMode The paging mode. > > > + > > > + @retval UNIT_TEST_PASSED The test is successful. > > > +**/ > > > +UNIT_TEST_STATUS > > > +MultipleMapEntryTest ( > > > + IN UINTN ExpctedEntryNumber, > > > + IN PAGING_MODE PagingMode > > > + ) > > > +{ > > > + UINTN PageTable; > > > + UINT64 MaxAddress; > > > + MAP_ENTRYS *MapEntrys; > > > + ALLOCATE_PAGE_RECORDS *PagesRecord; > > > + UINTN Index; > > > + UNIT_TEST_STATUS TestStatus; > > > + RETURN_STATUS Status; > > > + IA32_MAP_ENTRY *InitMap; > > > + UINTN InitMapCount; > > > + > > > + MaxAddress = GetMaxAddress (PagingMode); > > > + PageTable = 0; > > > + MapEntrys = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > > > (MAP_ENTRY) + sizeof (MAP_ENTRYS))); > > > + ASSERT (MapEntrys != NULL); > > > + MapEntrys->Count = 0; > > > + MapEntrys->InitCount = 0; > > > + MapEntrys->MaxCount = 1000; > > > + PagesRecord = AllocatePages (EFI_SIZE_TO_PAGES (1000*sizeof > > > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > > > + ASSERT (PagesRecord != NULL); > > > + PagesRecord->Count = 0; > > > + PagesRecord->MaxCount = 1000; > > > + PagesRecord->AllocatePagesForPageTable = RecordAllocatePages; > > > + > > > + if (mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) { > > > + ExpctedEntryNumber = ExpctedEntryNumber/2; > > > + } > > > + > > > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > > > + TestStatus = SingleMapEntryTest ( > > > + &PageTable, > > > + PagingMode, > > > + MaxAddress, > > > + MapEntrys, > > > + PagesRecord, > > > + NULL, > > > + 0 > > > + ); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + } > > > + > > > + if ((mFuzzOption & MANUAL_CHANGE_PAGE_TABLE) != 0) { > > > + MapEntrys->InitCount = ExpctedEntryNumber; > > > + TestStatus = ValidateAndRandomeModifyPageTable (PageTable, > > > PagingMode); > > > + RandomNumber = 0; > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + > > > + InitMapCount = 0; > > > + Status = PageTableParse (PageTable, PagingMode, NULL, > > > &InitMapCount); > > > + if (InitMapCount != 0) { > > > + UT_ASSERT_EQUAL (Status, RETURN_BUFFER_TOO_SMALL); > > > + > > > + // > > > + // Allocate memory for Maps > > > + // Note the memory is only used in this one Single MapEntry Test > > > + // > > > + InitMap = AllocatePages (EFI_SIZE_TO_PAGES (InitMapCount * > sizeof > > > (IA32_MAP_ENTRY))); > > > + ASSERT (InitMap != NULL); > > > + Status = PageTableParse (PageTable, PagingMode, InitMap, > > > &InitMapCount); > > > + } > > > + > > > + UT_ASSERT_EQUAL (Status, RETURN_SUCCESS); > > > + for (Index = 0; Index < ExpctedEntryNumber; Index++) { > > > + TestStatus = SingleMapEntryTest ( > > > + &PageTable, > > > + PagingMode, > > > + MaxAddress, > > > + MapEntrys, > > > + PagesRecord, > > > + InitMap, > > > + InitMapCount > > > + ); > > > + if (TestStatus != UNIT_TEST_PASSED) { > > > + return TestStatus; > > > + } > > > + } > > > + > > > + if (InitMapCount != 0) { > > > + FreePages (InitMap, EFI_SIZE_TO_PAGES (InitMapCount*sizeof > > > (IA32_MAP_ENTRY))); > > > + } > > > + } > > > + > > > + FreePages ( > > > + MapEntrys, > > > + EFI_SIZE_TO_PAGES (1000*sizeof (MAP_ENTRY) + sizeof > (MAP_ENTRYS)) > > > + ); > > > + > > > + for (Index = 0; Index < PagesRecord->Count; Index++) { > > > + FreePages (PagesRecord->Records[Index].Buffer, PagesRecord- > > > >Records[Index].Pages); > > > + } > > > + > > > + FreePages (PagesRecord, EFI_SIZE_TO_PAGES (1000*sizeof > > > (ALLOCATE_PAGE_RECORD) + sizeof (ALLOCATE_PAGE_RECORDS))); > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Fuzzy Test > > > + > > > + @param[in] Context [Optional] An optional parameter that enables: > > > + 1) test-case reuse with varied parameters and > > > + 2) test-case re-entry for Target tests that need a > > > + reboot. This parameter is a VOID* and it is the > > > + responsibility of the test author to ensure that the > > > + contents are well understood by all test cases that may > > > + consume it. > > > + > > > + @retval UNIT_TEST_PASSED The Unit test has completed and > the > > > test > > > + case was successful. > > > + @retval UNIT_TEST_ERROR_TEST_FAILED A test case assertion has > failed. > > > +**/ > > > +UNIT_TEST_STATUS > > > +EFIAPI > > > +TestCaseforFuzzyTest ( > > > + IN UNIT_TEST_CONTEXT Context > > > + ) > > > +{ > > > + UNIT_TEST_STATUS Status; > > > + UINTN Index; > > > + > > > + UT_ASSERT_EQUAL (RandomSeed (NULL, 0), TRUE); > > > + UT_ASSERT_EQUAL (Random32 (100, 100), 100); > > > + UT_ASSERT_EQUAL (Random64 (100, 100), 100); > > > + UT_ASSERT_TRUE ((Random32 (9, 10) >= 9) & (Random32 (9, 10) <= > 10)); > > > + UT_ASSERT_TRUE ((Random64 (9, 10) >= 9) & (Random64 (9, 10) <= > 10)); > > > + > > > + mSupportedBit.Bits.Present = 1; > > > + mSupportedBit.Bits.ReadWrite = 1; > > > + mSupportedBit.Bits.UserSupervisor = 1; > > > + mSupportedBit.Bits.WriteThrough = 1; > > > + mSupportedBit.Bits.CacheDisabled = 1; > > > + mSupportedBit.Bits.Accessed = 1; > > > + mSupportedBit.Bits.Dirty = 1; > > > + mSupportedBit.Bits.Pat = 1; > > > + mSupportedBit.Bits.Global = 1; > > > + mSupportedBit.Bits.Reserved1 = 0; > > > + mSupportedBit.Bits.PageTableBaseAddress = 0; > > > + mSupportedBit.Bits.Reserved2 = 0; > > > + mSupportedBit.Bits.ProtectionKey = 0xF; > > > + mSupportedBit.Bits.Nx = 1; > > > + > > > + mFuzzOption = ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > *)Context)->FuzzOption; > > > + mNumberIndex = 0; > > > + > > > + for (Index = 0; Index < ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT > > > *)Context)->TestCount; Index++) { > > > + Status = MultipleMapEntryTest ( > > > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > > > >TestRangeCount, > > > + ((CPU_PAGE_TABLE_LIB_FUZZY_TEST_CONTEXT *)Context)- > > > >PagingMode > > > + ); > > > + if (Status != UNIT_TEST_PASSED) { > > > + return Status; > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, ".")); > > > + } > > > + > > > + DEBUG ((DEBUG_INFO, "\n")); > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > > new file mode 100644 > > > index 0000000000..e7c35b1c29 > > > --- /dev/null > > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/FuzzyTest.h > > > @@ -0,0 +1,57 @@ > > > +/** @file > > > + Internal header for fuzzy test. > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#ifndef FUZZY_TEST_H_ > > > +#define FUZZY_TEST_H_ > > > + > > > +#include "CpuPageTableLibUnitTest.h" > > > + > > > +typedef struct _ALLOCATE_PAGE_RECORDS ALLOCATE_PAGE_RECORDS; > > > + > > > +typedef > > > +VOID * > > > +(EFIAPI *ALLOCATE_PAGES)( > > > + IN ALLOCATE_PAGE_RECORDS *PagesRecord, > > > + IN UINTN Pages > > > + ); > > > + > > > +typedef struct { > > > + VOID *Buffer; > > > + UINTN Pages; > > > +} ALLOCATE_PAGE_RECORD; > > > + > > > +struct _ALLOCATE_PAGE_RECORDS { > > > + UINTN Count; > > > + UINTN MaxCount; > > > + ALLOCATE_PAGES AllocatePagesForPageTable; > > > + ALLOCATE_PAGE_RECORD Records[0]; > > > +}; > > > + > > > +typedef struct { > > > + UINT64 LinearAddress; > > > + UINT64 Length; > > > + IA32_MAP_ATTRIBUTE Attribute; > > > + IA32_MAP_ATTRIBUTE Mask; > > > +} MAP_ENTRY; > > > + > > > +typedef struct { > > > + UINTN Count; > > > + UINTN InitCount; > > > + UINTN MaxCount; > > > + MAP_ENTRY Maps[10]; > > > +} MAP_ENTRYS; > > > + > > > +UINT64 > > > +GetEntryFromPageTable ( > > > + IN UINTN PageTable, > > > + IN PAGING_MODE PagingMode, > > > + IN UINT64 Address, > > > + OUT UINTN *Level > > > + ); > > > + > > > +#endif > > > diff --git > a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > > new file mode 100644 > > > index 0000000000..4ccbc47d9e > > > --- /dev/null > > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/RandomNumber.c > > > @@ -0,0 +1,5009 @@ > > > +/** @file > > > + Pre-generated random number used by CpuPageTableLib test. > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + **/ > > > +UINTN mNumberCount = 50000; > > > +UINT8 mNumbers[] = { > > > + 250, 22, 243, 87, 160, 129, 26, 103, 242, 136, > > > + 193, 195, 125, 183, 205, 246, 65, 169, 187, 121, > > > + 129, 195, 32, 183, 49, 100, 34, 51, 143, 84, > > > + 215, 111, 113, 121, 59, 119, 33, 56, 224, 245, > > > + 254, 244, 114, 20, 63, 216, 118, 253, 145, 171, > > > + 108, 208, 155, 4, 47, 174, 154, 5, 92, 107, > > > + 127, 176, 76, 238, 147, 4, 21, 26, 116, 251, > > > + 54, 33, 126, 239, 125, 21, 188, 17, 65, 2, > > > + 176, 77, 54, 82, 60, 32, 133, 105, 5, 211, > > > + 41, 67, 24, 246, 122, 160, 96, 3, 27, 53, > > > + 116, 129, 220, 46, 16, 251, 49, 70, 149, 153, > > > + 14, 102, 69, 131, 125, 166, 221, 13, 36, 189, > > > + 103, 28, 229, 50, 217, 174, 163, 98, 1, 101, > > > + 226, 237, 164, 232, 153, 165, 48, 155, 152, 26, > > > + 112, 129, 155, 23, 84, 154, 53, 147, 240, 195, > > > + 248, 207, 129, 49, 35, 151, 90, 77, 170, 216, > > > + 27, 51, 143, 214, 195, 161, 61, 219, 68, 106, > > > + 159, 225, 204, 197, 59, 176, 37, 203, 61, 23, > > > + 12, 76, 116, 118, 169, 250, 161, 68, 2, 247, > > > + 184, 242, 199, 226, 86, 150, 216, 112, 116, 194, > > > + 57, 173, 11, 146, 23, 244, 168, 185, 85, 234, > > > + 57, 209, 48, 95, 130, 137, 107, 148, 113, 152, > > > + 28, 152, 53, 2, 180, 115, 18, 32, 93, 178, > > > + 158, 230, 216, 3, 230, 150, 244, 153, 200, 24, > > > + 54, 195, 181, 205, 234, 159, 76, 162, 92, 91, > > > + 255, 87, 145, 10, 250, 76, 150, 79, 13, 48, > > > + 119, 161, 245, 145, 56, 216, 107, 237, 189, 197, > > > + 192, 90, 52, 251, 176, 247, 163, 5, 82, 56, > > > + 234, 155, 160, 208, 252, 10, 1, 148, 153, 21, > > > + 221, 42, 205, 226, 6, 13, 243, 146, 123, 14, > > > + 234, 102, 179, 156, 13, 30, 31, 182, 179, 252, > > > + 32, 174, 65, 247, 53, 152, 106, 134, 120, 116, > > > + 188, 59, 59, 217, 26, 39, 113, 246, 170, 127, > > > + 91, 18, 15, 117, 9, 175, 165, 92, 111, 208, > > > + 250, 48, 33, 57, 14, 129, 154, 4, 95, 216, > > > + 76, 51, 80, 234, 173, 189, 203, 146, 54, 6, > > > + 225, 175, 138, 148, 49, 123, 112, 211, 195, 119, > > > + 248, 241, 24, 60, 0, 70, 109, 54, 49, 157, > > > + 240, 15, 171, 235, 76, 60, 236, 105, 92, 183, > > > + 238, 160, 203, 157, 205, 246, 149, 13, 246, 67, > > > + 205, 249, 245, 154, 81, 30, 149, 145, 227, 208, > > > + 65, 190, 72, 232, 102, 176, 69, 231, 156, 85, > > > + 216, 241, 192, 157, 88, 169, 247, 23, 200, 41, > > > + 247, 62, 173, 240, 35, 52, 98, 224, 159, 53, > > > + 15, 141, 59, 213, 100, 28, 76, 48, 26, 73, > > > + 48, 209, 164, 18, 176, 99, 15, 248, 154, 240, > > > + 134, 70, 217, 179, 133, 76, 222, 185, 247, 40, > > > + 139, 101, 85, 137, 197, 186, 89, 66, 35, 127, > > > + 31, 201, 231, 81, 39, 206, 99, 231, 106, 26, > > > + 69, 72, 208, 207, 49, 227, 141, 233, 41, 247, > > > + 176, 102, 47, 51, 237, 80, 88, 149, 229, 18, > > > + 89, 77, 126, 156, 32, 72, 132, 216, 247, 142, > > > + 103, 179, 220, 178, 162, 133, 215, 249, 52, 160, > > > + 25, 223, 226, 103, 4, 253, 103, 93, 191, 46, > > > + 250, 20, 186, 223, 145, 73, 114, 195, 159, 76, > > > + 44, 215, 46, 142, 190, 141, 201, 241, 134, 40, > > > + 135, 140, 28, 105, 147, 102, 55, 210, 102, 44, > > > + 180, 229, 217, 207, 46, 145, 161, 94, 8, 44, > > > + 110, 4, 38, 254, 174, 75, 36, 64, 113, 51, > > > + 98, 73, 97, 94, 147, 101, 168, 22, 67, 232, > > > + 3, 20, 35, 104, 166, 105, 168, 45, 133, 122, > > > + 101, 170, 238, 103, 31, 245, 66, 16, 81, 166, > > > + 68, 155, 34, 71, 172, 186, 156, 37, 105, 171, > > > + 90, 137, 248, 76, 123, 220, 208, 138, 209, 48, > > > + 127, 195, 191, 150, 19, 19, 148, 229, 91, 73, > > > + 204, 28, 112, 141, 239, 86, 130, 65, 238, 77, > > > + 0, 133, 137, 105, 62, 107, 0, 132, 109, 180, > > > + 182, 194, 215, 232, 207, 171, 189, 50, 169, 186, > > > + 177, 76, 56, 56, 155, 204, 176, 145, 80, 67, > > > + 178, 229, 32, 144, 10, 182, 98, 7, 129, 74, > > > + 216, 213, 96, 172, 206, 205, 27, 4, 215, 121, > > > + 55, 60, 73, 234, 223, 181, 60, 150, 32, 212, > > > + 254, 35, 202, 173, 9, 234, 0, 103, 229, 21, > > > + 23, 137, 101, 75, 102, 40, 225, 180, 203, 121, > > > + 109, 172, 227, 249, 172, 75, 126, 33, 1, 20, > > > + 130, 66, 205, 131, 154, 16, 72, 184, 76, 10, > > > + 98, 226, 65, 208, 177, 154, 111, 80, 130, 27, > > > + 46, 224, 46, 113, 61, 227, 125, 136, 118, 129, > > > + 121, 144, 140, 83, 197, 235, 226, 140, 141, 154, > > > + 240, 173, 133, 114, 138, 101, 114, 242, 73, 70, > > > + 104, 236, 72, 141, 58, 129, 108, 211, 11, 189, > > > + 212, 95, 37, 117, 40, 236, 67, 168, 251, 228, > > > + 111, 152, 209, 130, 3, 209, 8, 21, 217, 223, > > > + 202, 134, 159, 13, 126, 137, 150, 185, 93, 207, > > > + 218, 38, 77, 183, 197, 250, 134, 36, 184, 228, > > > + 213, 109, 220, 69, 219, 229, 39, 153, 78, 125, > > > + 223, 57, 239, 131, 116, 73, 4, 147, 105, 239, > > > + 132, 57, 160, 255, 66, 233, 145, 183, 225, 82, > > > + 170, 151, 244, 113, 130, 180, 63, 66, 236, 237, > > > + 7, 82, 29, 141, 83, 61, 93, 219, 79, 89, > > > + 192, 102, 77, 47, 191, 96, 250, 191, 186, 235, > > > + 24, 40, 244, 70, 91, 193, 102, 171, 110, 55, > > > + 158, 127, 226, 211, 86, 16, 56, 42, 20, 81, > > > + 143, 82, 47, 189, 112, 85, 246, 111, 177, 229, > > > + 28, 179, 101, 35, 114, 38, 148, 26, 134, 246, > > > + 123, 102, 141, 0, 11, 207, 173, 232, 92, 129, > > > + 182, 97, 175, 143, 89, 42, 112, 238, 3, 137, > > > + 96, 51, 150, 148, 20, 71, 4, 209, 94, 181, > > > + 232, 175, 110, 244, 148, 44, 172, 99, 129, 161, > > > + 253, 136, 100, 180, 141, 103, 81, 153, 96, 213, > > > + 250, 140, 9, 89, 93, 123, 166, 177, 85, 235, > > > + 56, 72, 63, 15, 164, 161, 5, 68, 214, 188, > > > + 93, 15, 41, 64, 233, 117, 0, 9, 255, 96, > > > + 190, 47, 27, 209, 79, 28, 117, 202, 185, 211, > > > + 58, 184, 150, 75, 67, 22, 36, 243, 148, 21, > > > + 218, 208, 214, 68, 173, 218, 164, 50, 139, 85, > > > + 108, 106, 134, 4, 22, 210, 181, 209, 187, 239, > > > + 137, 19, 250, 75, 93, 117, 214, 21, 138, 62, > > > + 249, 172, 72, 36, 209, 119, 198, 35, 156, 231, > > > + 7, 3, 153, 29, 46, 197, 147, 47, 105, 234, > > > + 129, 160, 130, 96, 231, 27, 178, 11, 180, 172, > > > + 155, 168, 14, 66, 73, 211, 143, 171, 42, 61, > > > + 36, 34, 207, 31, 56, 158, 138, 30, 125, 238, > > > + 145, 56, 93, 233, 231, 195, 115, 208, 54, 131, > > > + 171, 11, 13, 151, 41, 39, 165, 132, 44, 147, > > > + 79, 140, 107, 103, 189, 108, 51, 24, 178, 214, > > > + 21, 139, 25, 240, 231, 36, 17, 132, 246, 211, > > > + 87, 62, 149, 98, 27, 209, 189, 72, 11, 181, > > > + 151, 161, 3, 254, 90, 120, 62, 40, 36, 49, > > > + 71, 206, 33, 234, 57, 76, 112, 23, 79, 22, > > > + 181, 9, 105, 251, 193, 84, 103, 75, 114, 30, > > > + 49, 0, 36, 168, 169, 205, 11, 154, 187, 2, > > > + 115, 168, 242, 251, 244, 124, 77, 39, 174, 42, > > > + 182, 162, 124, 76, 201, 92, 47, 110, 5, 122, > > > + 35, 139, 212, 181, 239, 120, 99, 105, 29, 143, > > > + 109, 13, 242, 219, 38, 82, 197, 44, 28, 160, > > > + 7, 181, 82, 144, 156, 83, 28, 68, 240, 147, > > > + 119, 247, 130, 55, 158, 175, 41, 23, 126, 98, > > > + 89, 192, 233, 22, 24, 13, 170, 83, 122, 125, > > > + 28, 72, 120, 237, 115, 29, 171, 236, 52, 187, > > > + 191, 160, 36, 10, 104, 77, 170, 46, 138, 53, > > > + 42, 89, 131, 119, 94, 198, 237, 180, 158, 81, > > > + 202, 1, 238, 141, 245, 65, 108, 177, 235, 9, > > > + 156, 167, 59, 55, 105, 49, 191, 116, 110, 255, > > > + 121, 123, 87, 28, 80, 47, 10, 24, 228, 107, > > > + 99, 107, 167, 144, 174, 2, 89, 53, 62, 151, > > > + 143, 221, 30, 226, 135, 203, 50, 39, 96, 119, > > > + 46, 121, 13, 178, 103, 245, 218, 141, 158, 112, > > > + 155, 1, 7, 130, 35, 6, 57, 67, 59, 27, > > > + 81, 136, 147, 51, 17, 147, 119, 236, 173, 150, > > > + 150, 241, 201, 35, 31, 144, 12, 121, 118, 165, > > > + 102, 70, 234, 179, 183, 60, 19, 159, 217, 6, > > > + 207, 87, 88, 189, 215, 198, 244, 7, 16, 143, > > > + 24, 132, 116, 74, 205, 147, 33, 232, 141, 96, > > > + 140, 249, 67, 82, 57, 38, 34, 238, 161, 2, > > > + 201, 207, 5, 110, 75, 231, 239, 22, 255, 56, > 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78, 64, 221, 25, > > > + 67, 33, 113, 24, 90, 123, 223, 86, 228, 242, > > > + 134, 21, 240, 230, 10, 184, 65, 103, 157, 183, > > > + 130, 5, 253, 139, 60, 105, 38, 39, 217, 29, > > > + 203, 117, 213, 90, 150, 45, 153, 143, 121, 202, > > > + 251, 57, 58, 88, 212, 152, 195, 43, 7, 92, > > > + 227, 14, 74, 242, 54, 172, 135, 150, 101, 247, > > > + 81, 82, 240, 10, 46, 17, 196, 179, 18, 195, > > > + 12, 179, 98, 1, 126, 158, 6, 95, 41, 122, > > > + 118, 143, 0, 75, 197, 239, 112, 133, 213, 46, > > > + 148, 60, 4, 49, 224, 138, 248, 77, 212, 6, > > > + 250, 85, 209, 147, 161, 162, 209, 235, 99, 60, > > > + 19, 115, 5, 219, 171, 195, 184, 236, 60, 241, > > > + 141, 6, 132, 100, 225, 35, 64, 131, 97, 130, > > > + 19, 226, 201, 64, 225, 146, 233, 49, 74, 203, > > > + 206, 35, 249, 43, 97, 102, 138, 59, 125, 33, > > > + 220, 143, 173, 212, 8, 12, 215, 93, 173, 220, > > > + 238, 140, 218, 73, 219, 243, 91, 44, 100, 20, > > > + 79, 232, 177, 204, 107, 153, 234, 167, 207, 9, > > > + 154, 46, 159, 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> > + 223, 141, 167, 95, 78, 151, 44, 210, 144, 143, > > > + 171, 100, 140, 187, 23, 178, 14, 55, 249, 68, > > > + 187, 200, 201, 50, 7, 30, 155, 254, 77, 159, > > > + 34, 123, 101, 249, 230, 56, 130, 54, 180, 151, > > > + 124, 15, 219, 98, 165, 58, 39, 195, 87, 139, > > > + 0, 45, 140, 182, 223, 51, 214, 19, 61, 109, > > > + 205, 84, 12, 127, 75, 233, 139, 204, 87, 34, > > > + 88, 88, 98, 29, 63, 106, 233, 163, 234, 183, > > > + 166, 56, 113, 26, 49, 51, 25, 104, 147, 183, > > > + 152, 76, 62, 12, 117, 217, 99, 100, 213, 202, > > > + 239, 172, 24, 50, 212, 156, 251, 63, 34, 70, > > > + 159, 92, 35, 196, 181, 253, 192, 146, 145, 35, > > > + 123, 6, 47, 227, 2, 211, 115, 145, 73, 0, > > > + 179, 66, 17, 197, 86, 70, 106, 18, 162, 122, > > > + 186, 101, 137, 166, 232, 109, 82, 247, 223, 111, > > > +}; > > > diff --git a/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > > b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > > new file mode 100644 > > > index 0000000000..5bd70c0f65 > > > --- /dev/null > > > +++ b/UefiCpuPkg/Library/CpuPageTableLib/UnitTest/TestHelper.c > > > @@ -0,0 +1,309 @@ > > > +/** @file > > > + helper file for Unit tests of the CpuPageTableLib instance of the > > > CpuPageTableLib class > > > + > > > + Copyright (c) 2022, Intel Corporation. All rights reserved.<BR> > > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > > + > > > +**/ > > > + > > > +#include "CpuPageTableLibUnitTest.h" > > > +#include "../CpuPageTable.h" > > > + > > > +// > > > +// Global Data to validate if the page table is legal > > > +// mValidMaskNoLeaf[0] is not used > > > +// mValidMaskNoLeaf[1] ... mValidMaskNoLeaf [5] represent PTE ... > PML5E > > > +// mValidMaskNoLeaf[Index] means if it is a valid no leaf entry, entry > > > should equal to (entry & mValidMaskNoLeaf[Index]) > > > +// mValidMaskLeaf[Index] means if it is a valid leaf entry, entry should > > > equal to (entry & mValidMaskLeaf[Index]) > > > +// mValidMaskLeafFlag[Index] means if it is a leaf entry, if and only if > ((entry > > > & mValidMaskLeafFlag[Index]) == mValidMaskLeafFlag[Index]) > > > +// > > > +IA32_PAGING_ENTRY mValidMaskNoLeaf[6]; > > > +IA32_PAGING_ENTRY mValidMaskLeaf[6]; > > > +IA32_PAGING_ENTRY mValidMaskLeafFlag[6]; > > > + > > > +/** > > > + Init global data. > > > + > > > + @param[in] MemorySpace Memory space > > > +**/ > > > +VOID > > > +InitGlobalData ( > > > + UINTN MemorySpace > > > + ) > > > +{ > > > + UINTN Index; > > > + > > > + ASSERT (MemorySpace <= 52); > > > + mValidMaskNoLeaf[0].Uint64 = 0; > > > + mValidMaskLeaf[0].Uint64 = 0; > > > + mValidMaskLeafFlag[0].Uint64 = 0; > > > + > > > + // > > > + // Set common part for all kinds of entrys. > > > + // > > > + for (Index = 1; Index < 6; Index++) { > > > + mValidMaskNoLeaf[Index].Uint64 = MAX_UINT64; > > > + mValidMaskLeaf[Index].Uint64 = MAX_UINT64; > > > + > > > + // > > > + // bit 51:M is reserved, and should be zero > > > + // > > > + if (MemorySpace - 1 < 51) { > > > + mValidMaskNoLeaf[Index].Uint64 = BitFieldWrite64 > > > (mValidMaskNoLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > > > + mValidMaskLeaf[Index].Uint64 = BitFieldWrite64 > > > (mValidMaskLeaf[Index].Uint64, MemorySpace - 1, 51, 0); > > > + } > > > + } > > > + > > > + // > > > + // Handle mask for no leaf entry. > > > + // > > > + mValidMaskNoLeaf[1].Uint64 = 0; // PTE can't map to page > > > structure. > > > + mValidMaskNoLeaf[2].Pnle.Bits.MustBeZero = 0; // for PML4E, bit 7 > must > > > be zero. > > > + mValidMaskNoLeaf[3].Pnle.Bits.MustBeZero = 0; // for PML5E, bit 7 > must > > > be zero. > > > + mValidMaskNoLeaf[4].Pml4.Bits.MustBeZero = 0; // for PML4E, bit 7 > must > > > be zero. > > > + mValidMaskNoLeaf[5].Pml4.Bits.MustBeZero = 0; // for PML5E, bit 7 > must > > > be zero. > > > + > > > + // > > > + // Handle mask for leaf entry. > > > + // No need to modification for PTE, since it doesn't have extra reserved > bit > > > + // > > > + mValidMaskLeaf[2].Uint64 = BitFieldWrite64 > (mValidMaskLeaf[2].Uint64, > > > 13, 20, 0); // bit 13-20 is reserved for PDE > > > + mValidMaskLeaf[3].Uint64 = BitFieldWrite64 > (mValidMaskLeaf[2].Uint64, > > > 13, 29, 0); // bit 13-29 is reserved for PDPTE > > > + mValidMaskLeaf[4].Uint64 = 0; // for PML4E, > no > > > possible to map to page. > > > + mValidMaskLeaf[5].Uint64 = 0; // for PML5E, > no > > > possible to map to page. > > > + > > > + // > > > + // Handle Flags to indicate it is a leaf entry. > > > + // for PML4E and PML5E, no possible to map to page, so the flag should > be > > > MAX_UINT64. > > > + // > > > + mValidMaskLeafFlag[1].Pce.Present = 1; // For PTE, as long as it is > present, > > > it maps to page > > > + // > > > + // For PDE and PDPTE, the bit 7 should be set to map to pages > > > + // > > > + mValidMaskLeafFlag[2].Pde2M.Bits.MustBeOne = 1; > > > + mValidMaskLeafFlag[2].Pde2M.Bits.Present = 1; > > > + mValidMaskLeafFlag[3].Pde2M.Bits.MustBeOne = 1; > > > + mValidMaskLeafFlag[3].Pde2M.Bits.Present = 1; > > > + mValidMaskLeafFlag[4].Uint64 = MAX_UINT64; > > > + mValidMaskLeafFlag[5].Uint64 = MAX_UINT64; > > > +} > > > + > > > +/** > > > + Check if the Page table entry is valid > > > + > > > + @param[in] PagingEntry The entry in page table to verify > > > + @param[in] Level the level of PagingEntry. > > > + @param[in] MaxLeafLevel Max leaf entry level. > > > + @param[in] LinearAddress The linear address verified. > > > + > > > + @retval Leaf entry. > > > +**/ > > > +UNIT_TEST_STATUS > > > +IsPageTableEntryValid ( > > > + IN IA32_PAGING_ENTRY *PagingEntry, > > > + IN UINTN Level, > > > + IN UINTN MaxLeafLevel, > > > + IN UINT64 Address > > > + ) > > > +{ > > > + UINT64 Index; > > > + IA32_PAGING_ENTRY *ChildPageEntry; > > > + UNIT_TEST_STATUS Status; > > > + > > > + if (PagingEntry->Pce.Present == 0) { > > > + return UNIT_TEST_PASSED; > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[Level].Uint64) == > > > mValidMaskLeafFlag[Level].Uint64) { > > > + // > > > + // It is a Leaf > > > + // > > > + if (Level > MaxLeafLevel) { > > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d entry 0x%lx is a leaf > entry, > > > but max leaf level is %d \n", Level, PagingEntry->Uint64, MaxLeafLevel)); > > > + UT_ASSERT_TRUE (Level <= MaxLeafLevel); > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeaf[Level].Uint64) != > PagingEntry- > > > >Uint64) { > > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d Leaf entry is 0x%lx, > which > > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > > mValidMaskLeaf[Level].Uint64), PagingEntry->Uint64); > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > + } > > > + > > > + // > > > + // Not a leaf > > > + // > > > + UT_ASSERT_NOT_EQUAL (Level, 1); > > > + if ((PagingEntry->Uint64 & mValidMaskNoLeaf[Level].Uint64) != > > > PagingEntry->Uint64) { > > > + DEBUG ((DEBUG_ERROR, "ERROR: Level %d no Leaf entry is 0x%lx, > which > > > reserved bit is set \n", Level, PagingEntry->Uint64)); > > > + UT_ASSERT_EQUAL ((PagingEntry->Uint64 & > > > mValidMaskNoLeaf[Level].Uint64), PagingEntry->Uint64); > > > + } > > > + > > > + ChildPageEntry = (IA32_PAGING_ENTRY > > > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << > 12); > > > + for (Index = 0; Index < 512; Index++) { > > > + Status = IsPageTableEntryValid (&ChildPageEntry[Index], Level-1, > > > MaxLeafLevel, Address + (Index<<(9*(Level-1) + 3))); > > > + if (Status != UNIT_TEST_PASSED) { > > > + return Status; > > > + } > > > + } > > > + > > > + return UNIT_TEST_PASSED; > > > +} > > > + > > > +/** > > > + Check if the Page table is valid > > > + > > > + @param[in] PageTable The pointer to the page table. > > > + @param[in] PagingMode The paging mode. > > > + > > > + @retval UNIT_TEST_PASSED It is a valid Page Table > > > +**/ > > > +UNIT_TEST_STATUS > > > +IsPageTableValid ( > > > + IN UINTN PageTable, > > > + IN PAGING_MODE PagingMode > > > + ) > > > +{ > > > + UINTN MaxLevel; > > > + UINTN MaxLeafLevel; > > > + UINT64 Index; > > > + UNIT_TEST_STATUS Status; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + > > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > > (PagingMode >= PagingModeMax)) { > > > + // > > > + // 32bit paging is never supported. > > > + // PAE paging will be supported later. > > > + // > > > + return UNIT_TEST_ERROR_TEST_FAILED; > > > + } > > > + > > > + MaxLeafLevel = (UINT8)PagingMode; > > > + MaxLevel = (UINT8)(PagingMode >> 8); > > > + > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > + for (Index = 0; Index < 512; Index++) { > > > + Status = IsPageTableEntryValid (&PagingEntry[Index], MaxLevel, > > > MaxLeafLevel, Index << (9 * MaxLevel + 3)); > > > + if (Status != UNIT_TEST_PASSED) { > > > + return Status; > > > + } > > > + } > > > + > > > + return Status; > > > +} > > > + > > > +/** > > > + Get the leaf entry for a given linear address from one entry in page > table > > > + > > > + @param[in] PagingEntry The entry in page table which covers the > > > linear address > > > + @param[in, out] Level On input, is the level of PagingEntry. > > > + On outout, is the level of the leaf entry > > > + @param[in] MaxLeafLevel Max leaf entry level. > > > + @param[in] LinearAddress The linear address. > > > + > > > + @retval Leaf entry. > > > +**/ > > > +UINT64 > > > +GetEntryFromSubPageTable ( > > > + IN IA32_PAGING_ENTRY *PagingEntry, > > > + IN OUT UINTN *Level, > > > + IN UINTN MaxLeafLevel, > > > + IN UINT64 Address > > > + ) > > > +{ > > > + UINT64 Index; > > > + IA32_PAGING_ENTRY *ChildPageEntry; > > > + > > > + if (PagingEntry->Pce.Present == 0) { > > > + return 0; > > > + } > > > + > > > + if ((PagingEntry->Uint64 & mValidMaskLeafFlag[*Level].Uint64) == > > > mValidMaskLeafFlag[*Level].Uint64) { > > > + // > > > + // It is a Leaf > > > + // > > > + return PagingEntry->Uint64; > > > + } > > > + > > > + // > > > + // Not a leaf > > > + // > > > + ChildPageEntry = (IA32_PAGING_ENTRY > > > *)(UINTN)(((UINTN)(PagingEntry->Pnle.Bits.PageTableBaseAddress)) << > 12); > > > + *Level = *Level -1; > > > + Index = Address >> (*Level * 9 + 3); > > > + ASSERT (Index == (Index & ((1<< 9) - 1))); > > > + > > > + return GetEntryFromSubPageTable (&ChildPageEntry[Index], Level, > > > MaxLeafLevel, Address - (Index << (9 * *Level + 3))); > > > +} > > > + > > > +/** > > > + Get the leaf entry for a given linear address from a page table > > > + > > > + @param[in] PageTable The pointer to the page table. > > > + @param[in] PagingMode The paging mode. > > > + @param[in] LinearAddress The linear address. > > > + @param[out] Level leaf entry's level. > > > + > > > + @retval Leaf entry. > > > +**/ > > > +UINT64 > > > +GetEntryFromPageTable ( > > > + IN UINTN PageTable, > > > + IN PAGING_MODE PagingMode, > > > + IN UINT64 Address, > > > + OUT UINTN *Level > > > + ) > > > +{ > > > + UINTN MaxLevel; > > > + UINTN MaxLeafLevel; > > > + UINT64 Index; > > > + IA32_PAGING_ENTRY *PagingEntry; > > > + > > > + if ((PagingMode == Paging32bit) || (PagingMode == PagingPae) || > > > (PagingMode >= PagingModeMax)) { > > > + // > > > + // 32bit paging is never supported. > > > + // PAE paging will be supported later. > > > + // > > > + return 0; > > > + } > > > + > > > + MaxLeafLevel = (UINT8)PagingMode; > > > + MaxLevel = (UINT8)(PagingMode >> 8); > > > + > > > + Index = Address >> (MaxLevel * 9 + 3); > > > + ASSERT (Index == (Index & ((1<< 9) - 1))); > > > + PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)PageTable; > > > + *Level = MaxLevel; > > > + > > > + return GetEntryFromSubPageTable (&PagingEntry[Index], Level, > > > MaxLeafLevel, Address - (Index << (9 * MaxLevel + 3))); > > > +} > > > + > > > +/** > > > + Get max physical adrress supported by specific page mode > > > + > > > + @param[in] Mode The paging mode. > > > + > > > + @retval max address. > > > +**/ > > > +UINT64 > > > +GetMaxAddress ( > > > + IN PAGING_MODE Mode > > > + ) > > > +{ > > > + switch (Mode) { > > > + case Paging32bit: > > > + case PagingPae: > > > + return SIZE_4GB; > > > + > > > + case Paging4Level: > > > + case Paging4Level1GB: > > > + case Paging5Level: > > > + case Paging5Level1GB: > > > + return 1ull << MIN (12 + (Mode >> 8) * 9, 52); > > > + > > > + default: > > > + ASSERT (0); > > > + return 0; > > > + } > > > +} > > > diff --git a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > > b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > > index 8a5c456830..e72e4cd622 100644 > > > --- a/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > > +++ b/UefiCpuPkg/Test/UefiCpuPkgHostTest.dsc > > > @@ -20,6 +20,10 @@ > > > > > > [LibraryClasses] > > > MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf > > > + > > > > CpuPageTableLib|UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableLib.inf > > > + OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf > > > + > > > > BaseCryptLib|CryptoPkg/Library/BaseCryptLib/UnitTestHostBaseCryptLib.inf > > > + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf > > > > > > [PcdsPatchableInModule] > > > > gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0 > > > @@ -29,3 +33,8 @@ > > > # Build HOST_APPLICATION that tests the MtrrLib > > > # > > > UefiCpuPkg/Library/MtrrLib/UnitTest/MtrrLibUnitTestHost.inf > > > + > > > + # > > > + # Build HOST_APPLICATION that tests the CpuPageTableLib > > > + # > > > + > > > > UefiCpuPkg/Library/CpuPageTableLib/UnitTest/CpuPageTableLibUnitTestHo > > > st.inf > > > diff --git a/UefiCpuPkg/UefiCpuPkg.ci.yaml > > > b/UefiCpuPkg/UefiCpuPkg.ci.yaml > > > index 6e0ab95fd8..bbdc44a45b 100644 > > > --- a/UefiCpuPkg/UefiCpuPkg.ci.yaml > > > +++ b/UefiCpuPkg/UefiCpuPkg.ci.yaml > > > @@ -15,6 +15,7 @@ > > > ## "<ErrorID>", "<KeyWord>" > > > ## ] > > > "ExceptionList": [ > > > + "8006", "main" > > > ], > > > ## Both file path and directory path are accepted. > > > "IgnoreFiles": [ > > > @@ -38,7 +39,8 @@ > > > ], > > > # For host based unit tests > > > "AcceptableDependencies-HOST_APPLICATION":[ > > > - "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec" > > > + "UnitTestFrameworkPkg/UnitTestFrameworkPkg.dec", > > > + "CryptoPkg/CryptoPkg.dec" > > > ], > > > # For UEFI shell based apps > > > "AcceptableDependencies-UEFI_APPLICATION":[], > > > -- > > > 2.31.1.windows.1 > > > > > > > > > > > > > > > > > > > > > > > > > ^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-08-15 3:23 UTC | newest]
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2022-08-12 9:19 ` [edk2-devel] [PATCH] UefiCpuPkg/CpuPageTableLib/UnitTest: Add host based unit test Zhiguang Liu
2022-08-12 18:12 ` Michael D Kinney
2022-08-15 3:23 ` Zhiguang Liu
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