From: "Michael D Kinney" <michael.d.kinney@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"kraxel@redhat.com" <kraxel@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>,
Laszlo Ersek <lersek@redhat.com>,
"Aktas, Erdem" <erdemaktas@google.com>,
Michael Roth <michael.roth@amd.com>,
"Xu, Min M" <min.m.xu@intel.com>,
"Yao, Jiewen" <jiewen.yao@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
"Oliver Steffen" <osteffen@redhat.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>
Subject: Re: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache type #defines from ArchitecturalMsr.h
Date: Thu, 25 Jan 2024 18:42:49 +0000 [thread overview]
Message-ID: <CO1PR11MB49299126D3739B24712A3DE4D27A2@CO1PR11MB4929.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20240125082311.310203-4-kraxel@redhat.com>
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd
> Hoffmann
> Sent: Thursday, January 25, 2024 12:23 AM
> To: devel@edk2.groups.io
> Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>; Laszlo Ersek
> <lersek@redhat.com>; Aktas, Erdem <erdemaktas@google.com>; Michael Roth
> <michael.roth@amd.com>; Xu, Min M <min.m.xu@intel.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Yao, Jiewen <jiewen.yao@intel.com>; Tom Lendacky
> <thomas.lendacky@amd.com>; Oliver Steffen <osteffen@redhat.com>
> Subject: [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache
> type #defines from ArchitecturalMsr.h
>
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
> UefiCpuPkg/Include/Library/MtrrLib.h | 14 ++++++++------
> 1 file changed, 8 insertions(+), 6 deletions(-)
>
> diff --git a/UefiCpuPkg/Include/Library/MtrrLib.h
> b/UefiCpuPkg/Include/Library/MtrrLib.h
> index 86cc1aab3b8e..c7d505ac06ed 100644
> --- a/UefiCpuPkg/Include/Library/MtrrLib.h
> +++ b/UefiCpuPkg/Include/Library/MtrrLib.h
> @@ -9,6 +9,8 @@
> #ifndef _MTRR_LIB_H_
> #define _MTRR_LIB_H_
>
> +#include <Register/Intel/ArchitecturalMsr.h>
> +
> //
> // According to IA32 SDM, MTRRs number and MSR offset are always
> consistent
> // for IA32 processor family
> @@ -90,12 +92,12 @@ typedef enum {
> CacheInvalid = 7
> } MTRR_MEMORY_CACHE_TYPE;
I think the values in the above enum should also use the
MSR_IA32_MTRR_CACHE values.
>
> -#define MTRR_CACHE_UNCACHEABLE 0
> -#define MTRR_CACHE_WRITE_COMBINING 1
> -#define MTRR_CACHE_WRITE_THROUGH 4
> -#define MTRR_CACHE_WRITE_PROTECTED 5
> -#define MTRR_CACHE_WRITE_BACK 6
> -#define MTRR_CACHE_INVALID_TYPE 7
> +#define MTRR_CACHE_UNCACHEABLE MSR_IA32_MTRR_CACHE_UNCACHEABLE
> +#define MTRR_CACHE_WRITE_COMBINING
> MSR_IA32_MTRR_CACHE_WRITE_COMBINING
> +#define MTRR_CACHE_WRITE_THROUGH MSR_IA32_MTRR_CACHE_WRITE_THROUGH
> +#define MTRR_CACHE_WRITE_PROTECTED
> MSR_IA32_MTRR_CACHE_WRITE_PROTECTED
> +#define MTRR_CACHE_WRITE_BACK MSR_IA32_MTRR_CACHE_WRITE_BACK
> +#define MTRR_CACHE_INVALID_TYPE MSR_IA32_MTRR_CACHE_INVALID_TYPE
>
> typedef struct {
> UINT64 BaseAddress;
> --
> 2.43.0
>
>
>
>
>
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next prev parent reply other threads:[~2024-01-25 18:43 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-25 8:23 [edk2-devel] [PATCH v2 0/4] OvmfPkg/Sec: Setup MTRR early in the boot process Gerd Hoffmann
2024-01-25 8:23 ` [edk2-devel] [PATCH v2 1/4] " Gerd Hoffmann
2024-01-25 10:52 ` Pedro Falcato
2024-01-25 23:28 ` Laszlo Ersek
2024-01-25 8:23 ` [edk2-devel] [PATCH v2 2/4] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types Gerd Hoffmann
2024-01-25 8:23 ` [edk2-devel] [PATCH v2 3/4] UefiCpuPkg/MtrrLib.h: use cache type #defines from ArchitecturalMsr.h Gerd Hoffmann
2024-01-25 18:42 ` Michael D Kinney [this message]
2024-01-25 8:23 ` [edk2-devel] [PATCH v2 4/4] OvmfPkg/Sec: " Gerd Hoffmann
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