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From: "Michael D Kinney" <michael.d.kinney@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "kraxel@redhat.com"
	<kraxel@redhat.com>
CC: Michael Roth <michael.roth@amd.com>, Oliver Steffen <osteffen@redhat.com>,
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 Biesheuvel" <ardb+tianocore@kernel.org>, "Aktas, Erdem"
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Subject: Re: [edk2-devel] [PATCH v3 2/4] MdePkg/ArchitecturalMsr.h: add #defines for MTRR cache types
Thread-Topic: [edk2-devel] [PATCH v3 2/4] MdePkg/ArchitecturalMsr.h: add
 #defines for MTRR cache types
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Date: Tue, 30 Jan 2024 17:49:54 +0000
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Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd
> Hoffmann
> Sent: Tuesday, January 30, 2024 5:05 AM
> To: devel@edk2.groups.io
> Cc: Michael Roth <michael.roth@amd.com>; Oliver Steffen
> <osteffen@redhat.com>; Yao, Jiewen <jiewen.yao@intel.com>; Gerd Hoffmann
> <kraxel@redhat.com>; Tom Lendacky <thomas.lendacky@amd.com>; Laszlo
> Ersek <lersek@redhat.com>; Xu, Min M <min.m.xu@intel.com>; Ard
> Biesheuvel <ardb+tianocore@kernel.org>; Aktas, Erdem
> <erdemaktas@google.com>
> Subject: [edk2-devel] [PATCH v3 2/4] MdePkg/ArchitecturalMsr.h: add
> #defines for MTRR cache types
>=20
> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
> ---
>  MdePkg/Include/Register/Intel/ArchitecturalMsr.h | 7 +++++++
>  1 file changed, 7 insertions(+)
>=20
> diff --git a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> index 756e7c86ec31..2b2e34b08c8b 100644
> --- a/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> +++ b/MdePkg/Include/Register/Intel/ArchitecturalMsr.h
> @@ -2103,6 +2103,13 @@ typedef union {
>  #define MSR_IA32_MTRR_PHYSBASE9  0x00000212
>  /// @}
>=20
> +#define MSR_IA32_MTRR_CACHE_UNCACHEABLE      0
> +#define MSR_IA32_MTRR_CACHE_WRITE_COMBINING  1
> +#define MSR_IA32_MTRR_CACHE_WRITE_THROUGH    4
> +#define MSR_IA32_MTRR_CACHE_WRITE_PROTECTED  5
> +#define MSR_IA32_MTRR_CACHE_WRITE_BACK       6
> +#define MSR_IA32_MTRR_CACHE_INVALID_TYPE     7
> +
>  /**
>    MSR information returned for MSR indexes #MSR_IA32_MTRR_PHYSBASE0 to
>    #MSR_IA32_MTRR_PHYSBASE9
> --
> 2.43.0
>=20
>=20
>=20
>=20
>=20



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