From: "Michael D Kinney" <michael.d.kinney@intel.com>
To: Andrew Fish <afish@apple.com>, Michael Brown <mcb30@ipxe.org>,
"Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: edk2-devel-groups-io <devel@edk2.groups.io>,
"Loh, Tien Hock" <tien.hock.loh@intel.com>,
"thloh85@gmail.com" <thloh85@gmail.com>,
"Leif Lindholm" <leif@nuviainc.com>,
Ard Biesheuvel <ardb+tianocore@kernel.org>
Subject: Re: [edk2-devel] [PATCH V5 1/1] EmbeddedPkg: DwMmcHcDxe: Add support for Designware SDMMC driver
Date: Wed, 28 Apr 2021 00:06:49 +0000 [thread overview]
Message-ID: <CO1PR11MB4929B85143B82A9E5B2BD908D2409@CO1PR11MB4929.namprd11.prod.outlook.com> (raw)
In-Reply-To: <7A9BDBC1-4107-41A3-9FE0-FAF502E390EC@apple.com>
Michael,
Another feature the current design supports is PCI rebalancing. Meaning the PCI resource assignment can change
during the boot. The PCI Bus Driver does not support doing a rebalance today, but the PCI I/O Protocol was
designed so the UEFI Driver that consumes the PCI I/O Protocol never needs to know the current resource
assignments.
Mike
> -----Original Message-----
> From: Andrew Fish <afish@apple.com>
> Sent: Tuesday, April 27, 2021 4:46 PM
> To: Michael Brown <mcb30@ipxe.org>
> Cc: edk2-devel-groups-io <devel@edk2.groups.io>; Loh, Tien Hock <tien.hock.loh@intel.com>; Kinney, Michael D
> <michael.d.kinney@intel.com>; thloh85@gmail.com; Leif Lindholm <leif@nuviainc.com>; Ard Biesheuvel
> <ardb+tianocore@kernel.org>
> Subject: Re: [edk2-devel] [PATCH V5 1/1] EmbeddedPkg: DwMmcHcDxe: Add support for Designware SDMMC driver
>
>
>
> > On Apr 27, 2021, at 2:40 PM, Michael Brown <mcb30@ipxe.org> wrote:
> >
> > On 27/04/2021 18:31, Andrew Fish via groups.io wrote:
> >> One trick people have pulled in the past is to write a driver that produces a “fake” PCI IO Protocol. The “fake” PCI IO
> driver abstracts how the MMIO device shows up on the platform. This works well if the MMIO device is really the same IP
> block as a PCI device. This usually maps to the PCI BAR being the same thing as the magic MMIO range. The “fake” PCI IO
> Protocol also abstracts platform specific DMA rules from the generic driver.
> >
> > Slightly off-topic, but I've always been curious about this: given that the entire purpose of PCI BARs is to allow for
> the use of straightforward MMIO operations, in which standard CPU read/write instructions can be used to access device
> registers with zero overhead and no possible error conditions, why do the EFI_PCI_IO_PROTOCOL.Mem.Read (and related)
> abstractions exist? They seem to add a lot of complexity for negative benefit, and I'd be interested to know if there was
> some reason why the design was chosen.
> >
>
> Michael,
>
> Assuming physical address == non-catchable memory region is not always true. For example on Itainium you had to flip bit
> 63 in physical mode to do a non-cached transaction. There are also some high end servers that have different physical
> address ranges for PCI v.s DRAM.
>
> Basically we were paranoid about portability. That and we really don’t want #ifdef in the code for different
> architectures.
>
> Thanks,
>
> Andrew Fish
>
> > Thanks,
> >
> > Michael
next prev parent reply other threads:[~2021-04-28 0:06 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210322032439.9312-1-tien.hock.loh@intel.com>
2021-03-22 3:24 ` [PATCH V5 1/1] EmbeddedPkg: DwMmcHcDxe: Add support for Designware SDMMC driver Loh, Tien Hock
2021-03-30 4:36 ` Loh, Tien Hock
2021-04-16 5:34 ` Loh, Tien Hock
2021-04-26 17:53 ` Michael D Kinney
2021-04-27 9:08 ` Loh, Tien Hock
2021-04-27 10:27 ` Loh, Tien Hock
2021-04-27 17:31 ` [edk2-devel] " Andrew Fish
2021-04-27 19:31 ` Michael D Kinney
2021-04-28 13:03 ` Ard Biesheuvel
2021-04-28 14:58 ` Andrew Fish
2021-04-29 0:33 ` Loh, Tien Hock
2021-04-27 21:40 ` Michael Brown
2021-04-27 23:45 ` Andrew Fish
2021-04-28 0:06 ` Michael D Kinney [this message]
2021-04-28 0:52 ` Andrew Fish
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