From: "Michael D Kinney" <michael.d.kinney@intel.com>
To: "devel@edk2.groups.io" <devel@edk2.groups.io>,
"Lin, JackX" <jackx.lin@intel.com>,
"Kinney, Michael D" <michael.d.kinney@intel.com>
Cc: "Chiu, Chasel" <chasel.chiu@intel.com>,
"Desimone, Nathaniel L" <nathaniel.l.desimone@intel.com>,
"Oram, Isaac W" <isaac.w.oram@intel.com>,
"Gao, Liming" <gaoliming@byosoft.com.cn>,
"Dong, Eric" <eric.dong@intel.com>,
"Kuo, Donald" <donald.kuo@intel.com>,
"Kumar, Chandana C" <chandana.c.kumar@intel.com>
Subject: Re: [edk2-devel] [edk2-platforms: PATCH] BIOS needs to present cores in order of relative performance in MADT
Date: Thu, 17 Nov 2022 06:06:29 +0000 [thread overview]
Message-ID: <CO1PR11MB4929E8BC69F4567E9B67E9B8D2069@CO1PR11MB4929.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20221117060123.209-1-jackx.lin@intel.com>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>
Mike
> -----Original Message-----
> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of JackX Lin
> Sent: Wednesday, November 16, 2022 10:01 PM
> To: devel@edk2.groups.io
> Cc: Lin, JackX <jackx.lin@intel.com>; Lin, JackX <jackx.lin@intel.com>; Chiu, Chasel <chasel.chiu@intel.com>; Desimone,
> Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; Gao, Liming <gaoliming@byosoft.com.cn>;
> Dong, Eric <eric.dong@intel.com>; Kuo, Donald <donald.kuo@intel.com>; Kumar, Chandana C <chandana.c.kumar@intel.com>
> Subject: [edk2-devel] [edk2-platforms: PATCH] BIOS needs to present cores in order of relative performance in MADT
>
> BIOS should keep MADT ordering by big core first then small core
>
> Signed-off-by: JackX Lin <JackX.Lin@intel.com>
> Cc: Chasel Chiu <chasel.chiu@intel.com>
> Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
> Cc: Isaac Oram <isaac.w.oram@intel.com>
> Cc: Liming Gao <gaoliming@byosoft.com.cn>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Donald Kuo <Donald.Kuo@intel.com>
> Cc: Chandana C Kumar <chandana.c.kumar@intel.com>
> Cc: JackX Lin <JackX.Lin@intel.com>
> ---
> Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 111
> ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 104 insertions(+), 7 deletions(-)
>
> diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> index 6e57b638e0..894790f246 100644
> --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
> @@ -18,6 +18,7 @@ typedef struct {
> UINT32 Flags;
> UINT32 SocketNum;
> UINT32 Thread;
> + UINT8 CpuCoreType;
> } EFI_CPU_ID_ORDER_MAP;
>
> //
> @@ -131,6 +132,49 @@ AppendCpuMapTableEntry (
>
> }
>
> +/**
> + Function will go through all processors to identify Core or Atom
> + by checking Core Type and update in IsBigCore.
> +
> + @param[in] CpuApicIdOrderTable Point to a buffer which will be filled in Core type information.
> +**/
> +VOID
> +STATIC
> +EFIAPI
> +CollectCpuCoreType (
> + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
> + )
> +{
> + CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
> + UINT32 Eax;
> + UINTN ApNumber;
> + EFI_STATUS Status;
> + UINT8 CoreType;
> +
> + Status = mMpService->WhoAmI (
> + mMpService,
> + &ApNumber
> + );
> + ASSERT_EFI_ERROR (Status);
> +
> + ///
> + /// Check Hetero feature is supported
> + /// with CPUID.(EAX=7,ECX=0):EDX[15]=1
> + ///
> + AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, 0, NULL, NULL, NULL, &Edx.Uint32);
> + if (Edx.Bits.Hybrid == 1) {
> + //
> + // Check which is the running core by reading CPUID.(EAX=1AH, ECX=00H):EAX
> + //
> + AsmCpuid (CPUID_HYBRID_INFORMATION, &Eax, NULL, NULL, NULL);
> + CoreType = (UINT8) ((Eax & 0xFF000000) >> 24);
> + } else {
> + CoreType = CPUID_CORE_TYPE_INTEL_CORE;
> + }
> +
> + CpuApicIdOrderTable[ApNumber].CpuCoreType = CoreType;
> +}
> +
> /**
> Collect all processors information and create a Cpu Apic Id table.
>
> @@ -138,7 +182,7 @@ AppendCpuMapTableEntry (
> **/
> EFI_STATUS
> CreateCpuLocalApicInTable (
> - IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
> + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
> )
> {
> EFI_STATUS Status;
> @@ -146,9 +190,24 @@ CreateCpuLocalApicInTable (
> UINT32 Index;
> UINT32 CurrProcessor;
> EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr;
> + EFI_CPU_ID_ORDER_MAP *TempCpuApicIdOrderTable;
> UINT32 Socket;
>
> - Status = EFI_SUCCESS;
> + TempCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
> + if (TempCpuApicIdOrderTable == NULL) {
> + return EFI_UNSUPPORTED;
> + }
> +
> + CollectCpuCoreType (TempCpuApicIdOrderTable);
> + mMpService->StartupAllAPs (
> + mMpService, // This
> + (EFI_AP_PROCEDURE) CollectCpuCoreType, // Procedure
> + TRUE, // SingleThread
> + NULL, // WaitEvent
> + 0, // TimeoutInMicrosecsond
> + TempCpuApicIdOrderTable, // ProcedureArgument
> + NULL // FailedCpuList
> + );
>
> for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++, Index++) {
> Status = mMpService->GetProcessorInfo (
> @@ -157,9 +216,9 @@ CreateCpuLocalApicInTable (
> &ProcessorInfoBuffer
> );
>
> - CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &CpuApicIdOrderTable[Index];
> + CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Index];
> if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
> - CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
> + CpuIdMapPtr->ApicId = (UINT32) ProcessorInfoBuffer.ProcessorId;
> CpuIdMapPtr->Thread = ProcessorInfoBuffer.Location.Thread;
> CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0);
> CpuIdMapPtr->SocketNum = ProcessorInfoBuffer.Location.Package;
> @@ -184,22 +243,60 @@ CreateCpuLocalApicInTable (
> //
> DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", GetApicId ()));
>
> -
> //
> // Fill in AcpiProcessorUid.
> //
> for (Socket = 0; Socket < FixedPcdGet32 (PcdMaxCpuSocketCount); Socket++) {
> for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
> - if (CpuApicIdOrderTable[CurrProcessor].Flags && (CpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
> - CpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid = (CpuApicIdOrderTable[CurrProcessor].SocketNum <<
> mNumOfBitShift) + Index;
> + if (TempCpuApicIdOrderTable[CurrProcessor].Flags && (TempCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
> + TempCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid = (TempCpuApicIdOrderTable[CurrProcessor].SocketNum <<
> mNumOfBitShift) + Index;
> Index++;
> }
> }
> }
>
> + //
> + // Re-ordering Cpu cores information to CpuApicIdOrderTable
> + // by big core first, then small core.
> + //
> + for (Index = 0, CurrProcessor = 0; Index < mNumberOfCpus; Index++) {
> + if (TempCpuApicIdOrderTable[Index].CpuCoreType == CPUID_CORE_TYPE_INTEL_CORE) {
> + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
> + CurrProcessor++;
> + }
> + }
> +
> + for (Index = 0; Index < mNumberOfCpus; Index++) {
> + if (TempCpuApicIdOrderTable[Index].CpuCoreType == CPUID_CORE_TYPE_INTEL_ATOM) {
> + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
> + CurrProcessor++;
> + }
> + }
> +
> + //
> + // Add unknown cpu core types to the bottom of the table
> + //
> + for (Index = 0; Index < mNumberOfCpus; Index++) {
> + if ((TempCpuApicIdOrderTable[Index].CpuCoreType != CPUID_CORE_TYPE_INTEL_CORE) &&
> (TempCpuApicIdOrderTable[Index].CpuCoreType != CPUID_CORE_TYPE_INTEL_ATOM)) {
> + DEBUG ((
> + DEBUG_INFO,
> + "Unknown Cpu Core type found: Apic = 0x%x, CoreType = 0x%x\n",
> + TempCpuApicIdOrderTable[Index].ApicId,
> + TempCpuApicIdOrderTable[Index].CpuCoreType
> + ));
> +
> + CopyMem (&CpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
> + CurrProcessor++;
> + }
> + }
> +
> DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. mNumOfBitShift = %x\n", mNumOfBitShift));
> DebugDisplayReOrderTable (CpuApicIdOrderTable);
>
> + if (TempCpuApicIdOrderTable != NULL) {
> + FreePool (TempCpuApicIdOrderTable);
> + }
> +
> return Status;
> }
>
> --
> 2.32.0.windows.2
>
>
>
>
>
next prev parent reply other threads:[~2022-11-17 6:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-17 6:01 [edk2-platforms: PATCH] BIOS needs to present cores in order of relative performance in MADT JackX Lin
2022-11-17 6:06 ` Michael D Kinney [this message]
2022-11-17 14:09 ` [edk2-devel] " Pedro Falcato
2022-11-18 8:34 ` JackX Lin
2022-11-18 19:11 ` Pedro Falcato
2022-11-22 3:35 ` Ni, Ray
-- strict thread matches above, loose matches on Subject: below --
2022-11-16 6:29 JackX Lin
2022-11-17 3:45 ` [edk2-devel] " Michael D Kinney
2022-11-17 3:54 ` JackX Lin
2022-11-16 2:52 JackX Lin
2022-11-16 3:50 ` [edk2-devel] " Michael D Kinney
2022-11-16 3:59 ` JackX Lin
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