From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail02.groups.io (mail02.groups.io [66.175.222.108]) by spool.mail.gandi.net (Postfix) with ESMTPS id 32F36D800FD for ; Tue, 7 Nov 2023 03:31:51 +0000 (UTC) DKIM-Signature: a=rsa-sha256; bh=XRXyInt322dWweEQ7GTglx64c9mu7OrB8GqMlljMKfE=; c=relaxed/simple; d=groups.io; h=ARC-Seal:ARC-Message-Signature:ARC-Authentication-Results:From:To:CC:Subject:Thread-Topic:Thread-Index:Date:Message-ID:References:In-Reply-To:Accept-Language:MIME-Version:Precedence:List-Subscribe:List-Help:Sender:List-Id:Mailing-List:Delivered-To:Reply-To:List-Unsubscribe-Post:List-Unsubscribe:Content-Language:Content-Type:Content-Transfer-Encoding; s=20140610; t=1699327909; v=1; b=rnYHZzI5Pd9Iosp7A6woW8EWq70P9FiydepZINFwF+0sx+za/2eudMbOJJLOb5NkhJWxa0SO J19qzNwSEwQXzEsnlxzJKrD64dyFflOrih895MRXwjcQmuDCuyMUpGV0kOy+EUAkD9wJlyBLVNh WE5Z/8ZWr1/ESLkA4t1zUpU4= X-Received: by 127.0.0.2 with SMTP id 55FFYY7687511xhZw3AvnV1j; Mon, 06 Nov 2023 19:31:49 -0800 X-Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web10.3102.1699327909358373650 for ; Mon, 06 Nov 2023 19:31:49 -0800 X-IronPort-AV: E=McAfee;i="6600,9927,10886"; a="420533247" X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="420533247" X-Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Nov 2023 19:31:49 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,282,1694761200"; d="scan'208";a="3836402" X-Received: from fmsmsx602.amr.corp.intel.com ([10.18.126.82]) by fmviesa002.fm.intel.com with ESMTP/TLS/AES256-GCM-SHA384; 06 Nov 2023 19:31:49 -0800 X-Received: from fmsmsx611.amr.corp.intel.com (10.18.126.91) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 6 Nov 2023 19:31:48 -0800 X-Received: from fmsmsx602.amr.corp.intel.com (10.18.126.82) by fmsmsx611.amr.corp.intel.com (10.18.126.91) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 6 Nov 2023 19:31:48 -0800 X-Received: from fmsedg601.ED.cps.intel.com (10.1.192.135) by fmsmsx602.amr.corp.intel.com (10.18.126.82) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34 via Frontend Transport; Mon, 6 Nov 2023 19:31:48 -0800 X-Received: from NAM12-MW2-obe.outbound.protection.outlook.com (104.47.66.41) by edgegateway.intel.com (192.55.55.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.34; Mon, 6 Nov 2023 19:31:47 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=jX/Y57YDnd8a30Je0t50hKGypgh02J7dhm18KAJzKLojxu07HtNsG4zSFdVDU0NaeU6D/PX+HWgWaVggDcEgEBf1ym8lGAhYggWF98U2fcHyqUQdSyV3IIE1wIhddW35AqNwa0DmrzDoe3hm70qJQE8DpUk/XMNSyUiZIroQk5ZGD+3Hp05xEx9rI91zgq0812LBf7tMjZ0M2HZB+3HQHUiDFlnqt0PlJdJOLymZMP9d5p89CO9wXKAEWyKiBLSmaX5QQHyClrWQFLiU/5k6sMCDccU5x4X4p+a2hCKcpVhwEmZd0kP/xGzn+3x/C2imhO0DPN+PNQ380GocSPhQ0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=xHfhwCfcL5LynijVDuULpf52+EfSf0nQgGpBl3ptnpQ=; b=fjhYsEglopXHQumWZGDRwWx0QeI9ZkQNSOn8YRbNmmHirIy3p1ZpN7JkKRagCiLtw4cTtSqkqVWOtTUzlPlFjhO8dOABofz1kbw0yZdKq+li5dQD6HFS/Lx+AaNT0lvNCAcS+LO+pJUT5MdB4nBGZCysUx+FEmCw1vYctioYEPt+SgRhUktPoxixEJFkG8t0e1MBq7sd3y33jPYTo1i0kPKlE1U4mInHSNp7zQltnrx83DLWWDxmtBw70cpgJ0yEtwaJcbcdpWEdNdvqrdAeyjTawtT3pocAWy7fPHCZHowo/c6ijr1AGubZAErcQ8oZPfQXGWlOwso9W5jHZE75oA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none X-Received: from CO1PR11MB4929.namprd11.prod.outlook.com (2603:10b6:303:6d::19) by DM8PR11MB5606.namprd11.prod.outlook.com (2603:10b6:8:3c::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6954.28; Tue, 7 Nov 2023 03:31:37 +0000 X-Received: from CO1PR11MB4929.namprd11.prod.outlook.com ([fe80::a2a0:3c59:8d07:7f]) by CO1PR11MB4929.namprd11.prod.outlook.com ([fe80::a2a0:3c59:8d07:7f%6]) with mapi id 15.20.6954.028; Tue, 7 Nov 2023 03:31:36 +0000 From: "Michael D Kinney" To: Chao Li , "devel@edk2.groups.io" CC: "Gao, Liming" , "Liu, Zhiguang" , "Kinney, Michael D" Subject: Re: [edk2-devel] [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function Thread-Topic: [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function Thread-Index: AQHaEGEwtUnoBAWTiEmYO11gqS8Cb7BuNQoQ Date: Tue, 7 Nov 2023 03:31:36 +0000 Message-ID: References: <20231106032521.2251143-1-lichao@loongson.cn> <20231106032709.2271132-1-lichao@loongson.cn> In-Reply-To: <20231106032709.2271132-1-lichao@loongson.cn> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CO1PR11MB4929:EE_|DM8PR11MB5606:EE_ x-ms-office365-filtering-correlation-id: cb3a5943-57cd-40d5-629b-08dbdf420c40 x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam-message-info: 8F0YUtofeJ157grksBguAI0Tt7AChE4qaGxqOSK3uZ30SIEe93zatjckmlSdvlxiGGT4qwpVjuG1uN20bAkrdVPGcyN/yPvVHq4l9wmAulp0WHiNnOmVv/sljd8xsu9pcP3GcTrr0SA8naEzv2jUAvSVTfDXRsTeTtB4oJolLp6kcNfxpLBOSN4xct/6lBnrYJ/DQ8Zqe4ZXDnrLvkRFznOCmru59hdqU9BrrM0UrXFibWBncr/2gV+UnbpNjgsTLpTJlpvILKisoZCqcpWbo8Xtppv9Rjo5m9xjWq+AKGmnMf4DlXPiwfzqcgatyv10OrSQ/YhnLM4A1Wd1Vto1oV6aEsirwq0LL1o4c/bKycdoANw3JTsA6CSqcl/dq/msMP519Y6wtU4K/yr/hIFbIelHz+4hQTFqKQd/PH2VZFy7p0vcS3uUS1SGcE1W4MgXfSliQbSF1soIZryYAZm56htTlecNdAh2eOd2YnlnfuLeiAB1ihACWMvQU2dVVjvFb1AoXisqj/KnDqUUNb89i6DwMiL+uqVXpnCTNiDGKltClLXd1bt4V3TixFL37aikkNZ18bo8TgRq4/6KRoy98Ls4oUCYp8gKKG2BnurZt6lrtMHcR67uWlzzCToBdNl5RVVFRbJ8nDOoUDSKxNRh1A== x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?aq3kedu45UK77ljRD8EA+4jLoMuIIcjjfFEqp9dtIkF5hlYVebb5k3t5A2eA?= =?us-ascii?Q?+KrZuPVJDHHUfiqvKLsPW5+WhKAw82Bnnuufn+Pq6XQXo6LUyzn8coSXAf5A?= =?us-ascii?Q?oxZA2k5Tt4SOkL2YXS+94OgTqU/xoHbOlrP/O+dJ/chnd616Yrfz1NGBcKku?= =?us-ascii?Q?lRwNEBJ8YZby4GgxwBhNYVbSKX07rwA8RBZqdGgOB6XQfAsfuvUFQvLFxA7/?= =?us-ascii?Q?pgsBVSeTn8RHtvCEL9zBeefbRWPMOTL+cu0ZA5d7K10pZEVBeaOuu9IlcnpZ?= =?us-ascii?Q?TyWuhSUBZQUWkenwmAmVEJ4QVfUmwK2VamWzByVYCbBCRyTMKZum2D5FqCdG?= =?us-ascii?Q?oOP3wmWsGi5dWoQXV+dbmRF59HUeNBeszE59Z2qsjW+dDbCqYFn8ni40wUPe?= =?us-ascii?Q?tAvn2W0iw08SDkO1mbtqAKlVbjeh1dxqzj97p1jisaKC9hE+jhxHESWE5PBS?= =?us-ascii?Q?DpZ9CK4OTvrpG17JF+YW3rM6QHsdvvyuorDkH4vOBKh5L8abSRTrhK+IEoXj?= =?us-ascii?Q?A2dKrOmJ2JfmtUiVsAdr2WnpmiqDpIO7WpPcVmN+M5fApuKl2AAvbpbxbTII?= =?us-ascii?Q?6Rr9AI3ljSgvgL+m0fflqfqai9Wu++uTWB5dVpTUfyTOi0pMUJHtYddwYTfH?= =?us-ascii?Q?rq+OdKS6THTQzQy5tsbSYkjpt8nVRbOGJYPsB8CZTZThK+VtAWe7XxMKAIok?= =?us-ascii?Q?pWdp1LDWkTcSlenpsQ9JX5EgffxzQBff2kD9x9zc3lKXPRvMBthhpJJf3uv3?= =?us-ascii?Q?iKyOeNiggT2umh57hBUF6noj19ouf9UypvrQu5B6/X/8B5cAsPPMT1qwlQfR?= =?us-ascii?Q?9MpynPxYSun41+yPswy7cFwnjtfjkmQYrXCKLBQHrBLxHxIC9M6zVOhgRVKT?= =?us-ascii?Q?bZmQB205FjZWxX6VFZvgiRvaNX4CHGyYnI58fiaZVhsUwvKvvsVy5tovqcJW?= =?us-ascii?Q?OE4SblwwnXJFewrFWz7Wnaztl+x+apQj6IQnXkNwaLUrYzAP+R4Ejw4fZao5?= =?us-ascii?Q?TH7VRoQWoAjBMj1llayALzw1LgfN9R3SYZ9tJkqXzAQYuXzfdiGi5B//xlG6?= =?us-ascii?Q?p94XaOPUPRFRUTi5OY39YMVUmrbmr/DfwjEb8dLfSsoQtJLpKOcNjquxMOoj?= =?us-ascii?Q?7vrrdTQ7o8IKS3kwWDI/xre2cKgR6h0OFqiouHiXLZFXtw74PoGNI1pMKCnQ?= =?us-ascii?Q?MmNv0mvH4x3xd39w8v67p6E/meQmERBaSPBx/pU7S9shZj1ok/VOQDwAMGgh?= =?us-ascii?Q?N0QGUHj/XE5WKc3nSKeGQIUKzFeMfEIT8TCfjDHju9A1OiQ173T0ap8HsoiG?= =?us-ascii?Q?iSeciA4UTf0dzl1ZmT6iqfn6Px0pyBWqh5PhGRyCAh6EFvc8/KYMXY2wjeOA?= =?us-ascii?Q?K8NEy1EO4o9pqe9Vsb84+eS9arqlC21JIBXA53526+4ASnrHZqdqqs7JQGiV?= =?us-ascii?Q?6L4ojdkEzWn3IqB6llh/qSj/NFO3zbsJOfQwCbfINBT4qCqJWM0RMrRMRGAl?= =?us-ascii?Q?MeGzSS/h9QfRWtoZRPn3E8Z/4/rkaZ6NPjXctVJ5emg5HCq9LSSO51G2pZ4W?= =?us-ascii?Q?O/t5d3Vps9b4fJ6/MVuoDSck7itZWzlJ8c3EDLr7ttdYPHCRmNZ/PYuXNLRj?= =?us-ascii?Q?2Q=3D=3D?= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: CO1PR11MB4929.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: cb3a5943-57cd-40d5-629b-08dbdf420c40 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Nov 2023 03:31:36.9379 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 32ZhWWuaIb4e1tue3/95sQmUWlgRL2bAeRoov5Gat0WGJpixfnfHXehSyDjqMCKqYLVSK8FlG9HBqC8ucnrHIsf5UmBuknttXgLfMzaQqpg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM8PR11MB5606 X-OriginatorOrg: intel.com Precedence: Bulk List-Subscribe: List-Help: Sender: devel@edk2.groups.io List-Id: Mailing-List: list devel@edk2.groups.io; contact devel+owner@edk2.groups.io Reply-To: devel@edk2.groups.io,michael.d.kinney@intel.com List-Unsubscribe-Post: List-Unsubscribe=One-Click List-Unsubscribe: X-Gm-Message-State: mqqQiKD91uwF1amCOImVziAvx7686176AA= Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable X-GND-Status: LEGIT Authentication-Results: spool.mail.gandi.net; dkim=pass header.d=groups.io header.s=20140610 header.b=rnYHZzI5; spf=pass (spool.mail.gandi.net: domain of bounce@groups.io designates 66.175.222.108 as permitted sender) smtp.mailfrom=bounce@groups.io; dmarc=fail reason="SPF not aligned (relaxed), DKIM not aligned (relaxed)" header.from=intel.com (policy=none); arc=reject ("signature check failed: fail, {[1] = sig:microsoft.com:reject}") Acked-by: Michael D Kinney > -----Original Message----- > From: Chao Li > Sent: Sunday, November 5, 2023 7:27 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D ; Gao, Liming > ; Liu, Zhiguang > Subject: [PATCH v2 05/30] MdePkg: Add LoongArch Cpucfg function >=20 > Add LoongArch AsmCpucfg function and Cpucfg definitions. >=20 > Also added Include/Register/LoongArch64/Cpucfg.h to IgnoreFiles of > EccCheck. >=20 > BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4584 >=20 > Cc: Michael D Kinney > Cc: Liming Gao > Cc: Zhiguang Liu > Signed-off-by: Chao Li > --- > MdePkg/Include/Library/BaseLib.h | 12 + > MdePkg/Include/Register/LoongArch64/Cpucfg.h | 565 > +++++++++++++++++++ > MdePkg/Library/BaseLib/BaseLib.inf | 1 + > MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S | 26 + > MdePkg/MdePkg.ci.yaml | 3 +- > 5 files changed, 606 insertions(+), 1 deletion(-) > create mode 100644 MdePkg/Include/Register/LoongArch64/Cpucfg.h > create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S >=20 > diff --git a/MdePkg/Include/Library/BaseLib.h > b/MdePkg/Include/Library/BaseLib.h > index 93a014cd49..3adf4d0042 100644 > --- a/MdePkg/Include/Library/BaseLib.h > +++ b/MdePkg/Include/Library/BaseLib.h > @@ -269,6 +269,18 @@ DisableLocalInterrupts ( > IN UINT16 > ); >=20 > +/** > + Read CPUCFG register. > + > + @param Index Specifies the register number of the CPUCFG to read > the data. > + @param Data A pointer to the variable used to store the CPUCFG > register value. > +**/ > +VOID > +AsmCpucfg ( > + IN UINT32 Index, > + OUT UINT32 *Data > + ); > + > #endif // defined (MDE_CPU_LOONGARCH64) >=20 > // > diff --git a/MdePkg/Include/Register/LoongArch64/Cpucfg.h > b/MdePkg/Include/Register/LoongArch64/Cpucfg.h > new file mode 100644 > index 0000000000..841885dc70 > --- /dev/null > +++ b/MdePkg/Include/Register/LoongArch64/Cpucfg.h > @@ -0,0 +1,565 @@ > +/** @file > + CPUCFG definitions. > + > + Copyright (c) 2023, Loongson Technology Corporation Limited. All > rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > +**/ > + > +#ifndef CPUCFG_H_ > +#define CPUCFG_H_ > + > +/** > + CPUCFG REG0 Information > + > + @code > + CPUCFG_REG0_INFO_DATA > + **/ > +#define CPUCFG_REG0_INFO 0x0 > + > +/** > + CPUCFG REG0 Information returned data. > + #CPUCFG_REG0_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 31:0] Processor Identity. > + /// > + UINT32 PRID : 32; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG0_INFO_DATA; > + > +/** > + CPUCFG REG1 Information > + > + @code > + CPUCFG_REG1_INFO_DATA > + **/ > +#define CPUCFG_REG1_INFO 0x1 > + > +/** > + CPUCFG REG1 Information returned data. > + #CPUCFG_REG1_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 1:0] Architecture: > + /// 2'b00 indicates the implementation of simplified > LoongAarch32; > + /// 2'b01 indicates the implementation of LoongAarch32; > + /// 2'b10 indicates the implementation of LoongAarch64; > + /// 2'b11 reserved; > + /// > + UINT32 ARCH : 2; > + /// > + /// [Bit 2] Paging mapping mode. A value of 1 indicates the > processor MMU supports > + /// page mapping mode. > + /// > + UINT32 PGMMU : 1; > + /// > + /// [Bit 3] A value of 1 indicates the processor supports the > IOCSR instruction. > + /// > + UINT32 IOCSR : 1; > + /// > + /// [Bit 11:4] Physical address bits. The supported physical > address bits PALEN value > + /// minus 1. > + /// > + UINT32 PALEN : 8; > + /// > + /// [Bit 19:12] Virtual address bits. The supported virtual > address bits VALEN value > + /// minus 1. > + /// > + UINT32 VALEN : 8; > + /// > + /// [Bit 20] Non-aligned Memory Access. A value of 1 indicates > the processor supports > + /// non-aligned memory access. > + /// > + UINT32 UAL : 1; > + /// > + /// [Bit 21] Page Read Inhibit. A value of 1 indicates the > processor supports page > + /// attribute of "Read Inhibit". > + /// > + UINT32 RI : 1; > + /// > + /// [Bit 22] Page Execution Protection. A value of 1 indicates > the processor supports > + /// page attribute of "Execution Protection". > + /// > + UINT32 EP : 1; > + /// > + /// [Bit 23] A value of 1 indicates the processor supports for > page attributes of RPLV. > + /// > + UINT32 RPLV : 1; > + /// > + /// [Bit 24] Huge Page. A value of 1 indicates the processor > supports page attribute > + /// of huge page. > + /// > + UINT32 HP : 1; > + /// > + /// [Bit 25] A value of 1 indicates that the string of processor > product information > + /// is recorded at address 0 of the IOCSR access space. > + /// > + UINT32 IOCSR_BRD : 1; > + /// > + /// [Bit 26] A value of 1 indicates that the external interrupt > uses the message > + /// interrupt mode, otherwise it is the level interrupt line > mode. > + /// > + UINT32 MSG_INT : 1; > + /// > + /// [Bit 31:27] Reserved. > + /// > + UINT32 Reserved : 5; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG1_INFO_DATA; > + > +/** > + CPUCFG REG2 Information > + > + @code > + CPUCFG_REG2_INFO_DATA > + **/ > +#define CPUCFG_REG2_INFO 0x2 > + > +/** > + CPUCFG REG2 Information returned data. > + #CPUCFG_REG2_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 0] Basic Floating-Point. A value of 1 indicates the > processor supports basic > + /// floating-point instructions. > + /// > + UINT32 FP : 1; > + /// > + /// [Bit 1] Sigle-Precision. A value of 1 indicates the processor > supports sigle-precision > + /// floating-point numbers. > + /// > + UINT32 FP_SP : 1; > + /// > + /// [Bit 2] Double-Precision. A value of 1 indicates the > processor supports double-precision > + /// floating-point numbers. > + /// > + UINT32 FP_DP : 1; > + /// > + /// [Bit 5:3] The version number of the floating-point arithmetic > standard. 1 is the initial > + /// version number, indicating that it is compatible with the > IEEE 754-2008 standard. > + /// > + UINT32 FP_ver : 3; > + /// > + /// [Bit 6] 128-bit Vector Extension. A value of 1 indicates the > processor supports 128-bit > + /// vector extension. > + /// > + UINT32 LSX : 1; > + /// > + /// [Bit 7] 256-bit Vector Extension. A value of 1 indicates the > processor supports 256-bit > + /// vector extension. > + /// > + UINT32 LASX : 1; > + /// > + /// [Bit 8] Complex Vector Operation Instructions. A value of 1 > indicates the processor supports > + /// complex vector operation instructions. > + /// > + UINT32 COMPLEX : 1; > + /// > + /// [Bit 9] Encryption And Decryption Vector Instructions. A > value of 1 indicates the processor > + /// supports encryption and decryption vector instructions. > + /// > + UINT32 CRYPTO : 1; > + /// > + /// [Bit 10] Virtualization Expansion. A value of 1 indicates the > processor supports > + /// virtualization expansion. > + /// > + UINT32 LVZ : 1; > + /// > + /// [Bit 13:11] The version number of the virtualization hardware > acceleration specification. > + /// 1 is the initial version number. > + /// > + UINT32 LVZ_ver : 3; > + /// > + /// [Bit 14] Constant Frequency Counter And Timer. A value of 1 > indicates the processor supports > + /// constant frequency counter and timer. > + /// > + UINT32 LLFTP : 1; > + /// > + /// [Bit 17:15] Constant frequency counter and timer version > number. 1 is the initial version. > + /// > + UINT32 LLTP_ver : 3; > + /// > + /// [Bit 18] X86 Binary Translation Extension. A value of 1 > indicates the processor supports > + /// X86 binary translation extension. > + /// > + UINT32 LBT_X86 : 1; > + /// > + /// [Bit 19] ARM Binary Translation Extension. A value of 1 > indicates the processor supports > + /// ARM binary translation extension. > + /// > + UINT32 LBT_ARM : 1; > + /// > + /// [Bit 20] MIPS Binary Translation Extension. A value of 1 > indicates the processor supports > + /// MIPS binary translation extension. > + /// > + UINT32 LBT_MIPS : 1; > + /// > + /// [Bit 21] Software Page Table Walking Instruction. A value of > 1 indicates the processor > + /// supports software page table walking instruction. > + /// > + UINT32 LSPW : 1; > + /// > + /// [Bit 22] Atomic Memory Access Instruction. A value of 1 > indicates the processor supports > + /// AM* atomic memory access instruction. > + /// > + UINT32 LAM : 1; > + /// > + /// [Bit 31:23] Reserved. > + /// > + UINT32 Reserved : 9; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG2_INFO_DATA; > + > +/** > + CPUCFG REG3 Information > + > + @code > + CPUCFG_REG3_INFO_DATA > + **/ > +#define CPUCFG_REG3_INFO 0x3 > + > +/** > + CPUCFG REG3 Information returned data. > + #CPUCFG_REG3_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 0] Hardware Cache Coherent DMA. A value of 1 indicates > the processor supports > + /// hardware cache coherent DMA. > + /// > + UINT32 CCDMA : 1; > + /// > + /// [Bit 1] Store Fill Buffer. A value of 1 indicates the > processor supports store fill > + /// buffer (SFB). > + /// > + UINT32 SFB : 1; > + /// > + /// [Bit 2] Uncache Accelerate. A value of 1 indicates the > processor supports uncache > + /// accelerate. > + /// > + UINT32 UCACC : 1; > + /// > + /// [Bit 3] A value of 1 indicates the processor supports LL > instruction to fetch exclusive > + /// block function. > + /// > + UINT32 LLEXC : 1; > + /// > + /// [Bit 4] A value of 1 indicates the processor supports random > delay function after SC > + /// instruction. > + /// > + UINT32 SCDLY : 1; > + /// > + /// [Bit 5] A value of 1 indicates the processor supports LL > automatic with dbar function. > + /// > + UINT32 LLDBAR : 1; > + /// > + /// [Bit 6] A value of 1 indicates the processor supports the > hardware maintains the > + /// consistency between ITLB and TLB. > + /// > + UINT32 ITLBT : 1; > + /// > + /// [Bit 7] A value of 1 indicates the processor supports the > hardware maintains the data > + /// consistency between ICache and DCache in one processor core. > + /// > + UINT32 ICACHET : 1; > + /// > + /// [Bit 10:8] The maximum number of directory levels supported > by the page walk instruction. > + /// > + UINT32 SPW_LVL : 3; > + /// > + /// [Bit 11] A value of 1 indicates the processor supports the > page walk instruction fills > + /// the TLB in half when it encounters a large page. > + /// > + UINT32 SPW_HP_HF : 1; > + /// > + /// [Bit 12] Virtual Address Range. A value of 1 indicates the > processor supports the software > + /// configuration can be used to shorten the virtual address > range. > + /// > + UINT32 RVA : 1; > + /// > + /// [Bit 16:13] The maximum configurable virtual address is > shortened by -1. > + /// > + UINT32 RVAMAX_1 : 4; > + /// > + /// [Bit 31:17] Reserved. > + /// > + UINT32 Reserved : 15; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG3_INFO_DATA; > + > +/** > + CPUCFG REG4 Information > + > + @code > + CPUCFG_REG4_INFO_DATA > + **/ > +#define CPUCFG_REG4_INFO 0x4 > + > +/** > + CPUCFG REG4 Information returned data. > + #CPUCFG_REG4_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 31:0] Constant frequency timer and the crystal frequency > corresponding to the clock > + /// used by the timer. > + /// > + UINT32 CC_FREQ : 32; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG4_INFO_DATA; > + > +/** > + CPUCFG REG5 Information > + > + @code > + CPUCFG_REG5_INFO_DATA > + **/ > +#define CPUCFG_REG5_INFO 0x5 > + > +/** > + CPUCFG REG5 Information returned data. > + #CPUCFG_REG5_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 15:0] Constant frequency timer and the corresponding > multiplication factor of the > + /// clock used by the timer. > + /// > + UINT32 CC_MUL : 16; > + /// > + /// [Bit 31:16] Constant frequency timer and the division > coefficient corresponding to the > + /// clock used by the timer > + /// > + UINT32 CC_DIV : 16; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG5_INFO_DATA; > + > +/** > + CPUCFG REG6 Information > + > + @code > + CPUCFG_REG6_INFO_DATA > + **/ > +#define CPUCFG_REG6_INFO 0x6 > + > +/** > + CPUCFG REG6 Information returned data. > + #CPUCFG_REG6_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 0] Performance Counter. A value of 1 indicates the > processor supports performance > + /// counter. > + /// > + UINT32 PMP : 1; > + /// > + /// [Bit 3:1] In the performance monitor, the architecture > defines the version number of the > + /// event, and 1 is the initial version > + /// > + UINT32 PMVER : 3; > + /// > + /// [Bit 7:4] Number of performance monitors minus 1. > + /// > + UINT32 PMNUM : 4; > + /// > + /// [Bit 13:8] Number of bits of a performance monitor minus 1. > + /// > + UINT32 PMBITS : 6; > + /// > + /// [Bit 14] A value of 1 indicates the processor supports > reading performance counter in user mode. > + /// > + UINT32 UPM : 1; > + /// > + /// [Bit 31:15] Reserved. > + /// > + UINT32 Reserved : 17; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG6_INFO_DATA; > + > +/** > + CPUCFG REG16 Information > + > + @code > + CPUCFG_REG16_INFO_DATA > + **/ > +#define CPUCFG_REG16_INFO 0x10 > + > +/** > + CPUCFG REG16 Information returned data. > + #CPUCFG_REG16_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 0] A value of 1 indicates the processor has a first- > level instruction cache > + /// or a first-level unified cache > + /// > + UINT32 L1_IU_Present : 1; > + /// > + /// [Bit 1] A value of 1 indicates that the cache shown by L1 > IU_Present is the > + /// unified cache. > + /// > + UINT32 L1_IU_Unify : 1; > + /// > + /// [Bit 2] A value of 1 indicates the processor has a first- > level data cache. > + /// > + UINT32 L1_D_Present : 1; > + /// > + /// [Bit 3] A value of 1 indicates the processor has a second- > level instruction cache > + /// or a second-level unified cache. > + /// > + UINT32 L2_IU_Present : 1; > + /// > + /// [Bit 4] A value of 1 indicates that the cache shown by L2 > IU_Present is the > + /// unified cache. > + /// > + UINT32 L2_IU_Unify : 1; > + /// > + /// [Bit 5] A value of 1 indicates that the cache shown by L2 > IU_Present is private > + /// to each core. > + /// > + UINT32 L2_IU_Private : 1; > + /// > + /// [Bit 6] A value of 1 indicates that the cache shown by L2 > IU_Present has an inclusive > + /// relationship to the lower levels (L1). > + /// > + UINT32 L2_IU_Inclusive : 1; > + /// > + /// [Bit 7] A value of 1 indicates the processor has a second- > level data cache. > + /// > + UINT32 L2_D_Present : 1; > + /// > + /// [Bit 8] A value of 1 indicates that the second-level data > cache is private to each core. > + /// > + UINT32 L2_D_Private : 1; > + /// > + /// [Bit 9] A value of 1 indicates that the second-level data > cache has a containment > + /// relationship to the lower level (L1). > + /// > + UINT32 L2_D_Inclusive : 1; > + /// > + /// [Bit 10] A value of 1 indicates the processor has a three- > level instruction cache > + /// or a second-level unified Cache. > + /// > + UINT32 L3_IU_Present : 1; > + /// > + /// [Bit 11] A value of 1 indicates that the cache shown by L3 > IU_Present is the > + /// unified cache. > + /// > + UINT32 L3_IU_Unify : 1; > + /// > + /// [Bit 12] A value of 1 indicates that the cache shown by L3 > IU_Present is private > + /// to each core. > + /// > + UINT32 L3_IU_Private : 1; > + /// > + /// [Bit 13] A value of 1 indicates that the cache shown by L3 > IU_Present has an inclusive > + /// relationship to the lower levels (L1 and L2). > + /// > + UINT32 L3_IU_Inclusive : 1; > + /// > + /// [Bit 14] A value of 1 indicates the processor has a three- > level data cache. > + /// > + UINT32 L3_D_Present : 1; > + /// > + /// [Bit 15] A value of 1 indicates that the three-level data > cache is private to each core. > + /// > + UINT32 L3_D_Private : 1; > + /// > + /// [Bit 16] A value of 1 indicates that the three-level data > cache has a containment > + /// relationship to the lower level (L1 and L2). > + /// > + UINT32 L3_D_Inclusive : 1; > + /// > + /// [Bit 31:17] Reserved. > + /// > + UINT32 Reserved : 15; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_REG16_INFO_DATA; > + > +/** > + CPUCFG REG17, REG18, REG19 and REG20 Information > + > + @code > + CPUCFG_CACHE_INFO_DATA > + **/ > +#define CPUCFG_REG17_INFO 0x11 /// L1 unified cache. > +#define CPUCFG_REG18_INFO 0x12 /// L1 data cache. > +#define CPUCFG_REG19_INFO 0x13 /// L2 unified cache. > +#define CPUCFG_REG20_INFO 0x14 /// L3 unified cache. > + > +/** > + CPUCFG CACHE Information returned data. > + #CPUCFG_REG17_INFO > + #CPUCFG_REG18_INFO > + #CPUCFG_REG19_INFO > + #CPUCFG_REG20_INFO > + **/ > +typedef union { > + struct { > + /// > + /// [Bit 15:0] Number of channels minus 1. > + /// > + UINT32 Way_1 : 16; > + /// > + /// [Bit 23:16] Log2 (number of cache rows per channel). > + /// > + UINT32 Index_log2 : 8; > + /// > + /// [Bit 30:24] Log2 (cache row bytes). > + /// > + UINT32 Linesize_log2 : 7; > + /// > + /// [Bit 31] Reserved. > + /// > + UINT32 Reserved : 1; > + } Bits; > + /// > + /// All bit fields as a 32-bit value > + /// > + UINT32 Uint32; > +} CPUCFG_CACHE_INFO_DATA; > +#endif > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > b/MdePkg/Library/BaseLib/BaseLib.inf > index a18fe5efb4..a427aa9359 100644 > --- a/MdePkg/Library/BaseLib/BaseLib.inf > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > @@ -420,6 +420,7 @@ > LoongArch64/SetJumpLongJump.S | GCC > LoongArch64/SwitchStack.S | GCC > LoongArch64/ExceptionBase.S | GCC > + LoongArch64/Cpucfg.S | GCC >=20 > [Packages] > MdePkg/MdePkg.dec > diff --git a/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S > b/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S > new file mode 100644 > index 0000000000..7ed49146b4 > --- /dev/null > +++ b/MdePkg/Library/BaseLib/LoongArch64/Cpucfg.S > @@ -0,0 +1,26 @@ > +#-------------------------------------------------------------------- > ---------- > +# > +# AsmCpucfg for LoongArch > +# > +# Copyright (c) 2023, Loongson Technology Corporation Limited. All > rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#-------------------------------------------------------------------- > ---------- > + > +ASM_GLOBAL ASM_PFX(AsmCpucfg) > + > +#/** > +# Read CPUCFG register. > +# > +# @param a0 Specifies the register number of the CPUCFG to read > the data. > +# @param a1 Pointer to the variable used to store the CPUCFG > register value. > +# > +#**/ > + > +ASM_PFX(AsmCpucfg): > + cpucfg $t0, $a0 > + stptr.d $t0, $a1, 0 > + > + jirl $zero, $ra, 0 > + .end > diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml > index 1d3d8327b1..f2d81af080 100644 > --- a/MdePkg/MdePkg.ci.yaml > +++ b/MdePkg/MdePkg.ci.yaml > @@ -80,7 +80,8 @@ > "Include/Register/Amd/SmramSaveStateMap.h", >=20 > "Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.c", >=20 > "Test/UnitTest/Library/DevicePathLib/TestDevicePathLib.h", > - > "Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c > " > + > "Test/UnitTest/Library/DevicePathLib/TestDevicePathStringConversions.c > ", > + "Include/Register/LoongArch64/Cpucfg.h" > ] > }, > ## options defined ci/Plugin/CompilerPlugin > -- > 2.27.0 -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#110791): https://edk2.groups.io/g/devel/message/110791 Mute This Topic: https://groups.io/mt/102413851/7686176 Group Owner: devel+owner@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/leave/12367111/7686176/19134562= 12/xyzzy [rebecca@openfw.io] -=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-=3D-