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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Luo, Heng > Sent: Monday, January 4, 2021 3:00 PM > To: devel@edk2.groups.io > Cc: Ni, Ray ; Wu, Hao A > Subject: [Patch V3 2/2] MdeModulePkg/Bus/Pci/PciBusDxe: Support PCIe > Resizable BAR Capability >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D313 >=20 > Add PcdPcieResizableBarSupport to enable/disable PCIe Resizable > BAR Capability fearture. > Program the Resizable BAR Register if the device suports PCIe Resizable > BAR Capability and PcdPcieResizableBarSupport is TRUE. >=20 > Cc: Ray Ni > Cc: Hao A Wu > Signed-off-by: Heng Luo > --- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h | 4 +++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf | 3 ++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 27 > ++++++++++++++++++++++++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h | 12 > +++++++++++- > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c | 185 > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ > +++++++++++++++++++++++++++++++++++++++++++-------------- > MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h | 22 > +++++++++++++++++++++- > MdeModulePkg/MdeModulePkg.dec | 8 +++++++- > 7 files changed, 241 insertions(+), 20 deletions(-) >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > index d4113993c8..a619a68526 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h > @@ -1,7 +1,7 @@ > /** @file >=20 > Header files and data structures needed by PCI Bus module. >=20 >=20 >=20 > -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -280,6 +280,8 @@ struct _PCI_IO_DEVICE { > // This field is used to support this case. >=20 > // >=20 > UINT16 BridgeIoAlignment; >=20 > + UINT32 ResizableBarOffset; >=20 > + UINT32 ResizableBarNumber; >=20 > }; >=20 >=20 >=20 > #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \ >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > index 9284998f36..e317169d9c 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > @@ -2,7 +2,7 @@ > # The PCI bus driver will probe all PCI devices and allocate MMIO and I= O > space for these devices. >=20 > # Please use PCD feature flag PcdPciBusHotplugDeviceSupport to enable h= ot > plug supporting. >=20 > # >=20 > -# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved. >=20 > +# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved. >=20 > # >=20 > # SPDX-License-Identifier: BSD-2-Clause-Patent >=20 > # >=20 > @@ -106,6 +106,7 @@ > gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport ## CONSU= MES >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport ## > CONSUMES >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration ## > SOMETIMES_CONSUMES >=20 > + gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport ## > CONSUMES >=20 >=20 >=20 > [UserExtensions.TianoCore."ExtraFiles"] >=20 > PciBusDxeExtra.uni >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > index 6c68a97d4e..1b64924b7b 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c > @@ -1,7 +1,7 @@ > /** @file >=20 > PCI emumeration support functions implementation for PCI Bus module. >=20 >=20 >=20 > -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
>=20 > (C) Copyright 2015 Hewlett Packard Enterprise Development LP
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > @@ -2426,6 +2426,31 @@ CreatePciIoDevice ( > } >=20 > } >=20 >=20 >=20 > + PciIoDevice->ResizableBarOffset =3D 0; >=20 > + if (PcdGetBool (PcdPcieResizableBarSupport)) { >=20 > + Status =3D LocatePciExpressCapabilityRegBlock ( >=20 > + PciIoDevice, >=20 > + PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID, >=20 > + &PciIoDevice->ResizableBarOffset, >=20 > + NULL >=20 > + ); >=20 > + if (!EFI_ERROR (Status)) { >=20 > + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL > ResizableBarControl; >=20 > + UINT32 Offset; >=20 > + Offset =3D PciIoDevice->ResizableBarOffset + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER) >=20 > + + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CAPABILITY), >=20 > + PciIo->Pci.Read ( >=20 > + PciIo, >=20 > + EfiPciIoWidthUint8, >=20 > + Offset, >=20 > + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_CONTROL), >=20 > + &ResizableBarControl >=20 > + ); >=20 > + PciIoDevice->ResizableBarNumber =3D > ResizableBarControl.Bits.ResizableBarNumber; >=20 > + PciProgramResizableBar (PciIoDevice, PciResizableBarMax); >=20 > + } >=20 > + } >=20 > + >=20 > // >=20 > // Initialize the reserved resource list >=20 > // >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > index d76606c7df..4581b270c9 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.h > @@ -1,7 +1,7 @@ > /** @file >=20 > PCI enumeration support functions declaration for PCI Bus module. >=20 >=20 >=20 > -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -467,4 +467,14 @@ DumpPpbPaddingResource ( > IN PCI_BAR_TYPE ResourceType >=20 > ); >=20 >=20 >=20 > +/** >=20 > + Dump the PCI BAR information. >=20 > + >=20 > + @param PciIoDevice PCI IO instance. >=20 > +**/ >=20 > +VOID >=20 > +DumpPciBars ( >=20 > + IN PCI_IO_DEVICE *PciIoDevice >=20 > + ); >=20 > + >=20 > #endif >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > index 72690ab647..6bba283671 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.c > @@ -1,7 +1,7 @@ > /** @file >=20 > Internal library implementation for PCI Bus module. >=20 >=20 >=20 > -Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
>=20 > (C) Copyright 2015 Hewlett Packard Enterprise Development LP
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > @@ -377,6 +377,60 @@ DumpResourceMap ( > } >=20 > } >=20 >=20 >=20 > +/** >=20 > + Adjust the Devices' BAR size to minimum value if it support Resizeable= BAR > capability. >=20 > + >=20 > + @param RootBridgeDev Pointer to instance of PCI_IO_DEVICE.. >=20 > + >=20 > + @return TRUE if BAR size is adjusted. >=20 > + >=20 > +**/ >=20 > +BOOLEAN >=20 > +AdjustPciDeviceBarSize ( >=20 > + IN PCI_IO_DEVICE *RootBridgeDev >=20 > + ) >=20 > +{ >=20 > + PCI_IO_DEVICE *PciIoDevice; >=20 > + LIST_ENTRY *CurrentLink; >=20 > + BOOLEAN Adjusted; >=20 > + UINTN Offset; >=20 > + UINTN BarIndex; >=20 > + >=20 > + Adjusted =3D FALSE; >=20 > + CurrentLink =3D RootBridgeDev->ChildList.ForwardLink; >=20 > + >=20 > + while (CurrentLink !=3D NULL && CurrentLink !=3D &RootBridgeDev->Child= List) { >=20 > + PciIoDevice =3D PCI_IO_DEVICE_FROM_LINK (CurrentLink); >=20 > + >=20 > + if (IS_PCI_BRIDGE (&PciIoDevice->Pci)) { >=20 > + if (AdjustPciDeviceBarSize (PciIoDevice)) { >=20 > + Adjusted =3D TRUE; >=20 > + } >=20 > + } else { >=20 > + if (PciIoDevice->ResizableBarOffset !=3D 0) { >=20 > + DEBUG (( >=20 > + DEBUG_ERROR, >=20 > + "PciBus: [%02x|%02x|%02x] Adjust Pci Device Bar Size\n", >=20 > + PciIoDevice->BusNumber, PciIoDevice->DeviceNumber, PciIoDevice= - > >FunctionNumber >=20 > + )); >=20 > + PciProgramResizableBar (PciIoDevice, PciResizableBarMin); >=20 > + // >=20 > + // Start to parse the bars >=20 > + // >=20 > + for (Offset =3D 0x10, BarIndex =3D 0; Offset <=3D 0x24 && BarInd= ex < > PCI_MAX_BAR; BarIndex++) { >=20 > + Offset =3D PciParseBar (PciIoDevice, Offset, BarIndex); >=20 > + } >=20 > + Adjusted =3D TRUE; >=20 > + DEBUG_CODE (DumpPciBars (PciIoDevice);); >=20 > + } >=20 > + } >=20 > + >=20 > + CurrentLink =3D CurrentLink->ForwardLink; >=20 > + } >=20 > + >=20 > + return Adjusted; >=20 > +} >=20 > + >=20 > /** >=20 > Submits the I/O and memory resource requirements for the specified PCI > Host Bridge. >=20 >=20 >=20 > @@ -422,6 +476,10 @@ PciHostBridgeResourceAllocator ( > PCI_RESOURCE_NODE PMem64Pool; >=20 > EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD HandleExtendedData; >=20 > EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD > AllocFailExtendedData; >=20 > + BOOLEAN ResizableBarNeedAdjust; >=20 > + BOOLEAN ResizableBarAdjusted; >=20 > + >=20 > + ResizableBarNeedAdjust =3D PcdGetBool (PcdPcieResizableBarSupport); >=20 >=20 >=20 > // >=20 > // It may try several times if the resource allocation fails >=20 > @@ -703,19 +761,30 @@ PciHostBridgeResourceAllocator ( > sizeof (AllocFailExtendedData) >=20 > ); >=20 >=20 >=20 > - Status =3D PciHostBridgeAdjustAllocation ( >=20 > - &IoPool, >=20 > - &Mem32Pool, >=20 > - &PMem32Pool, >=20 > - &Mem64Pool, >=20 > - &PMem64Pool, >=20 > - IoResStatus, >=20 > - Mem32ResStatus, >=20 > - PMem32ResStatus, >=20 > - Mem64ResStatus, >=20 > - PMem64ResStatus >=20 > - ); >=20 > - >=20 > + // >=20 > + // When resource conflict happens, adjust the BAR size first. >=20 > + // Only when adjusting BAR size doesn't help or BAR size cannot be > adjusted, >=20 > + // reject the device who requests largest resource that causes conf= lict. >=20 > + // >=20 > + ResizableBarAdjusted =3D FALSE; >=20 > + if (ResizableBarNeedAdjust) { >=20 > + ResizableBarAdjusted =3D AdjustPciDeviceBarSize (RootBridgeDev); >=20 > + ResizableBarNeedAdjust =3D FALSE; >=20 > + } >=20 > + if (!ResizableBarAdjusted) { >=20 > + Status =3D PciHostBridgeAdjustAllocation ( >=20 > + &IoPool, >=20 > + &Mem32Pool, >=20 > + &PMem32Pool, >=20 > + &Mem64Pool, >=20 > + &PMem64Pool, >=20 > + IoResStatus, >=20 > + Mem32ResStatus, >=20 > + PMem32ResStatus, >=20 > + Mem64ResStatus, >=20 > + PMem64ResStatus >=20 > + ); >=20 > + } >=20 > // >=20 > // Destroy all the resource tree >=20 > // >=20 > @@ -1651,3 +1720,91 @@ PciHostBridgeEnumerator ( >=20 >=20 > return EFI_SUCCESS; >=20 > } >=20 > + >=20 > +/** >=20 > + This function is used to program the Resizable BAR Register. >=20 > + >=20 > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. >=20 > + @param ResizableBarOp PciResizableBarMax: Set BAR to max size >=20 > + PciResizableBarMin: set BAR to min size. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully enumerated the host bridge. >=20 > + @retval other Some error occurred when enumerating the= host > bridge. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PciProgramResizableBar ( >=20 > + IN PCI_IO_DEVICE *PciIoDevice, >=20 > + IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp >=20 > + ) >=20 > +{ >=20 > + EFI_PCI_IO_PROTOCOL *PciIo; >=20 > + UINT64 Capabilities; >=20 > + UINT32 Index; >=20 > + UINT32 Offset; >=20 > + INTN Bit; >=20 > + UINTN ResizableBarNumber; >=20 > + EFI_STATUS Status; >=20 > + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY > Entries[PCI_MAX_BAR]; >=20 > + >=20 > + ASSERT (PciIoDevice->ResizableBarOffset !=3D 0); >=20 > + >=20 > + DEBUG ((DEBUG_INFO, " Programs Resizable BAR register, offset: 0x%08= x, > number: %d\n", >=20 > + PciIoDevice->ResizableBarOffset, PciIoDevice->ResizableBarNumber= )); >=20 > + >=20 > + ResizableBarNumber =3D MIN (PciIoDevice->ResizableBarNumber, > PCI_MAX_BAR); >=20 > + PciIo =3D &PciIoDevice->PciIo; >=20 > + Status =3D PciIo->Pci.Read ( >=20 > + PciIo, >=20 > + EfiPciIoWidthUint8, >=20 > + PciIoDevice->ResizableBarOffset + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER), >=20 > + sizeof (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) > * ResizableBarNumber, >=20 > + (VOID *)(&Entries) >=20 > + ); >=20 > + ASSERT_EFI_ERROR (Status); >=20 > + >=20 > + for (Index =3D 0; Index < ResizableBarNumber; Index++) { >=20 > + >=20 > + // >=20 > + // When the bit of Capabilities Set, indicates that the Function sup= ports >=20 > + // operating with the BAR sized to (2^Bit) MB. >=20 > + // Example: >=20 > + // Bit 0 is set: supports operating with the BAR sized to 1 MB >=20 > + // Bit 1 is set: supports operating with the BAR sized to 2 MB >=20 > + // Bit n is set: supports operating with the BAR sized to (2^n) MB >=20 > + // >=20 > + Capabilities =3D > LShiftU64(Entries[Index].ResizableBarControl.Bits.BarSizeCapability, 28) >=20 > + | Entries[Index].ResizableBarCapability.Bits.BarSizeCa= pability; >=20 > + >=20 > + if (ResizableBarOp =3D=3D PciResizableBarMax) { >=20 > + Bit =3D HighBitSet64(Capabilities); >=20 > + } else if (ResizableBarOp =3D=3D PciResizableBarMin) { >=20 > + Bit =3D LowBitSet64(Capabilities); >=20 > + } else { >=20 > + ASSERT ((ResizableBarOp =3D=3D PciResizableBarMax) || (ResizableBa= rOp =3D=3D > PciResizableBarMin)); >=20 > + } >=20 > + >=20 > + ASSERT (Bit >=3D 0); >=20 > + >=20 > + Offset =3D PciIoDevice->ResizableBarOffset + sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER) >=20 > + + Index * sizeof > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY) >=20 > + + OFFSET_OF > (PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY, > ResizableBarControl); >=20 > + >=20 > + Entries[Index].ResizableBarControl.Bits.BarSize =3D (UINT32) Bit; >=20 > + DEBUG (( >=20 > + DEBUG_INFO, >=20 > + " Resizable Bar: Offset =3D 0x%x, Bar Size Capability =3D 0x%016= lx, New Bar > Size =3D 0x%lx\n", >=20 > + OFFSET_OF (PCI_TYPE00, > Device.Bar[Entries[Index].ResizableBarControl.Bits.BarIndex]), >=20 > + Capabilities, LShiftU64 (SIZE_1MB, Bit) >=20 > + )); >=20 > + PciIo->Pci.Write ( >=20 > + PciIo, >=20 > + EfiPciIoWidthUint32, >=20 > + Offset, >=20 > + 1, >=20 > + &Entries[Index].ResizableBarControl.Uint32 >=20 > + ); >=20 > + } >=20 > + >=20 > + return EFI_SUCCESS; >=20 > +} >=20 > diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > index 10b435d146..aeec6d6b6d 100644 > --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciLib.h > @@ -1,7 +1,7 @@ > /** @file >=20 > Internal library declaration for PCI Bus module. >=20 >=20 >=20 > -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
>=20 > +Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -24,6 +24,10 @@ typedef struct { > UINT8 *AllocRes; >=20 > } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD; >=20 >=20 >=20 > +typedef enum { >=20 > + PciResizableBarMin =3D 0x00, >=20 > + PciResizableBarMax =3D 0xFF >=20 > +} PCI_RESIZABLE_BAR_OPERATION; >=20 >=20 >=20 > /** >=20 > Retrieve the PCI Card device BAR information via PciIo interface. >=20 > @@ -156,4 +160,20 @@ PciHostBridgeEnumerator ( > IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > *PciResAlloc >=20 > ); >=20 >=20 >=20 > +/** >=20 > + This function is used to program the Resizable BAR Register. >=20 > + >=20 > + @param PciIoDevice A pointer to the PCI_IO_DEVICE. >=20 > + @param ResizableBarOp PciResizableBarMax: Set BAR to max size >=20 > + PciResizableBarMin: set BAR to min size. >=20 > + >=20 > + @retval EFI_SUCCESS Successfully enumerated the host bridge. >=20 > + @retval other Some error occurred when enumerating the= host > bridge. >=20 > + >=20 > +**/ >=20 > +EFI_STATUS >=20 > +PciProgramResizableBar ( >=20 > + IN PCI_IO_DEVICE *PciIoDevice, >=20 > + IN PCI_RESIZABLE_BAR_OPERATION ResizableBarOp >=20 > + ); >=20 > #endif >=20 > diff --git a/MdeModulePkg/MdeModulePkg.dec > b/MdeModulePkg/MdeModulePkg.dec > index 9b52b34494..9173fdef83 100644 > --- a/MdeModulePkg/MdeModulePkg.dec > +++ b/MdeModulePkg/MdeModulePkg.dec > @@ -4,7 +4,7 @@ > # and libraries instances, which are used for those modules. >=20 > # >=20 > # Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. >=20 > -# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
>=20 > +# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
>=20 > # Copyright (c) 2016, Linaro Ltd. All rights reserved.
>=20 > # (C) Copyright 2016 - 2019 Hewlett Packard Enterprise Development LP >=20 > # Copyright (c) 2017, AMD Incorporated. All rights reserved.
>=20 > @@ -2043,6 +2043,12 @@ > # @Prompt Enable StatusCode via memory. >=20 >=20 > gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE|BOOLE > AN|0x00010023 >=20 >=20 >=20 > + ## Indicates if the PCIe Resizable BAR Capability Supported.

>=20 > + # TRUE - PCIe Resizable BAR Capability is supported.
>=20 > + # FALSE - PCIe Resizable BAR Capability is not supported.
>=20 > + # @Prompt Enable PCIe Resizable BAR Capability support. >=20 > + > gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport|TRUE|BOOLE > AN|0x10000024 >=20 > + >=20 > [PcdsPatchableInModule] >=20 > ## Specify memory size with page number for PEI code when >=20 > # Loading Module at Fixed Address feature is enabled. >=20 > -- > 2.24.0.windows.2