From: "Ni, Ray" <ray.ni@intel.com>
To: "Sheng, W" <w.sheng@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Dong, Eric" <eric.dong@intel.com>,
Laszlo Ersek <lersek@redhat.com>,
"Kumar, Rahul1" <rahul1.kumar@intel.com>,
"Yao, Jiewen" <jiewen.yao@intel.com>
Subject: Re: [PATCH v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo
Date: Fri, 30 Oct 2020 10:44:03 +0000 [thread overview]
Message-ID: <CO1PR11MB493015671B75974B051B79588C150@CO1PR11MB4930.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20201030074502.5744-2-w.sheng@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
> -----Original Message-----
> From: Sheng, W <w.sheng@intel.com>
> Sent: Friday, October 30, 2020 3:45 PM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul1
> <rahul1.kumar@intel.com>; Yao, Jiewen <jiewen.yao@intel.com>
> Subject: [PATCH v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo
>
> Change the variable name from mInternalGr3 to mInternalCr3.
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3015
>
> Change-Id: I6a9df4836d4358405837b1ebbd2d5d4c85e3635f
> Signed-off-by: Sheng Wei <w.sheng@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> Cc: Jiewen Yao <jiewen.yao@intel.com>
> ---
> UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> index ebfc46ad45..d67f036aea 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c
> @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] = {
> {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64},
> };
>
> -UINTN mInternalGr3;
> +UINTN mInternalCr3;
>
> /**
> Set the internal page table base address.
> @@ -46,7 +46,7 @@ SetPageTableBase (
> IN UINTN Cr3
> )
> {
> - mInternalGr3 = Cr3;
> + mInternalCr3 = Cr3;
> }
>
> /**
> @@ -59,8 +59,8 @@ GetPageTableBase (
> VOID
> )
> {
> - if (mInternalGr3 != 0) {
> - return mInternalGr3;
> + if (mInternalCr3 != 0) {
> + return mInternalCr3;
> }
> return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64);
> }
> @@ -252,7 +252,7 @@ ConvertPageEntryAttribute (
> if ((Attributes & EFI_MEMORY_RO) != 0) {
> if (IsSet) {
> NewPageEntry &= ~(UINT64)IA32_PG_RW;
> - if (mInternalGr3 != 0) {
> + if (mInternalCr3 != 0) {
> // Environment setup
> // ReadOnly page need set Dirty bit for shadow stack
> NewPageEntry |= IA32_PG_D;
> --
> 2.16.2.windows.1
next parent reply other threads:[~2020-10-30 10:44 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20201030074502.5744-1-w.sheng@intel.com>
[not found] ` <20201030074502.5744-2-w.sheng@intel.com>
2020-10-30 10:44 ` Ni, Ray [this message]
[not found] ` <20201030074502.5744-3-w.sheng@intel.com>
2020-10-31 6:29 ` [PATCH v2 2/2] UefiCpuPkg/PiSmmCpuDxeSmm: Return level paging type for Internal CR3 Ni, Ray
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