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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Sheng, W > Sent: Friday, October 30, 2020 3:45 PM > To: devel@edk2.groups.io > Cc: Dong, Eric ; Ni, Ray ; Laszlo = Ersek ; Kumar, Rahul1 > ; Yao, Jiewen > Subject: [PATCH v2 1/2] UefiCpuPkg/PiSmmCpuDxeSmm: Correct the Cr3 typo >=20 > Change the variable name from mInternalGr3 to mInternalCr3. >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3015 >=20 > Change-Id: I6a9df4836d4358405837b1ebbd2d5d4c85e3635f > Signed-off-by: Sheng Wei > Cc: Eric Dong > Cc: Ray Ni > Cc: Laszlo Ersek > Cc: Rahul Kumar > Cc: Jiewen Yao > --- > UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) >=20 > diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > index ebfc46ad45..d67f036aea 100644 > --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmCpuMemoryManagement.c > @@ -32,7 +32,7 @@ PAGE_ATTRIBUTE_TABLE mPageAttributeTable[] =3D { > {Page1G, SIZE_1GB, PAGING_1G_ADDRESS_MASK_64}, > }; >=20 > -UINTN mInternalGr3; > +UINTN mInternalCr3; >=20 > /** > Set the internal page table base address. > @@ -46,7 +46,7 @@ SetPageTableBase ( > IN UINTN Cr3 > ) > { > - mInternalGr3 =3D Cr3; > + mInternalCr3 =3D Cr3; > } >=20 > /** > @@ -59,8 +59,8 @@ GetPageTableBase ( > VOID > ) > { > - if (mInternalGr3 !=3D 0) { > - return mInternalGr3; > + if (mInternalCr3 !=3D 0) { > + return mInternalCr3; > } > return (AsmReadCr3 () & PAGING_4K_ADDRESS_MASK_64); > } > @@ -252,7 +252,7 @@ ConvertPageEntryAttribute ( > if ((Attributes & EFI_MEMORY_RO) !=3D 0) { > if (IsSet) { > NewPageEntry &=3D ~(UINT64)IA32_PG_RW; > - if (mInternalGr3 !=3D 0) { > + if (mInternalCr3 !=3D 0) { > // Environment setup > // ReadOnly page need set Dirty bit for shadow stack > NewPageEntry |=3D IA32_PG_D; > -- > 2.16.2.windows.1