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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni -----Original Message----- From: Lin, JackX =20 Sent: Friday, August 27, 2021 2:04 PM To: devel@edk2.groups.io Cc: Chiu, Chasel ; Dong, Eric ;= Yao, Jiewen ; Ni, Ray ; Chaganty, = Rangasai V ; Kuo, Donald ; Kumar, Chandana C Subject: [edk2-platforms: PATCH V10 1/2] Platform/Intel: Correct CPU APIC I= Ds REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3365 BIOS cannot find correct AcpiProcId in mApicIdMap because of there is no su= itable map, that causes ACPI_BIOS_ERROR. Remove mApicIdMap for determing AcpiProcId, uses normal countings instead. Signed-off-by: JackX Lin Cc: Chasel Chiu Cc: Dong Eric Cc: Jiewen Yao Cc: Ray Ni Cc: Rangasai V Chaganty Cc: Donald Kuo Cc: Chandana C Kumar Cc: JackX Lin --- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 417 +++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++------------------------------------------------------------------------= ---------------------------------------------------------------------------= ---------------------------------------------------------------------------= ------------------------------------- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 4 +++- Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 4 +++- 3 files changed, 164 insertions(+), 261 deletions(-) diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b= /Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c index 2b51c34ef2..ab3296d68a 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c @@ -1,14 +1,13 @@ /** @file ACPI Platform Driver =20 -Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ =20 #include "AcpiPlatform.h" - -#define MAX_CPU_NUM (FixedPcdGet32(PcdMaxCpuThreadCount) * FixedPcdGet32(P= cdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuSocketCount)) +#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount)) =20 #pragma pack(1) =20 @@ -16,8 +15,8 @@ typedef struct { UINT32 AcpiProcessorId; UINT32 ApicId; UINT32 Flags; - UINT32 SwProcApicId; UINT32 SocketNum; + UINT32 Thread; } EFI_CPU_ID_ORDER_MAP; =20 // @@ -58,170 +57,58 @@ BOOLEAN mX2ApicEnabled; =20 EFI_MP_SERVICES_PROTOCOL *mMpService; BOOLEAN mCpuOrderSorted; -EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM]; -UINTN mNumberOfCPUs =3D 0; +EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable =3D NULL; +UINTN mNumberOfCpus =3D 0; UINTN mNumberOfEnabledCPUs =3D 0; =20 -// following are possible APICID Map for SKX -static const UINT32 ApicIdMa= pA[] =3D { //for SKUs have number of core > 16 - //it is 14 + 14 + 14 + 14 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x00000010, 0x00000011, - 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017, = 0x00000018, 0x00000019, - 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x00000020, 0x00000021, = 0x00000022, 0x00000023, - 0x00000024, 0x00000025, 0x00000026, 0x00000027, 0x00000028, 0x00000029, = 0x0000002A, 0x0000002B, - 0x0000002C, 0x0000002D, 0x00000030, 0x00000031, 0x00000032, 0x00000033, = 0x00000034, 0x00000035, - 0x00000036, 0x00000037, 0x00000038, 0x00000039, 0x0000003A, 0x0000003B, = 0x0000003C, 0x0000003D -}; - -static const UINT32 ApicIdMapB[] =3D { //for SKUs have number of cores <= =3D 16 use 32 ID space - //it is 16+16 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, = 0x00000016, 0x00000017, - 0x00000018, 0x00000019, 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, = 0x0000001E, 0x0000001F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - - -static const UINT32 ApicIdMapC[] =3D { //for SKUs have number of cores <= =3D 16 use 64 ID space - //it is 16+0+16+0 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, = 0x00000026, 0x00000027, - 0x00000028, 0x00000029, 0x0000002A, 0x0000002B, 0x0000002C, 0x0000002D, = 0x0000002E, 0x0000002F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - -static const UINT32 ApicIdMapD[] =3D { //for SKUs have number of cores <= =3D 8 use 16 ID space - //it is 16 format - 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, = 0x00000006, 0x00000007, - 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, = 0x0000000E, 0x0000000F, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF, - 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, = 0xFFFFFFFF, 0xFFFFFFFF -}; - -const UINT32 *mApicIdMap =3D NULL; =20 /** - This function detect the APICID map and update ApicID Map pointer + The function is called by PerformQuickSort to compare int values. =20 - @param None + @param[in] Left The pointer to first buffer. + @param[in] Right The pointer to second buffer. =20 - @retval VOID + @return -1 Buffer1 is less than Buffer2. + @return 1 Buffer1 is greater than Buffer2. =20 **/ -VOID DetectApicIdMap(VOID) +INTN +EFIAPI +ApicIdCompareFunction ( + IN CONST VOID *Left, + IN CONST VOID *Right + ) { - UINTN CoreCount; + UINT32 LeftApicId; + UINT32 RightApicId; =20 - CoreCount =3D 0; - - if(mApicIdMap !=3D NULL) { - return; //aleady initialized - } - - mApicIdMap =3D ApicIdMapA; // default to > 16C SKUs - - CoreCount =3D mNumberOfEnabledCPUs / 2; - DEBUG ((DEBUG_INFO, "CoreCount - %d\n", CoreCount)); - - //DEBUG((EFI_D_ERROR, ":: Default to use Map A @ %08X FusedCoreCount: %0= 2d, sktlevel: %d\n",mApicIdMap, FusedCoreCount, mNumOfBitShift)); - // Dont assert for single core, single thread system. - //ASSERT (CoreCount !=3D 0); - - if(CoreCount <=3D 16) { - - if(mNumOfBitShift =3D=3D 4) { - mApicIdMap =3D ApicIdMapD; - //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap)); - } - - if(mNumOfBitShift =3D=3D 5) { - mApicIdMap =3D ApicIdMapB; - //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap)); - } - - if(mNumOfBitShift =3D=3D 6) { - mApicIdMap =3D ApicIdMapC; - //DEBUG((EFI_D_ERROR, ":: Use Map C @ %08X\n",mApicIdMap)); - } + LeftApicId =3D ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId; RightApicId =3D= =20 + ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId; =20 - } - - return; + return (LeftApicId > RightApicId)? 1 : (-1); } =20 /** - This function return the CoreThreadId of ApicId from ACPI ApicId Map arr= ay - - @param ApicId - - @retval Index of ACPI ApicId Map array + Print Cpu Apic ID Table =20 + @param[in] CpuApicIdOrderTable Data will be dumped. **/ -UINT32 -GetIndexFromApicId ( - UINT32 ApicId - ) -{ - UINT32 CoreThreadId; - UINT32 i; - - ASSERT (mApicIdMap !=3D NULL); - - CoreThreadId =3D ApicId & ((1 << mNumOfBitShift) - 1); - - for(i =3D 0; i < (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdM= axCpuThreadCount)); i++) { - if(mApicIdMap[i] =3D=3D CoreThreadId) { - break; - } - } - - ASSERT (i <=3D (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMax= CpuThreadCount))); - - return i; -} - -UINT32 -ApicId2SwProcApicId ( - UINT32 ApicId - ) -{ - UINT32 Index; - - for (Index =3D 0; Index < MAX_CPU_NUM; Index++) { - if ((mCpuApicIdOrderTable[Index].Flags =3D=3D 1) && (mCpuApicIdOrderTa= ble[Index].ApicId =3D=3D ApicId)) { - return Index; - } - } - - return (UINT32) -1; - -} - VOID -DebugDisplayReOrderTable( - VOID +DebugDisplayReOrderTable ( + IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable ) { UINT32 Index; =20 - DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\n"= )); - for (Index=3D0; IndexGetProcessorInfo ( - mMpService, - CurrProcessor, - &ProcessorInfoBuffer - ); + TempCpuApicIdOrderTable =3D AllocateZeroPool (mNumberOfCpus * sizeof=20 + (EFI_CPU_ID_ORDER_MAP)); TempVal =3D AllocateZeroPool (sizeof=20 + (EFI_CPU_ID_ORDER_MAP)); CoreThreadMask =3D (UINT32) ((1 <<=20 + mNumOfBitShift) - 1); =20 - if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) !=3D 0)= { - if(ProcessorInfoBuffer.ProcessorId & 1) { //is 2nd thread - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[(I= ndex - 1) + MAX_CPU_NUM / 2]; - } else { //is primary thread - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[In= dex]; - Index++; + for (CurrProcessor =3D 0, Index =3D 0; CurrProcessor < mNumberOfCpus; Cu= rrProcessor++, Index++) { + Status =3D mMpService->GetProcessorInfo ( + mMpService, + CurrProcessor, + &ProcessorInfoBuffer + ); + + CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Inde= x]; + if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) !=3D 0) { + CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId; + CpuIdMapPtr->Thread =3D ProcessorInfoBuffer.Location.Thread; + CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROCESSO= R_ENABLED_BIT) !=3D 0); + CpuIdMapPtr->SocketNum =3D ProcessorInfoBuffer.Location.Package; + + //update processorbitMask + if (CpuIdMapPtr->Flags =3D=3D 1) { + if (mForceX2ApicId) { + CpuIdMapPtr->SocketNum &=3D 0x7; + CpuIdMapPtr->AcpiProcessorId &=3D 0xFF; //keep lower 8bit due=20 + to use Proc obj in dsdt } - CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId; - CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROCES= SOR_ENABLED_BIT) !=3D 0); - CpuIdMapPtr->SocketNum =3D (UINT32)ProcessorInfoBuffer.Location.Pa= ckage; - CpuIdMapPtr->AcpiProcessorId =3D (CpuIdMapPtr->SocketNum * FixedPc= dGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + GetInde= xFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId; - CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.Locati= on.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.ProcessorId) = & CoreThreadMask)); - if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it star= ts from base 0 and contiguous - //may not necessory!!!!! - } - - //update processorbitMask - if (CpuIdMapPtr->Flags =3D=3D 1) { + } + } else { //not enabled + CpuIdMapPtr->ApicId =3D (UINT32)-1; + CpuIdMapPtr->Thread =3D (UINT32)-1; + CpuIdMapPtr->Flags =3D 0; + CpuIdMapPtr->SocketNum =3D (UINT32)-1; + } //end if PROC ENABLE + } //end for CurrentProcessor + =20 + //keep for debug purpose + DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMa= sk =3D %x, mNumOfBitShift =3D %x\n", CoreThreadMask, mNumOfBitShift)); + DebugDisplayReOrderTable (TempCpuApicIdOrderTable); + + // + // Get Bsp Apic Id + // + BspApicId =3D GetApicId (); + DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", BspApicId)); + + // + //check to see if 1st entry is BSP, if not swap it // if=20 + (TempCpuApicIdOrderTable[0].ApicId !=3D BspApicId) { + for (Index =3D 0; Index < mNumberOfCpus; Index++) { + if ((TempCpuApicIdOrderTable[Index].Flags =3D=3D 1) && (TempCpuApicI= dOrderTable[Index].ApicId =3D=3D BspApicId)) { + CopyMem (&TempVal, &TempCpuApicIdOrderTable[Index], sizeof (EFI_CP= U_ID_ORDER_MAP)); + CopyMem (&TempCpuApicIdOrderTable[Index], &TempCpuApicIdOrderTable= [0], sizeof (EFI_CPU_ID_ORDER_MAP)); + CopyMem (&TempCpuApicIdOrderTable[0], &TempVal, sizeof (EFI_CPU_ID= _ORDER_MAP)); + break; + } + } =20 - if(mForceX2ApicId) { - CpuIdMapPtr->SocketNum &=3D 0x7; - CpuIdMapPtr->AcpiProcessorId &=3D 0xFF; //keep lower 8bit due = to use Proc obj in dsdt - CpuIdMapPtr->SwProcApicId &=3D 0xFF; - } - } - } else { //not enabled - CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Inde= x]; - CpuIdMapPtr->ApicId =3D (UINT32)-1; - CpuIdMapPtr->Flags =3D 0; - CpuIdMapPtr->AcpiProcessorId =3D (UINT32)-1; - CpuIdMapPtr->SwProcApicId =3D (UINT32)-1; - CpuIdMapPtr->SocketNum =3D (UINT32)-1; - } //end if PROC ENABLE - } //end for CurrentProcessor - - //keep for debug purpose - DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThread= Mask =3D %x, mNumOfBitShift =3D %x\n", CoreThreadMask, mNumOfBitShift)); - DebugDisplayReOrderTable(); - - //make sure 1st entry is BSP - if(mX2ApicEnabled) { - BspApicId =3D (UINT32)AsmReadMsr64(0x802); - } else { - BspApicId =3D (*(volatile UINT32 *)(UINTN)0xFEE00020) >> 24; + if (mNumberOfCpus <=3D Index) { + DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bu= fferflow\n")); + return EFI_INVALID_PARAMETER; } - DEBUG ((EFI_D_INFO, "BspApicId - 0x%x\n", BspApicId)); + } =20 - if(mCpuApicIdOrderTable[0].ApicId !=3D BspApicId) { - //check to see if 1st entry is BSP, if not swap it - Index =3D ApicId2SwProcApicId(BspApicId); + // + // 1. Sort TempCpuApicIdOrderTable,=20 + // sort it by using ApicId from minimum to maximum (Socket0 to Socket= N), and the BSP must in the fist location of the table. + // So, start sorting the table from the second element and total elem= ents are mNumberOfCpus-1. + // + PerformQuickSort ((TempCpuApicIdOrderTable + 1), (mNumberOfCpus - 1),=20 + sizeof (EFI_CPU_ID_ORDER_MAP), (SORT_COMPARE) ApicIdCompareFunction); =20 - if(MAX_CPU_NUM <=3D Index) { - DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index = Bufferflow\n")); - return EFI_INVALID_PARAMETER; - } + // + // 2. Sort and map the primary threads to the front of the=20 + CpuApicIdOrderTable // for (CurrProcessor =3D 0, Index =3D 0; Index <=20 + mNumberOfCpus; Index++) { + if ((TempCpuApicIdOrderTable[Index].Thread) =3D=3D 0) { // primary thr= ead + CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTa= ble[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } =20 - TempVal =3D mCpuApicIdOrderTable[Index].ApicId; - mCpuApicIdOrderTable[Index].ApicId =3D mCpuApicIdOrderTable[0].ApicI= d; - mCpuApicIdOrderTable[0].ApicId =3D TempVal; - mCpuApicIdOrderTable[Index].Flags =3D mCpuApicIdOrderTable[0].Flags; - mCpuApicIdOrderTable[0].Flags =3D 1; - TempVal =3D mCpuApicIdOrderTable[Index].SwProcApicId; - mCpuApicIdOrderTable[Index].SwProcApicId =3D mCpuApicIdOrderTable[0]= .SwProcApicId; - mCpuApicIdOrderTable[0].SwProcApicId =3D TempVal; - //swap AcpiProcId - TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorId; - mCpuApicIdOrderTable[Index].AcpiProcessorId =3D mCpuApicIdOrderTable= [0].AcpiProcessorId; - mCpuApicIdOrderTable[0].AcpiProcessorId =3D TempVal; + // + // 3. Sort and map the second threads to the middle of the=20 + CpuApicIdOrderTable // for (Index =3D 0; Index < mNumberOfCpus;=20 + Index++) { + if ((TempCpuApicIdOrderTable[Index].Thread) =3D=3D 1) { //second threa= d + CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTa= ble[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; + } + } =20 + // + // 4. Sort and map the not enabled threads to the bottom of the=20 + CpuApicIdOrderTable // for (Index =3D 0; Index < mNumberOfCpus;=20 + Index++) { + if (TempCpuApicIdOrderTable[Index].Flags =3D=3D 0) { // not enabled + CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTa= ble[Index], sizeof (EFI_CPU_ID_ORDER_MAP)); + CurrProcessor++; } + } =20 - //Make sure no holes between enabled threads - for(CurrProcessor =3D 0; CurrProcessor < MAX_CPU_NUM; CurrProcessor++)= { - - if(mCpuApicIdOrderTable[CurrProcessor].Flags =3D=3D 0) { - //make sure disabled entry has ProcId set to FFs - mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32)-1; - mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D (UINT32)-1= ; - mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32)-1; - - for(Index =3D CurrProcessor+1; Index < MAX_CPU_NUM; Index++) { - if(mCpuApicIdOrderTable[Index].Flags =3D=3D 1) { - //move enabled entry up - mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1; - mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCpuApicIdOrder= Table[Index].ApicId; - mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D mCpuAp= icIdOrderTable[Index].AcpiProcessorId; - mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCpuApicI= dOrderTable[Index].SwProcApicId; - mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCpuApicIdOr= derTable[Index].SocketNum; - //disable moved entry - mCpuApicIdOrderTable[Index].Flags =3D 0; - mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1; - mCpuApicIdOrderTable[Index].AcpiProcessorId =3D (UINT32)-1; - mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1; - break; - } - } + // + // 5. Re-assigen AcpiProcessorId for AcpiProcessorUId uses purpose. + // + for (Socket =3D 0; Socket < MAX_SOCKET; Socket++) { + for (CurrProcessor =3D 0, Index =3D 0; CurrProcessor < mNumberOfCpus; = CurrProcessor++) { + if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTab= le[CurrProcessor].SocketNum =3D=3D Socket)) { + mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D (Processor= InfoBuffer.Location.Package << mNumOfBitShift) + Index; + Index++; } } + } =20 - //keep for debug purpose - DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n")); - DebugDisplayReOrderTable(); + //keep for debug purpose + DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n")); =20 + DebugDisplayReOrderTable (mCpuApicIdOrderTable); =20 - mCpuOrderSorted =3D TRUE; - } + mCpuOrderSorted =3D TRUE; =20 return Status; } @@ -871,7 +762,11 @@ InstallMadtFromScratch ( NewMadtTable =3D NULL; MaxMadtStructCount =3D 0; =20 - DetectApicIdMap(); + mCpuApicIdOrderTable =3D AllocateZeroPool (mNumberOfCpus * sizeof=20 + (EFI_CPU_ID_ORDER_MAP)); if (mCpuApicIdOrderTable =3D=3D NULL) { + DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structur= e pointer array\n")); + return EFI_OUT_OF_RESOURCES; + } =20 // Call for Local APIC ID Reorder Status =3D SortCpuLocalApicInTable (); @@ -881,8 +776,8 @@ InstallMadtFromScratch ( } =20 MaxMadtStructCount =3D (UINT32) ( - MAX_CPU_NUM + // processor local APIC structures - MAX_CPU_NUM + // processor local x2APIC structures + mNumberOfCpus + // processor local APIC structures + mNumberOfCpus + // processor local x2APIC structures 1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures 2 + // interrupt source override structures 1 + // local APIC NMI structures @@ -910,7 +805,7 @@ InstallMadtFromScratch ( goto Done; } =20 - DEBUG ((EFI_D_INFO, "Number of CPUs detected =3D %d \n", mNumberOfCPUs))= ; + DEBUG ((EFI_D_INFO, "Number of CPUs detected =3D %d \n",=20 + mNumberOfCpus)); =20 // // Build Processor Local APIC Structures and Processor Local X2APIC Stru= ctures @@ -923,7 +818,7 @@ InstallMadtFromScratch ( ProcLocalX2ApicStruct.Reserved[0] =3D 0; ProcLocalX2ApicStruct.Reserved[1] =3D 0; =20 - for (Index =3D 0; Index < MAX_CPU_NUM; Index++) { + for (Index =3D 0; Index < mNumberOfCpus; Index++) { // // If x2APIC mode is not enabled, and if it is possible to express the // APIC ID as a UINT8, use a processor local APIC structure. Otherwise= , @@ -1136,6 +1031,10 @@ Done: FreePool (NewMadtTable); } =20 + if (mCpuApicIdOrderTable !=3D NULL) { + FreePool (mCpuApicIdOrderTable); + } + return Status; } =20 @@ -1551,11 +1450,11 @@ InstallAcpiPlatform ( // mMpService->GetNumberOfProcessors ( mMpService, - &mNumberOfCPUs, + &mNumberOfCpus, &mNumberOfEnabledCPUs ); - ASSERT (mNumberOfCPUs <=3D MAX_CPU_NUM && mNumberOfEnabledCPUs >=3D 1); - DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs)); + + DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus)); DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs)= ); =20 DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled)); diff --= git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h b/Platfo= rm/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h index bd11f9e988..61f7470f80 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h @@ -1,7 +1,7 @@ /** @file This is an implementation of the ACPI platform driver. =20 -Copyright (c) 2017, Intel Corporation. All rights reserved.
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent =20 **/ @@ -35,6 +35,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include #include #include = +#include +#include =20 #include #include diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf= b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf index 5d9c8cab50..95f6656af0 100644 --- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf +++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf @@ -1,7 +1,7 @@ ### @file # Component information file for AcpiPlatform module # -# Copyright (c) = 2017, Intel Corporation. All rights reserved.
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights=20 +reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,8 @@ PciSegmentInfoLib AslUpdateLib BoardAcpiTableLib + SortLib + LocalApicLib =20 [Pcd] gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId -- 2.32.0.windows.2