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boundary="_000_CO1PR11MB4930A27248B4DF5480BA4C4E8CDB9CO1PR11MB4930namp_" --_000_CO1PR11MB4930A27248B4DF5480BA4C4E8CDB9CO1PR11MB4930namp_ Content-Type: text/plain; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable Extending PciBus to support such case is valid. But can you check if there is other pure software way to detect whether it'= s an ECiEP? From: Bassa, Damian Sent: Wednesday, September 15, 2021 7:54 PM To: Wu, Hao A ; devel@edk2.groups.io; Ni, Ray Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che= ck for RCiEP before looking for RP Should we consider this workaround? I'm having issues interpreting this par= t of PCIe spec. My understanding of this quote is that this capability can exist in but it = shouldn't be considered. I would assume it's possible option that it needs to be considered? Is that= wrong? Damian From: Wu, Hao A > Sent: Wednesday, September 8, 2021 9:17 AM To: Bassa, Damian >; = devel@edk2.groups.io; Ni, Ray > Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che= ck for RCiEP before looking for RP Really sorry for the late response. So this is a workaround for RCiEP device that is not compliant to the PCIe = spec: |> ARI is an optional capability. This capability must be implemented by e= ach |> Function in an ARI Device. It is not applicable to a Root Port, a Switc= h |> Downstream Port, an RCiEP, or a Root Complex Event Collector. If this the case, could you help to: * Add a comment that briefly describe this workaround before the newly adde= d code * Also mention this workaround information in the commit log message. * Send out a V2 version of the patch? Thanks in advance. Hello Ray, please help to raise if you have concern on this. Best Regards, Hao Wu From: Bassa, Damian > Sent: Wednesday, September 1, 2021 1:45 AM To: Wu, Hao A >; devel@edk2.g= roups.io; Ni, Ray > Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che= ck for RCiEP before looking for RP It refers to access to the root port device that doesn't exist in case we a= re dealing with RCiEP device. There can be specific case where RCiEP device has ARI extended capability I= D (even though it's unsupported in this case). In such a case PciSearchDevice goes to CreatePciIoDevice through GatherDevi= ceInfo. And in this case parent is PCI_IO_DEVICE instance created from Crea= teRootBridge function, which isn't valid PCIe device and doesn't have speci= fic bus, only a range of buses. In that case enumerator tries to use this i= nstance to read operation using default 0 bus number, which isn't correct. Damian From: Wu, Hao A > Sent: Tuesday, August 31, 2021 6:28 AM To: devel@edk2.groups.io; Wu, Hao A >; Bassa, Damian >; Ni, Ray > Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che= ck for RCiEP before looking for RP From: devel@edk2.groups.io > On Behalf Of Wu, Hao A Sent: Tuesday, August 31, 2021 12:25 PM To: devel@edk2.groups.io; Bassa, Damian > Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to che= ck for RCiEP before looking for RP Really sorry, Could you help to provide more information on the below statement? "undefined parent register accesses" Thanks in advance. Best Regards, Hao Wu From: devel@edk2.groups.io > On Behalf Of Bassa, Damian Sent: Tuesday, August 24, 2021 11:15 PM To: devel@edk2.groups.io Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to check f= or RCiEP before looking for RP Before trying to access parent root port to check ARI capabilities, enumerator should see if Endpoint device is not Root Complex integrated to avoid undefined parent register accesses in these cases. Signed-off-by: Damian Bassa damian.bassa@intel.com --- .../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c b/MdeMod= ulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c index db1b35f8ef..6451fb8af9 100644 --- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c +++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c @@ -2153,6 +2153,7 @@ CreatePciIoDevice ( PCI_IO_DEVICE *PciIoDevice; EFI_PCI_IO_PROTOCOL *PciIo; EFI_STATUS Status; + PCI_REG_PCIE_CAPABILITY Capability; PciIoDevice =3D AllocateZeroPool (sizeof (PCI_IO_DEVICE)); if (PciIoDevice =3D=3D NULL) { @@ -2229,7 +2230,16 @@ CreatePciIoDevice ( return NULL; } - if (PcdGetBool (PcdAriSupport)) { + PciIo->Pci.Read ( + PciIo, + EfiPciIoWidthUint16, + PciIoDevice->PciExpressCapabilityOffset + OFFSET_OF (PCI_C= APABILITY_PCIEXP, Capability), + 1, + &Capability.Uint16 + ); + + if (PcdGetBool (PcdAriSupport) && + Capability.Bits.DevicePortType !=3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX= _INTEGRATED_ENDPOINT) { // // Check if the device is an ARI device. // -- 2.27.0.windows.1 ________________________________ Intel Technology Poland sp. z o.o. ul. S=B3owackiego 173 | 80-298 Gda=F1sk | S=B1d Rejonowy Gda=F1sk P=F3=B3no= c | VII Wydzia=B3 Gospodarczy Krajowego Rejestru S=B1dowego - KRS 101882 | = NIP 957-07-52-316 | Kapita=B3 zak=B3adowy 200.000 PLN. Ta wiadomo=B6=E6 wraz z za=B3=B1cznikami jest przeznaczona dla okre=B6loneg= o adresata i mo=BFe zawiera=E6 informacje poufne. W razie przypadkowego otr= zymania tej wiadomo=B6ci, prosimy o powiadomienie nadawcy oraz trwa=B3e jej= usuni=EAcie; jakiekolwiek przegl=B1danie lub rozpowszechnianie jest zabron= ione. This e-mail and any attachments may contain confidential material for the s= ole use of the intended recipient(s). If you are not the intended recipient= , please contact the sender and delete all copies; any review or distributi= on by others is strictly prohibited. --_000_CO1PR11MB4930A27248B4DF5480BA4C4E8CDB9CO1PR11MB4930namp_ Content-Type: text/html; charset="iso-8859-2" Content-Transfer-Encoding: quoted-printable

Extending PciBus to support such case is valid.=

 

But can you check if there is other pure software wa= y to detect whether it’s an ECiEP?

 

From: Bassa, Damian <damian.bassa@intel.co= m>
Sent: Wednesday, September 15, 2021 7:54 PM
To: Wu, Hao A <hao.a.wu@intel.com>; devel@edk2.groups.io; Ni, = Ray <ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator= to check for RCiEP before looking for RP

 

Should we consider this workaround? I’m having= issues interpreting this part of PCIe spec.

My understanding of this quote is that this capabili= ty can exist in but it shouldn’t be considered.

I would assume it’s possible option that it ne= eds to be considered? Is that wrong?

 

Damian

 

 

From: Wu, Hao A <hao.a.wu@intel.com>
Sent: Wednesday, September 8, 2021 9:17 AM
To: Bassa, Damian <dami= an.bassa@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator= to check for RCiEP before looking for RP

 

Really sorry for the late response.

 

So this is a workaround for RCiEP device that is not= compliant to the PCIe spec:

|>  ARI is an optional capability. This capa= bility must be implemented by each

|>  Function in an ARI Device. It is not app= licable to a Root Port, a Switch

|>  Downstream Port, an RCiEP, or a Root Com= plex Event Collector.

 

If this the case, could you help to:

* Add a comment that briefly describe this workaroun= d before the newly added code

* Also mention this workaround information in the co= mmit log message.

* Send out a V2 version of the patch?

Thanks in advance.

 

Hello Ray, please help to raise if you have concern = on this.

 

Best Regards,

Hao Wu

 

From: Bassa, Damian <damian.bassa@intel.com>
Sent: Wednesday, September 1, 2021 1:45 AM
To: Wu, Hao A <hao.a.wu@int= el.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator= to check for RCiEP before looking for RP

 

It refers to access to the root port device that doe= sn’t exist in case we are dealing with RCiEP device.

There can be specific case where RCiEP device has AR= I extended capability ID (even though it’s unsupported in this case).

In such a case PciSearchDevice goes to CreatePciIoDe= vice through GatherDeviceInfo. And in this case parent is PCI_IO_DEVICE ins= tance created from CreateRootBridge function, which isn’t valid PCIe = device and doesn’t have specific bus, only a range of buses. In that case enumerator tries to use this instance to re= ad operation using default 0 bus number, which isn’t correct.

 

Damian

 

From: Wu, Hao A <hao.a.wu@intel.com>
Sent: Tuesday, August 31, 2021 6:28 AM
To: devel@edk2.groups.io= ; Wu, Hao A <hao.a.wu@intel.com>; Bassa, Damian <damian.b= assa@intel.com>; Ni, Ray <ray= .ni@intel.com>
Subject: RE: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator= to check for RCiEP before looking for RP

 

From: devel@edk2.groups.io <devel= @edk2.groups.io> On Behalf Of Wu, Hao A
Sent: Tuesday, August 31, 2021 12:25 PM
To: devel@edk2.groups.io= ; Bassa, Damian <damian.bassa@= intel.com>
Subject: Re: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator= to check for RCiEP before looking for RP

 

Really sorry,

 

Could you help to provide more information on the be= low statement?

“undefined parent register accesses”

 

Thanks in advance.

 

Best Regards,

Hao Wu

 

From: devel@edk2.groups.io <devel= @edk2.groups.io> On Behalf Of Bassa, Damian
Sent: Tuesday, August 24, 2021 11:15 PM
To: devel@edk2.groups.io=
Subject: [edk2-devel] [PATCH] MdeModulePkg/PciBusDxe: Enumerator to = check for RCiEP before looking for RP

 

Before trying to access parent root port to check AR= I capabilities,

enumerator should see if Endpoint device is not Root= Complex integrated

to avoid undefined parent register accesses in these= cases.

 

Signed-off-by: Damian Bassa damian.bassa@intel.com

 

---

.../Bus/Pci/PciBusDxe/PciEnumeratorSupport.c &n= bsp;       | 12 +++++++++++-

1 file changed, 11 insertions(+), 1 deletion(-)=

 

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnume= ratorSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSupport.c=

index db1b35f8ef..6451fb8af9 100644

--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu= pport.c

+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciEnumeratorSu= pport.c

@@ -2153,6 +2153,7 @@ CreatePciIoDevice (=

   PCI_IO_DEVICE    &n= bsp;   *PciIoDevice;

   EFI_PCI_IO_PROTOCOL  *PciIo;<= /o:p>

   EFI_STATUS     &nbs= p;     Status;

+  PCI_REG_PCIE_CAPABILITY Capability;

 

   PciIoDevice =3D AllocateZeroPool (= sizeof (PCI_IO_DEVICE));

   if (PciIoDevice =3D=3D NULL) {

@@ -2229,7 +2230,16 @@ CreatePciIoDevice (

     return NULL;

   }

 

-  if (PcdGetBool (PcdAriSupport)) {=

+  PciIo->Pci.Read (

+        &nb= sp;       PciIo,

+        &nb= sp;       EfiPciIoWidthUint16,

+        &nb= sp;       PciIoDevice->PciExpressCapabilit= yOffset + OFFSET_OF (PCI_CAPABILITY_PCIEXP, Capability),

+        &nb= sp;       1,

+        &nb= sp;       &Capability.Uint16

+        &nb= sp;       );

+

+  if (PcdGetBool (PcdAriSupport) &&

+    Capability.Bits.DevicePortType != =3D PCIE_DEVICE_PORT_TYPE_ROOT_COMPLEX_INTEGRATED_ENDPOINT) {

     //

     // Check if the device is a= n ARI device.

     //

--

2.27.0.windows.1

 

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