Re: [PATCH v1 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change Bitwidth During Static Paging

["Ni, Ray" <ray.ni@intel.com>]

Is it possible to let SetStaticPageTable() accept another parameter "PhysicalAddressBits" so it doesn't update the global one?
Using this way, SetStaticPageTable() can avoid reference the global variable completely.

> -----Original Message-----
> From: Kun Qin <kuqin12@gmail.com>
> Sent: Wednesday, April 14, 2021 10:59 AM
> To: devel@edk2.groups.io
> Cc: Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo
> Ersek <lersek@redhat.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>
> Subject: [PATCH v1 1/1] UefiCpuPkg: PiSmmCpuDxeSmm: Not to Change
> Bitwidth During Static Paging
> 
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3300
> 
> Current implementation of SetStaticPageTable routine in PiSmmCpuDxeSmm
> driver will check a global variable mPhysicalAddressBits, and eventually
> cap any value larger than 39 at 39.
> 
> This global variable is used in ConvertMemoryPageAttributes, which backs
> SmmSetMemoryAttributes and SmmClearMemoryAttributes. Thus for a
> processor
> that supports more than 39 bits width, trying to mark page table regions
> higher than 39-bit will always return EFI_UNSUPPROTED.
> 
> This change replaced the changed bitwidth to a stack based variable.
> 
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> 
> Signed-off-by: Kun Qin <kuqin12@gmail.com>
> ---
>  UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c | 25 +++++++++++---------
>  1 file changed, 14 insertions(+), 11 deletions(-)
> 
> diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> index 6902584b1fbd..0caee8a27abe 100644
> --- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/PageTbl.c
> @@ -226,6 +226,7 @@ SetStaticPageTable (
>    UINTN                                         IndexOfPml4Entries;
>    UINTN                                         IndexOfPdpEntries;
>    UINTN                                         IndexOfPageDirectoryEntries;
> +  UINT64                                        PhysicalAddressBits;
>    UINT64                                        *PageMapLevel5Entry;
>    UINT64                                        *PageMapLevel4Entry;
>    UINT64                                        *PageMap;
> @@ -237,26 +238,28 @@ SetStaticPageTable (
>    // IA-32e paging translates 48-bit linear addresses to 52-bit physical
> addresses
>    //  when 5-Level Paging is disabled.
>    //
> -  ASSERT (mPhysicalAddressBits <= 52);
> -  if (!m5LevelPagingNeeded && mPhysicalAddressBits > 48) {
> -    mPhysicalAddressBits = 48;
> +  PhysicalAddressBits = mPhysicalAddressBits;
> +
> +  ASSERT (PhysicalAddressBits <= 52);
> +  if (!m5LevelPagingNeeded && PhysicalAddressBits > 48) {
> +    PhysicalAddressBits = 48;
>    }
> 
>    NumberOfPml5EntriesNeeded = 1;
> -  if (mPhysicalAddressBits > 48) {
> -    NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1,
> mPhysicalAddressBits - 48);
> -    mPhysicalAddressBits = 48;
> +  if (PhysicalAddressBits > 48) {
> +    NumberOfPml5EntriesNeeded = (UINTN) LShiftU64 (1,
> PhysicalAddressBits - 48);
> +    PhysicalAddressBits = 48;
>    }
> 
>    NumberOfPml4EntriesNeeded = 1;
> -  if (mPhysicalAddressBits > 39) {
> -    NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1,
> mPhysicalAddressBits - 39);
> -    mPhysicalAddressBits = 39;
> +  if (PhysicalAddressBits > 39) {
> +    NumberOfPml4EntriesNeeded = (UINTN) LShiftU64 (1,
> PhysicalAddressBits - 39);
> +    PhysicalAddressBits = 39;
>    }
> 
>    NumberOfPdpEntriesNeeded = 1;
> -  ASSERT (mPhysicalAddressBits > 30);
> -  NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1,
> mPhysicalAddressBits - 30);
> +  ASSERT (PhysicalAddressBits > 30);
> +  NumberOfPdpEntriesNeeded = (UINTN) LShiftU64 (1, PhysicalAddressBits
> - 30);
> 
>    //
>    // By architecture only one PageMapLevel4 exists - so lets allocate storage
> for it.
> --
> 2.31.0.windows.1