From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.1180.1610698308937024623 for ; Fri, 15 Jan 2021 00:11:49 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@intel.onmicrosoft.com header.s=selector2-intel-onmicrosoft-com header.b=emhEiqJS; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: ray.ni@intel.com) IronPort-SDR: T2QW2xwSRgN+Ac2sDFJ9yUuK50nslSDi8Zq8RGNzoWazGHWjV6O6ni6Rhl6iUSayyU3AIvRZCm fLB6ld43m96A== X-IronPort-AV: E=McAfee;i="6000,8403,9864"; a="178665640" X-IronPort-AV: E=Sophos;i="5.79,348,1602572400"; d="scan'208,217";a="178665640" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 15 Jan 2021 00:11:46 -0800 IronPort-SDR: 73jq+RVf1yif5UbUs69ydnOqq3/MkCFx2joSzn58zjMogcalgyiROpDyUUKvRwLqfXixVwBadz hwOEizjav3nQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,348,1602572400"; d="scan'208,217";a="572558054" Received: from orsmsx606.amr.corp.intel.com ([10.22.229.19]) by fmsmga005.fm.intel.com with ESMTP; 15 Jan 2021 00:11:45 -0800 Received: from orsmsx605.amr.corp.intel.com (10.22.229.18) by ORSMSX606.amr.corp.intel.com (10.22.229.19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Fri, 15 Jan 2021 00:11:45 -0800 Received: from ORSEDG601.ED.cps.intel.com (10.7.248.6) by orsmsx605.amr.corp.intel.com (10.22.229.18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5 via Frontend Transport; Fri, 15 Jan 2021 00:11:45 -0800 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (104.47.56.168) by edgegateway.intel.com (134.134.137.102) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.1713.5; Fri, 15 Jan 2021 00:11:45 -0800 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ajoUkSEXYEo8n4l9Z7GGZVbmgQ85hL2AyAHspP8L8nLZNXeTLO9K9nTKIsJmDCSzyS27mFtkqu1y5NjRTRSbtysgMszrroSqwftNAPhTj3OpDoZGRT6y+Jz463dmpKbEgT+2wFyrg+ONW6MftSZeQwP9FzzJIQFLY4iYnORLfCf6qx5/eauwWxGV/wr6q2TQXZjQSFcqsttvhPoz830DdhYYkaOnq3o4mexFbIbqKq8PtLLpMg4m7Sxidq+R1Sz0sTciPz+aTx6jtrdwWCVD+3jlk8MPkWQd760mE56os+z5xXXAjnftcBxWrjeOheHqsIsP0YN2+6zhIyLtcQDyeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b2Kznh14P3yDrZz/kbBGrFZowhTcPkx2nzwuN8TskIY=; b=cFCMb+1KczMGZ+eW9Gcda2QvuWnFtt1mYkmJwQFewh+hVTyDSatTKdM14oLSR5boRYp4nhk2xsn5S8lsnsmrBO7WXFCs8Ki60EittxAcFyd8okqfcdlKWTnUHpPgqfr0q5R2laYqSI60X0L75JtoEdQAkPyoFz4OSTSvFVYKBb9c05wWqWm4knqfhteK+VyZhm5kNto+l5hoyHcq2TIJ+Fkn1m2LKyDbt4XOYQmUSI3iLEN7uXf0tlWDLzKf5R7oOO7z1oHuaOKhwTfIKCxmDw8oSkkyvRT2BJdu4eAGJdu149XUcbIwO7s01wowo5VINECCrFidzWmJxSrSoPNFJw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=intel.onmicrosoft.com; s=selector2-intel-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=b2Kznh14P3yDrZz/kbBGrFZowhTcPkx2nzwuN8TskIY=; b=emhEiqJS4bPCS+v55EfBM/5d22DdF9LgdBcsgsomCG6e7ogNm1IRqFVJ6Mffd1Am7vD4eNXMRXVX+s+BHb9h7wNHvrT5KH3Z99hqA9/c9RYzgvq1q03makSs9vqJCpraJPzevoyMOqeL+coK50znbescGt8WpuABRWkiFZ2u/MU= Received: from CO1PR11MB4930.namprd11.prod.outlook.com (2603:10b6:303:9b::11) by MW3PR11MB4585.namprd11.prod.outlook.com (2603:10b6:303:52::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3763.11; Fri, 15 Jan 2021 08:11:44 +0000 Received: from CO1PR11MB4930.namprd11.prod.outlook.com ([fe80::d18:1234:c1d6:5936]) by CO1PR11MB4930.namprd11.prod.outlook.com ([fe80::d18:1234:c1d6:5936%7]) with mapi id 15.20.3763.010; Fri, 15 Jan 2021 08:11:44 +0000 From: "Ni, Ray" To: "Zhong, Zarcd" CC: "Wu, Hao A" , "Kinney, Michael D" , "devel@edk2.groups.io" , "Kim, Andrew" Subject: Re: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in high 32bit of MEM64. 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Hi Ray, Your suggestion for one line patch test PASS. Attached file is the patch. Please help to review. From: Kim, Andrew > Sent: Friday, January 15, 2021 3:53 PM To: Zhong, Zarcd > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Zarcd, It works fine with this Ray's solution. Customer confirmed it. -Andrew From: Kim, Andrew Sent: Thursday, January 14, 2021 10:14 AM To: Zhong, Zarcd > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. BTW, to be clear for this to try. Could you confirm if this is right update with your suggestion? if (EFI_ERROR (Status)) { PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; return Offset + 4; } -Andrew From: Kim, Andrew Sent: Thursday, January 14, 2021 9:38 AM To: Zhong, Zarcd > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Zarcd, Thanks for this update. Sure, I will let you know once it has been verified. -Andrew From: Zhong, Zarcd > Sent: Wednesday, January 13, 2021 10:32 PM To: Kim, Andrew > Cc: Wu, Hao A >; Kinney, Mich= ael D >; deve= l@edk2.groups.io; Ni, Ray > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Kim, Ray suggests a one line patch instead of google's solution. + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; Could you help to verify Ray's solution on that card? From: Ni, Ray > Sent: Thursday, January 14, 2021 1:59 PM To: Zhong, Zarcd >; dev= el@edk2.groups.io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Zarcd, I may not say very clearly. I prefer to just keep below line. Can you check= whether that can work? + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; Thanks, Ray From: Zhong, Zarcd > Sent: Thursday, January 14, 2021 10:48 AM To: Ni, Ray >; devel@edk2.groups.= io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Hi Ray, Attached patch is updated with below add. Thanks for your remind. PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown; From: Ni, Ray > Sent: Wednesday, January 13, 2021 3:01 PM To: Zhong, Zarcd >; dev= el@edk2.groups.io Cc: Wu, Hao A >; Kinney, Mich= ael D > Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail= in high 32bit of MEM64. Zarcd, I can understand that this patch is needed for some buggy pci devices whose VF bar behaves strangely. Incompatible PCI protocol can only deal with norm= al PCI bar. And this patch is just to enhance the error handling logic. Can you please use below code for error handling? + PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown I understand that your change is aligned to existing error handling in the = beginning of PciIovParseVfBar(). But that logic runs before PciIoDevice->VfPciBar[BarIndex].BarType is assig= ned. The key is to reset the BarType to PciBarTypeUnknown so that the resource s= ummary code doesn't count this bar. Thanks, Ray From: Zhong, Zarcd > Sent: Monday, January 4, 2021 5:48 PM To: devel@edk2.groups.io Cc: Ni, Ray >; Wu, Hao A > Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in = high 32bit of MEM64. >>From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Sep 17 00:00:00 2001 From: Zarcd Zhong > Date: Mon, 4 Jan 2021 17:32:54 +0800 Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing fail in = high 32bit of MEM64. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3149 Clear length and alignment for low 32bit of MEM64 BAR if sizing fail in= high 32bit. Cc: Ray Ni > Cc: Hao A Wu > --_000_CO1PR11MB4930CEF39FB380F26730DAD68CA70CO1PR11MB4930namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Reviewed-by: Ray Ni <ray.ni@intel.com>

 

From: Zhong, Zarcd <zarcd.zhong@intel.com&= gt;
Sent: Friday, January 15, 2021 4:11 PM
To: Ni, Ray <ray.ni@intel.com>
Cc: Wu, Hao A <hao.a.wu@intel.com>; Kinney, Michael D <mich= ael.d.kinney@intel.com>; devel@edk2.groups.io; Kim, Andrew <andrew.ki= m@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Ray,

 

  Your suggestion for one line patch test PASS.=   

 

Attached file is the patch. Please help to review. <= o:p>

 

From: Kim, Andrew <andrew.kim@intel.com>
Sent: Friday, January 15, 2021 3:53 PM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Zarcd,

 

It works fine with this Ray’s solution. Custom= er confirmed it.

 

-Andrew

 

From: Kim, Andrew
Sent: Thursday, January 14, 2021 10:14 AM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

BTW, to be clear for this to try.

Could you confirm if this is right update with your = suggestion?

 

 

      if (EFI_ERROR (Status= )) {

        PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBarTypeU= nknown;

 

        return Of= fset + 4;

      }

 

 

-Andrew

 

From: Kim, Andrew
Sent: Thursday, January 14, 2021 9:38 AM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Zarcd,

 

Thanks for this update.

 

Sure, I will let you know once it has been verified.=

 

-Andrew

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Wednesday, January 13, 2021 10:32 PM
To: Kim, Andrew <andrew.k= im@intel.com>
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>; devel@edk2.groups.io; Ni, Ray &= lt;ray.ni@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Kim,

 

Ray suggests  a one line patch instead of googl= e’s solution.

+        PciIoDev= ice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown;

 

Could you help to verify Ray’s solution on tha= t card?

 

 

 

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Thursday, January 14, 2021 1:59 PM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Zarcd,

I may not say very clearly. I prefer to just keep be= low line. Can you check whether that can work?

+        PciIoDev= ice->VfPciBar[BarIndex].BarType =3D PciBarTypeUnknown;

 

Thanks,
Ray

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Thursday, January 14, 2021 10:48 AM
To: Ni, Ray <ray.ni@intel.com= >; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Hi Ray,

 

Attached patch is updated with below add. Thanks for= your remind.

 

PciIoDevice->VfPciBar[BarIndex].BarType =3D PciBa= rTypeUnknown;

 

 

From: Ni, Ray <ray.ni@intel.com>
Sent: Wednesday, January 13, 2021 3:01 PM
To: Zhong, Zarcd <zarcd.= zhong@intel.com>; devel@edk2.groups.io
Cc: Wu, Hao A <hao.a.wu@int= el.com>; Kinney, Michael D <michael.d.kinney@intel.com>
Subject: RE: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizi= ng fail in high 32bit of MEM64.

 

Zarcd,

I can understand that this patch is needed for some = buggy pci devices whose
VF bar behaves strangely. Incompatible PCI protocol can only deal with norm= al
PCI bar. And this patch is just to enhance the error handling logic.

 

Can you please use below code for error handling?

+        PciIoDev= ice->VfPciBar[BarIndex].BarType     =3D PciBarTypeUn= known

 

I understand that your change is aligned to existing= error handling in the beginning
of PciIovParseVfBar().

But that logic runs before PciIoDevice->VfPciBar[= BarIndex].BarType is assigned.

The key is to reset the BarType to PciBarTypeUnknown= so that the resource summary
code doesn’t count this bar.

 

Thanks,

Ray

 

From: Zhong, Zarcd <zarcd.zhong@intel.com>
Sent: Monday, January 4, 2021 5:48 PM
To: devel@edk2.groups.io=
Cc: Ni, Ray <ray.ni@intel.com= >; Wu, Hao A <hao.a.wu@inte= l.com>
Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Handle BAR sizing f= ail in high 32bit of MEM64.

 

From 7518212a85269e486d06dcea927a3d34e23372c2 Mon Se= p 17 00:00:00 2001

From: Zarcd Zhong <zarcd.zhong@intel.com>

Date: Mon, 4 Jan 2021 17:32:54 +0800

Subject: [PATCH] MdeModulePkg/Bus/Pci/PciBusDxe: Han= dle BAR sizing fail in high 32bit of MEM64.

 

    REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3149

 

    Clear length and alignment for lo= w 32bit of MEM64 BAR if sizing fail in high 32bit.

 

    Cc: Ray Ni <ray.ni@intel.com>

    Cc: Hao A Wu <hao.a.wu@intel.com>

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