From: "Ni, Ray" <ray.ni@intel.com>
To: "Lou, Yun" <yun.lou@intel.com>,
"devel@edk2.groups.io" <devel@edk2.groups.io>
Cc: "Dong, Eric" <eric.dong@intel.com>,
Laszlo Ersek <lersek@redhat.com>,
"Kumar, Rahul1" <rahul1.kumar@intel.com>
Subject: Re: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type
Date: Tue, 16 Mar 2021 03:39:42 +0000 [thread overview]
Message-ID: <CO1PR11MB4930E7C99987813DA163CB798C6B9@CO1PR11MB4930.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20210315134854.6363-1-yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
> -----Original Message-----
> From: Lou, Yun <yun.lou@intel.com>
> Sent: Monday, March 15, 2021 9:49 PM
> To: devel@edk2.groups.io
> Cc: Lou, Yun <yun.lou@intel.com>; Ni, Ray <ray.ni@intel.com>; Dong, Eric
> <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul1
> <rahul1.kumar@intel.com>
> Subject: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative
> type
>
> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3265
>
> Support collecting cache associative type in CpuCacheInfoLib.
> This prevents the user from using additional code to obtain the
> same information.
>
> Signed-off-by: Jason Lou <yun.lou@intel.com>
> Cc: Ray Ni <ray.ni@intel.com>
> Cc: Eric Dong <eric.dong@intel.com>
> Cc: Laszlo Ersek <lersek@redhat.com>
> Cc: Rahul Kumar <rahul1.kumar@intel.com>
> ---
> UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 49
> +++++++++++---------
> UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 15 +++++-
> UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 15 +++++-
> 3 files changed, 53 insertions(+), 26 deletions(-)
>
> diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
> b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
> index d46fb0425851..126ee0da86fc 100644
> --- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
> +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c
> @@ -1,7 +1,7 @@
> /** @file
>
> Provides cache info for each package, core type, cache level and cache type.
>
>
>
> - Copyright (c) 2020 Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> **/
>
> @@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable (
> {
>
> UINTN Index;
>
>
>
> - DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------
> ------------------------+\n"));
>
> - DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType
> CacheWays CacheSizeinKB CacheCount |\n"));
>
> - DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------
> ------------------------+\n"));
>
> + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------------------
> --------------------------------+\n"));
>
> + DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType
> CacheWays (FA|DM) CacheSizeinKB CacheCount |\n"));
>
> + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------------------
> --------------------------------+\n"));
>
>
>
> for (Index = 0; Index < CpuCacheInfoCount; Index++) {
>
> - DEBUG ((DEBUG_INFO, "| %4x
> | %4x %2x %2x %2x %4x %8x %4x |\n", Index,
>
> - CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType,
> CpuCacheInfo[Index].CacheLevel,
>
> - CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays,
> CpuCacheInfo[Index].CacheSizeinKB,
>
> - CpuCacheInfo[Index].CacheCount));
>
> + DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x %4x
> ( %x| %x) %8x %4x |\n",
>
> + Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType,
> CpuCacheInfo[Index].CacheLevel,
>
> + CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays,
> CpuCacheInfo[Index].FullyAssociativeCache,
>
> + CpuCacheInfo[Index].DirectMappedCache,
> CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount));
>
> }
>
>
>
> - DEBUG ((DEBUG_INFO, "+-------+-------------------------------------------------------
> ------------------------+\n"));
>
> + DEBUG ((DEBUG_INFO, "+-------+------------------------------------------------------
> --------------------------------+\n"));
>
> }
>
>
>
> /**
>
> @@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData (
> CPUID_CACHE_PARAMS_EAX CacheParamEax;
>
> CPUID_CACHE_PARAMS_EBX CacheParamEbx;
>
> UINT32 CacheParamEcx;
>
> + CPUID_CACHE_PARAMS_EDX CacheParamEdx;
>
> CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX
> NativeModelIdAndCoreTypeEax;
>
> COLLECT_CPUID_CACHE_DATA_CONTEXT *Context;
>
> CPUID_CACHE_DATA *CacheData;
>
> @@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData (
> CacheParamLeafIndex = 0;
>
>
>
> while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) {
>
> - AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex,
> &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL);
>
> + AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex,
> &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx,
> &CacheParamEdx.Uint32);
>
>
>
> if (CacheParamEax.Bits.CacheType == 0) {
>
> break;
>
> }
>
>
>
> - CacheData[CacheParamLeafIndex].CacheLevel =
> (UINT8)CacheParamEax.Bits.CacheLevel;
>
> - CacheData[CacheParamLeafIndex].CacheType =
> (UINT8)CacheParamEax.Bits.CacheType;
>
> - CacheData[CacheParamLeafIndex].CacheWays =
> (UINT16)CacheParamEbx.Bits.Ways;
>
> - CacheData[CacheParamLeafIndex].CacheShareBits =
> (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
>
> - CacheData[CacheParamLeafIndex].CacheSizeinKB =
> (CacheParamEbx.Bits.Ways + 1) *
>
> + CacheData[CacheParamLeafIndex].CacheLevel =
> (UINT8)CacheParamEax.Bits.CacheLevel;
>
> + CacheData[CacheParamLeafIndex].CacheType =
> (UINT8)CacheParamEax.Bits.CacheType;
>
> + CacheData[CacheParamLeafIndex].CacheWays =
> (UINT16)CacheParamEbx.Bits.Ways;
>
> + CacheData[CacheParamLeafIndex].FullyAssociativeCache =
> (UINT8)CacheParamEax.Bits.FullyAssociativeCache;
>
> + CacheData[CacheParamLeafIndex].DirectMappedCache =
> (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing;
>
> + CacheData[CacheParamLeafIndex].CacheShareBits =
> (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors;
>
> + CacheData[CacheParamLeafIndex].CacheSizeinKB =
> (CacheParamEbx.Bits.Ways + 1) *
>
> (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.LineSize + 1)
> * (CacheParamEcx + 1) / SIZE_1KB;
>
>
>
> CacheParamLeafIndex++;
>
> @@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData (
> if (CacheInfoIndex == LocalCacheInfoCount) {
>
> ASSERT (LocalCacheInfoCount < MaxCacheInfoCount);
>
>
>
> - LocalCacheInfo[LocalCacheInfoCount].Package = ProcessorInfo[Index /
> MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
>
> - LocalCacheInfo[LocalCacheInfoCount].CoreType = ProcessorInfo[Index /
> MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
>
> - LocalCacheInfo[LocalCacheInfoCount].CacheLevel =
> CacheData[Index].CacheLevel;
>
> - LocalCacheInfo[LocalCacheInfoCount].CacheType =
> CacheData[Index].CacheType;
>
> - LocalCacheInfo[LocalCacheInfoCount].CacheWays =
> CacheData[Index].CacheWays;
>
> - LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =
> CacheData[Index].CacheSizeinKB;
>
> - LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
>
> + LocalCacheInfo[LocalCacheInfoCount].Package =
> ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package;
>
> + LocalCacheInfo[LocalCacheInfoCount].CoreType =
> ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType;
>
> + LocalCacheInfo[LocalCacheInfoCount].CacheLevel =
> CacheData[Index].CacheLevel;
>
> + LocalCacheInfo[LocalCacheInfoCount].CacheType =
> CacheData[Index].CacheType;
>
> + LocalCacheInfo[LocalCacheInfoCount].CacheWays =
> CacheData[Index].CacheWays;
>
> + LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache =
> CacheData[Index].FullyAssociativeCache;
>
> + LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache =
> CacheData[Index].DirectMappedCache;
>
> + LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =
> CacheData[Index].CacheSizeinKB;
>
> + LocalCacheInfo[LocalCacheInfoCount].CacheCount = 1;
>
>
>
> LocalCacheInfoCount++;
>
> }
>
> diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
> b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
> index a7f29b188775..a66152bce009 100644
> --- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
> +++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h
> @@ -1,7 +1,7 @@
> /** @file
>
> Header file for CPU Cache info Library.
>
>
>
> - Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> **/
>
> @@ -33,7 +33,18 @@ typedef struct {
> // Ways of associativity.
>
> // Value = CPUID.04h:EBX[31:22]
>
> //
>
> - UINT16 CacheWays;
>
> + UINT16 CacheWays : 10;
>
> + //
>
> + // Fully associative cache.
>
> + // Value = CPUID.04h:EAX[09]
>
> + //
>
> + UINT16 FullyAssociativeCache : 1;
>
> + //
>
> + // Direct mapped cache.
>
> + // Value = CPUID.04h:EDX[02]
>
> + //
>
> + UINT16 DirectMappedCache : 1;
>
> + UINT16 Reserved : 4;
>
> //
>
> // Size of single cache that this package's this type of logical processor
> corresponds to.
>
> // Value = (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) *
>
> diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
> b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
> index de56db9c0cbe..b6e6ae5bc50a 100644
> --- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
> +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h
> @@ -1,7 +1,7 @@
> /** @file
>
> Internal header file for CPU Cache info Library.
>
>
>
> - Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
>
> + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.<BR>
>
> SPDX-License-Identifier: BSD-2-Clause-Patent
>
>
>
> **/
>
> @@ -52,7 +52,18 @@ typedef struct {
> // Ways of associativity.
>
> // Value = CPUID.04h:EBX[31:22]
>
> //
>
> - UINT16 CacheWays;
>
> + UINT16 CacheWays : 10;
>
> + //
>
> + // Fully associative cache.
>
> + // Value = CPUID.04h:EAX[09]
>
> + //
>
> + UINT16 FullyAssociativeCache : 1;
>
> + //
>
> + // Direct mapped cache.
>
> + // Value = CPUID.04h:EDX[02]
>
> + //
>
> + UINT16 DirectMappedCache : 1;
>
> + UINT16 Reserved : 4;
>
> //
>
> // Cache share bits.
>
> // Value = CPUID.04h:EAX[25:14]
>
> --
> 2.28.0.windows.1
next prev parent reply other threads:[~2021-03-16 3:39 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-15 13:48 [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type Jason Lou
2021-03-16 3:39 ` Ni, Ray [this message]
2021-03-16 14:01 ` Dong, Eric
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-list from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=CO1PR11MB4930E7C99987813DA163CB798C6B9@CO1PR11MB4930.namprd11.prod.outlook.com \
--to=devel@edk2.groups.io \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox