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Tue, 16 Mar 2021 03:39:42 +0000 From: "Ni, Ray" To: "Lou, Yun" , "devel@edk2.groups.io" CC: "Dong, Eric" , Laszlo Ersek , "Kumar, Rahul1" Subject: Re: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type Thread-Topic: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associative type Thread-Index: AQHXGaH59CcyE7PPekKaEinGRuFVM6qF+KcQ Date: Tue, 16 Mar 2021 03:39:42 +0000 Message-ID: References: <20210315134854.6363-1-yun.lou@intel.com> In-Reply-To: <20210315134854.6363-1-yun.lou@intel.com> Accept-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: intel.com; dkim=none (message not signed) header.d=none;intel.com; dmarc=none action=none header.from=intel.com; x-originating-ip: [192.198.147.194] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f660c164-7ffe-465d-cda4-08d8e82d22cb x-ms-traffictypediagnostic: MWHPR11MB1519: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:7691; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Reviewed-by: Ray Ni > -----Original Message----- > From: Lou, Yun > Sent: Monday, March 15, 2021 9:49 PM > To: devel@edk2.groups.io > Cc: Lou, Yun ; Ni, Ray ; Dong, Eric > ; Laszlo Ersek ; Kumar, Rahul1 > > Subject: [PATCH v2 1/1] UefiCpuPkg/CpuCacheInfoLib: Collect cache associa= tive > type >=20 > REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3265 >=20 > Support collecting cache associative type in CpuCacheInfoLib. > This prevents the user from using additional code to obtain the > same information. >=20 > Signed-off-by: Jason Lou > Cc: Ray Ni > Cc: Eric Dong > Cc: Laszlo Ersek > Cc: Rahul Kumar > --- > UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c | 49 > +++++++++++--------- > UefiCpuPkg/Include/Library/CpuCacheInfoLib.h | 15 +++++- > UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h | 15 +++++- > 3 files changed, 53 insertions(+), 26 deletions(-) >=20 > diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c > b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c > index d46fb0425851..126ee0da86fc 100644 > --- a/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c > +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/CpuCacheInfoLib.c > @@ -1,7 +1,7 @@ > /** @file >=20 > Provides cache info for each package, core type, cache level and cache= type. >=20 >=20 >=20 > - Copyright (c) 2020 Intel Corporation. All rights reserved.
>=20 > + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -23,18 +23,18 @@ CpuCacheInfoPrintCpuCacheInfoTable ( > { >=20 > UINTN Index; >=20 >=20 >=20 > - DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= --------------- > ------------------------+\n")); >=20 > - DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType > CacheWays CacheSizeinKB CacheCount |\n")); >=20 > - DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= --------------- > ------------------------+\n")); >=20 > + DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= -------------- > --------------------------------+\n")); >=20 > + DEBUG ((DEBUG_INFO, "| Index | Packge CoreType CacheLevel CacheType > CacheWays (FA|DM) CacheSizeinKB CacheCount |\n")); >=20 > + DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= -------------- > --------------------------------+\n")); >=20 >=20 >=20 > for (Index =3D 0; Index < CpuCacheInfoCount; Index++) { >=20 > - DEBUG ((DEBUG_INFO, "| %4x > | %4x %2x %2x %2x %4x %8x %4x = |\n", Index, >=20 > - CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType, > CpuCacheInfo[Index].CacheLevel, >=20 > - CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, > CpuCacheInfo[Index].CacheSizeinKB, >=20 > - CpuCacheInfo[Index].CacheCount)); >=20 > + DEBUG ((DEBUG_INFO, "| %4x | %4x %2x %2x %2x = %4x > ( %x| %x) %8x %4x |\n", >=20 > + Index, CpuCacheInfo[Index].Package, CpuCacheInfo[Index].CoreType= , > CpuCacheInfo[Index].CacheLevel, >=20 > + CpuCacheInfo[Index].CacheType, CpuCacheInfo[Index].CacheWays, > CpuCacheInfo[Index].FullyAssociativeCache, >=20 > + CpuCacheInfo[Index].DirectMappedCache, > CpuCacheInfo[Index].CacheSizeinKB, CpuCacheInfo[Index].CacheCount)); >=20 > } >=20 >=20 >=20 > - DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= --------------- > ------------------------+\n")); >=20 > + DEBUG ((DEBUG_INFO, "+-------+----------------------------------------= -------------- > --------------------------------+\n")); >=20 > } >=20 >=20 >=20 > /** >=20 > @@ -160,6 +160,7 @@ CpuCacheInfoCollectCoreAndCacheData ( > CPUID_CACHE_PARAMS_EAX CacheParamEax; >=20 > CPUID_CACHE_PARAMS_EBX CacheParamEbx; >=20 > UINT32 CacheParamEcx; >=20 > + CPUID_CACHE_PARAMS_EDX CacheParamEdx; >=20 > CPUID_NATIVE_MODEL_ID_AND_CORE_TYPE_EAX > NativeModelIdAndCoreTypeEax; >=20 > COLLECT_CPUID_CACHE_DATA_CONTEXT *Context; >=20 > CPUID_CACHE_DATA *CacheData; >=20 > @@ -185,17 +186,19 @@ CpuCacheInfoCollectCoreAndCacheData ( > CacheParamLeafIndex =3D 0; >=20 >=20 >=20 > while (CacheParamLeafIndex < MAX_NUM_OF_CACHE_PARAMS_LEAF) { >=20 > - AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, > &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, NULL); >=20 > + AsmCpuidEx (CPUID_CACHE_PARAMS, CacheParamLeafIndex, > &CacheParamEax.Uint32, &CacheParamEbx.Uint32, &CacheParamEcx, > &CacheParamEdx.Uint32); >=20 >=20 >=20 > if (CacheParamEax.Bits.CacheType =3D=3D 0) { >=20 > break; >=20 > } >=20 >=20 >=20 > - CacheData[CacheParamLeafIndex].CacheLevel =3D > (UINT8)CacheParamEax.Bits.CacheLevel; >=20 > - CacheData[CacheParamLeafIndex].CacheType =3D > (UINT8)CacheParamEax.Bits.CacheType; >=20 > - CacheData[CacheParamLeafIndex].CacheWays =3D > (UINT16)CacheParamEbx.Bits.Ways; >=20 > - CacheData[CacheParamLeafIndex].CacheShareBits =3D > (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors; >=20 > - CacheData[CacheParamLeafIndex].CacheSizeinKB =3D > (CacheParamEbx.Bits.Ways + 1) * >=20 > + CacheData[CacheParamLeafIndex].CacheLevel =3D > (UINT8)CacheParamEax.Bits.CacheLevel; >=20 > + CacheData[CacheParamLeafIndex].CacheType =3D > (UINT8)CacheParamEax.Bits.CacheType; >=20 > + CacheData[CacheParamLeafIndex].CacheWays =3D > (UINT16)CacheParamEbx.Bits.Ways; >=20 > + CacheData[CacheParamLeafIndex].FullyAssociativeCache =3D > (UINT8)CacheParamEax.Bits.FullyAssociativeCache; >=20 > + CacheData[CacheParamLeafIndex].DirectMappedCache =3D > (UINT8)CacheParamEdx.Bits.ComplexCacheIndexing; >=20 > + CacheData[CacheParamLeafIndex].CacheShareBits =3D > (UINT16)CacheParamEax.Bits.MaximumAddressableIdsForLogicalProcessors; >=20 > + CacheData[CacheParamLeafIndex].CacheSizeinKB =3D > (CacheParamEbx.Bits.Ways + 1) * >=20 > (CacheParamEbx.Bits.LinePartitions + 1) * (CacheParamEbx.Bits.Li= neSize + 1) > * (CacheParamEcx + 1) / SIZE_1KB; >=20 >=20 >=20 > CacheParamLeafIndex++; >=20 > @@ -305,13 +308,15 @@ CpuCacheInfoCollectCpuCacheInfoData ( > if (CacheInfoIndex =3D=3D LocalCacheInfoCount) { >=20 > ASSERT (LocalCacheInfoCount < MaxCacheInfoCount); >=20 >=20 >=20 > - LocalCacheInfo[LocalCacheInfoCount].Package =3D ProcessorInf= o[Index / > MAX_NUM_OF_CACHE_PARAMS_LEAF].Package; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CoreType =3D ProcessorInf= o[Index / > MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CacheLevel =3D > CacheData[Index].CacheLevel; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CacheType =3D > CacheData[Index].CacheType; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CacheWays =3D > CacheData[Index].CacheWays; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =3D > CacheData[Index].CacheSizeinKB; >=20 > - LocalCacheInfo[LocalCacheInfoCount].CacheCount =3D 1; >=20 > + LocalCacheInfo[LocalCacheInfoCount].Package =3D > ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].Package; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CoreType =3D > ProcessorInfo[Index / MAX_NUM_OF_CACHE_PARAMS_LEAF].CoreType; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CacheLevel =3D > CacheData[Index].CacheLevel; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CacheType =3D > CacheData[Index].CacheType; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CacheWays =3D > CacheData[Index].CacheWays; >=20 > + LocalCacheInfo[LocalCacheInfoCount].FullyAssociativeCache =3D > CacheData[Index].FullyAssociativeCache; >=20 > + LocalCacheInfo[LocalCacheInfoCount].DirectMappedCache =3D > CacheData[Index].DirectMappedCache; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CacheSizeinKB =3D > CacheData[Index].CacheSizeinKB; >=20 > + LocalCacheInfo[LocalCacheInfoCount].CacheCount =3D 1; >=20 >=20 >=20 > LocalCacheInfoCount++; >=20 > } >=20 > diff --git a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h > b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h > index a7f29b188775..a66152bce009 100644 > --- a/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h > +++ b/UefiCpuPkg/Include/Library/CpuCacheInfoLib.h > @@ -1,7 +1,7 @@ > /** @file >=20 > Header file for CPU Cache info Library. >=20 >=20 >=20 > - Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -33,7 +33,18 @@ typedef struct { > // Ways of associativity. >=20 > // Value =3D CPUID.04h:EBX[31:22] >=20 > // >=20 > - UINT16 CacheWays; >=20 > + UINT16 CacheWays : 10; >=20 > + // >=20 > + // Fully associative cache. >=20 > + // Value =3D CPUID.04h:EAX[09] >=20 > + // >=20 > + UINT16 FullyAssociativeCache : 1; >=20 > + // >=20 > + // Direct mapped cache. >=20 > + // Value =3D CPUID.04h:EDX[02] >=20 > + // >=20 > + UINT16 DirectMappedCache : 1; >=20 > + UINT16 Reserved : 4; >=20 > // >=20 > // Size of single cache that this package's this type of logical proce= ssor > corresponds to. >=20 > // Value =3D (CPUID.04h:EBX[31:22] + 1) * (CPUID.04h:EBX[21:12] + 1) * >=20 > diff --git a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h > b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h > index de56db9c0cbe..b6e6ae5bc50a 100644 > --- a/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h > +++ b/UefiCpuPkg/Library/CpuCacheInfoLib/InternalCpuCacheInfoLib.h > @@ -1,7 +1,7 @@ > /** @file >=20 > Internal header file for CPU Cache info Library. >=20 >=20 >=20 > - Copyright (c) 2020, Intel Corporation. All rights reserved.
>=20 > + Copyright (c) 2020 - 2021, Intel Corporation. All rights reserved.
>=20 > SPDX-License-Identifier: BSD-2-Clause-Patent >=20 >=20 >=20 > **/ >=20 > @@ -52,7 +52,18 @@ typedef struct { > // Ways of associativity. >=20 > // Value =3D CPUID.04h:EBX[31:22] >=20 > // >=20 > - UINT16 CacheWays; >=20 > + UINT16 CacheWays : 10; >=20 > + // >=20 > + // Fully associative cache. >=20 > + // Value =3D CPUID.04h:EAX[09] >=20 > + // >=20 > + UINT16 FullyAssociativeCache : 1; >=20 > + // >=20 > + // Direct mapped cache. >=20 > + // Value =3D CPUID.04h:EDX[02] >=20 > + // >=20 > + UINT16 DirectMappedCache : 1; >=20 > + UINT16 Reserved : 4; >=20 > // >=20 > // Cache share bits. >=20 > // Value =3D CPUID.04h:EAX[25:14] >=20 > -- > 2.28.0.windows.1